Keysight (Agilent) 4280A Application Note

CONTENTS

1. INTRODUCTION

1. 1 4280A Applications ...........................................

1.2 4280A Features

1. 3 C-V Characteristics of MOS Structures and pn Junctions

1.4 Wafer Capacitance Measurements

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1
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3

EVALUATION OF C-V/G-V CHARACTERISTICS

2.

2. 1 C-V Measurement

2. 2 How to Calculate Semiconductor Parameters

3. C-t CHARACTERISTICS and ZERBST ANALYSIS

3. 1 C-t Measurement (1) C-t Measurement Using Internal Bias Source (2) C-t Measurement Using External Bias Source

3.2 Zerbst Analysis

4. DOPING PROFILE EVALUATION

4. 1

( 4280A Technical Information )

(Appendixes)

I.

lI. Connection Mode (CONN MODE)

III.

Doping Profile Measurement

l

Internal Bias Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

l

Sampling Mode Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

......................................................

Evaluation of pn Junction Capacitance Characteristics

SamplePrograms ................................................

(1) C-V Measurement Program

C-t Measurement Program

(2)

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4280A IMHz C METER/C-V PLOTTER

1. INTRODUCTION

, 1. 1 4280A Applications

The HP model 4280A 1MHz C Meter/C-V Plotter is de­signed to measure the high-frequency Capacitance-Voltage
(C-V) and Capacitance-time (C-t) characteristics of semi-

conductor devices and materials. When testing Metal-Oxide
Semiconductors (MOS) or bipolar transistors, the 4280A
provides fully automatic measurements with improved

speed and accuracy. The 4280A is ideally suited for wafer

process evaluation and for development of new semicon-

ductor devices.

This Application Note explains how to perform reliable

C-V and C-t characteristics measurements on semicon-

ductor wafers using the 4280A. This note also contains a

procedure for calculating other semiconductor parameters

from measured C-V or C-t characteristics.

1. 2 4280A Features

n

High Accuracy and High Resolution

The 4280A measures Capacitance (C) and Conductance

(G) with 0.1% accuracy and maximum 4-l/2-digit display

resolution (5l/2-digit resolution with opt. 001). The test

frequency is fiied at 1 MHz.

ment is only lps, so the C-t characteristics of semicon­ductors having slow or fast transient properties, can be
obtained easily. C-t measurements can be used in Zerbst
analysis to calculate the minority carrier lifetime and sur-

face generation velocity. Measured C-t values are also used

to calculate deep-level traps.

n

Automatic System Applications

Measurements, analysis, and plotting can be performed

automatically using the HP-IB. The 4280A outputs meas-

ured values in either of two formats: ASCII, or for fast

dats output, binary code.
Data measured at each bias point during a sweep are

stored in the 4280A’s measurement data buffer. All stored

data are then transfered to the controller at one time
(block-data output) when the sweep ends. Block-data
output reduces measurement time significantly.

The 4280A’s SYNC OUTPUT and EXT TRIGGER are
used to synchronize the 4280A with peripheral equip­ment, such as bias sources or thermal controllers. A

recorder output is also provided for hard copy analog
plotters. These features make the HP 4280A an ideal ele-

ment for automatic C-t or B-T (Bias Temperature) systems.

The 4280A’s CABLE LENGTH CAL capability provides
compensation for residuals of the external cables. ZERO
OPEN provides compensation for parallel capacitance

and conductance in the test fixture. The 4280A’s two-

terminal pair measurement method virtually eliminates

the effects of external noise. All of these 4280A features
combine to provide capability for precision C and G

measurements.

n

C-V and G-V Measurement Versatility Covers Most
Semiconductor Applications

The internal DC bias source can be set to from -lOOV to
+lOOV with 1mV (3-digit) resolution and 0.1% accuracy.
Even minute changes in the C-V or G-V characteristics
of a device can be measured accurately.

Automatic swept bias measurements are made by setting
START V, STOP V, and STEP V. To allow the device
under test to reach stability, HOLD TIME and STEP DE­LAY TIME can also be set. This means that device charac­teristics are obtained after the device has attained thermal
equilibrium. The 4280A’s measurement accuracy insures
accurate calculation of device parameters such as flat band
voltage (Vfb) and minority carrier lifetime.

Table l-l. 4280A Key Specifications

Measurement C-G : C, G, C-G

Function c-t : c-t, G-t ,

Test Signal

Frequency : 1 MHz f 0.01 %
OSC Level : lOmVrms, 30mVrms *lot

C . G-t

Function : :,/,A,>,
output : 0 - +lOOV, 3 digits

Internal DC

Bias Source

Range
Resolution : 1 mV (max)
Basic : 0.1%

Accuracy

Time *l lo/&- 32s

Sweep Range *2(X number of measurement points)

Measurement C : 1fF - 1.9 nF

Range G : 10nS -12mS

Basic Accuracy 0.1 %

and Display
Digits

4-l/2 digits max.
(with opt. 001 C : 5-l/2 digits)

*l : Using an external bias source
** : Max number of measurement points is 9999.

n

Easy-to-Obtain C-t Characteristics

When performing C-t measurements, the 428OA’s measure­ment time interval (td) can be set from 10~s (with an ex­ternal bias source) to 32s, with 10~s resolution and 0.02%

accuracy. The response time for a capacitance measure-

I -

1. 3 C-V Characteristics of MOS Structures and pn Junctions

Doping profile, flat band voltage (Vfb), and threshold
voltage (Vth) are essential parameters used for process
monitoring and for new semiconductor device evaluation.
These parameters can be derived from C-V measurements.
Benefits can include improved device quality and increased
production yield.

n

C-V Characteristics of MOS Structures

Total capacitance of the MOS structure shown in Figure

l-l consists of oxide-layer capacitance (Cox) and deple­tion-layer capacitance (Cd). Total capacitance is obtained
from the equation below:

c = Cox * Cd

Cox + Cd

Figure 1-2 shows swept bias C-V characteristics of an n­type MOS structure. Curves (a), (b), and (c) show the
characteristics of the structure at low frequency, high
frequency, and high frequency with pulsed bias.

The carrier distribution in the MOS structure during ac­cumulation, depletion, and inversion is shown in Figure

1-3.

(1) Accumulation

When positive voltage is applied to the gate, majority

carriers (electrons) accumulate on the Si-SiOz surface.
In this state, Cd is negligible and MOS capacitance is equal
to Cox, as shown in Figures l-2 and l-3.

(2) Depletion

When the applied voltage goes negative, the majority

carriers are repelled from the SiOz surface. Donor ions
remain as fixed charges, forming the depletion layer. In
this state, MOS capacitance consists of Cox and Cd, which
varies with the applied gate voltage. The MOS capacitance
is calculated from this equation:

c = Cox - Cd

Cox + Cd

(3) Inversion

As the applied gate voltage becomes more negative, the
density of the minority carriers (holes) becomes greater
than the density of electrons at the surface of the deple­tion layer, forming the inversion layer.

When a state of deep inversion is reached, the width of the

depletion layer becomes constant. Holes in the inversion

layer are supplied by the generation of electron-hole pairs

caused by normal thermal agitation. This electron-hole
generation is relatively slow. At high frequencies, how­ever, holes cannot be generated fast enough, so MOS
capacitance decreases and becomes constant as shown in
Figure 1-2 (b). But at lower frequencies, holes can be
generated fast enough to replenish the inversion layer.
Thus MOS capacitance becomes equal to Cox, as shown
in Figure l-2 for curve (a).

When high-frequency pulsed bias is applied, minority
carriers are generated even more slowly than when high

frequency is applied. This causes MOS capacitance to
decrease even further, as shown in Figure l-2 (c).

Semiconductor

Figure l-l

Inversion 1

-.vG

Figure l-2 C-V Characteristics of a MOS Structure

,,,p +2gizg:,”

T

d

I,

(1) Accumulation

,,,P K”

(3 __-------

‘, ..:.,:...:. _.,,

: ‘_ ‘.

MOS Structure

Accumulation

U

Bias

:,:,..'.'.'..,,

. . . . . . . . .

. . . . . . . . .

“G

Elec*trons

n-type material

7

b

-L

(2) Depletion

CdL

Figure 1-3 Carrier Distribution of a MOS Structure

_--_-_---

. . . . . . . . 1

T

1

(3) InZsion

-2

n C-V Characteristics of pn Junctions

Figure l-4 shows how the depletion layer of a pn junction
is formed by fixed charges (donor and acceptor ions)
which concentrate at the junction of the p and n mate-

k rials. The depletion layer capacitance, Cd, depends on the

applied bias voltage. Because Cd depends largely on the
impurity concentration of the substrate, the impurity
concentration and the built-in potential can be calculated
by measuring the pn structure’s C-V characteristics. Figure

1-5 shows an example of the C-V characteristics of a pn

junction.

Depiction

Figure 1-4 pn Junction

layer

When calculating such parameters as the impurity concen­tration or oxide layer thickness, precise capacitance meas-

urement results are necessary. These results can be fed
back to control the wafer production process, thereby
increasing production yields, improving device quality,
and reducing test cost.

(I) Error Correction

The 4280A has a CABLE LENGTH CALIBRATION
function that corrects errors occurring in cables up to five

meters long. With the test cable connected to the HIGH
terminal (open termination) the 4280A measures the open

admittance of the test cable and stores the measured value
in internal ROM. The stored value is then used to correct
the measured value of the device under test. The cor­rected value is displayed. CABLE LENGTH CAL doesn’t
need to be performed when the test cable is zero or one
meter.

Next, perform the ZERO OPEN measurement with the

test future and cables open (see Figure l-6). In this case

the 4280A measures stray capacitance/conductance of the

test fixture and stores the measurement in memory.

Last, press the CORRECTION ENABLE key. This causes

the 4280A to calculate error corrections, such as the one

shown below, then display the true value for the DUT.

Figure 1-5

1.4 Wafer Capacitance Measurements It has always been difficult to measure wafer capacitance

accurately when using a wafer prober, because of such in­herent measurement errors as these:

l

Stray capacitance and conductance of test furture and
probes

l

Mutual inductance and admittance of test cables

l

Effects of environmental noise

l

Transient line noise when performing grounded device
measurements

C-V Characteristics of a pn Junction

YT =

Where

YM is the measured value (admittance);
Yr is the true value of the DUT (admittance);
YA is the open admittance of the test cable;
Yz is the stray admittance of the test fixture;
Zo is the characteristic impedance of the test cable,

a constant (be sure to use the specified cable
(HP No. 8120-4195) otherwise accurate error

correction will be impossible because of incor-

rect Z,); and

Rs and RD are the residual resistances of the test

signal source (Rs) and the measurement circuit
or I-V convertor (Ro) (also constants).

YM{~ + (RD + MYA)

1 -ZhYi

-YM(2Z&YA+R,,+RS) ’
(For floating DUT measurements)

Stray admittance

\

-y

‘““w Low

The HP 4280A, however, virtually eliminates these errors.
The 4280A’s error correction function, two-terminal pair

k measurement method, and grounded device measurement

capability enable the user to make accurate measurements

when using a wafer prober.

-3

I Wafer

Chuck

Figure 1-6 Open Condition

C-V CHARRCTERISTICS

Sample= ME DIODE

Ccr= 43.351pFl

428OP

I .a

I ,r----- I

i
i

:

‘3 8.5

\

CJ

t

Figure 1-7 Difference in Measurement Results with and

without Error Correction

Figure l-7 shows the difference in the results obtained

with and without error correction. It can be seen that the
effect of error correction is substantial.

(2) Two-Terminal Pair Measurement Method

Figure l-8 illustrates the two-terminal pair measurement
method. When using a coaxial cable in this method,
currents of equal and opposite direction flow down the

/! .-.-. -... Without correction 1

With correction

center conductor and outer conductor. Consequently the

effects of mutual interference between High and Low con­ductors cancel. And the outer conductor acts as a shield
to eliminate external noise.

I

(3) Grounded DUT Measurement

When the device under test is grounded (for example,

the chuck of a wafer prober), select the “GROUNDED”
CONNECTION MODE. In the grounded mode, the cur­rent flowing in the DUT is measured correctly and noise
from ground is eliminated. This improves measurement

accuracy. The grounded measurement is performed as
shown in Figure 1-8 (b).

When testing wafers, connect the 4280A to the prober as

1

shown in Figure 1-9 (a). First cover the prober with a
shield box with dark interior to reduce the effects of
external noise and light. Next, as shown in Figure l-9 (b),

insulate the test cable from the shield box at the con­nector to avoid mixing noise from the shield box and the
outer conductor of the text cables. Further, as shown in

Figure 1-9 (c), use coaxial lead as close to the probe tip as
possible to decrease stray admittance; and short the outer
conductors of the High and Low cables to prevent errors
that could occur if the two-terminal pair were not formed.
Use of this technique will help insure stable, accurate
measurements.

r----­I ,

r-----

I-

L---------J

4280A

----

4280A

-

-

duter conductor

(a) FLOATING MODE

1

1 HIGH (Test cable)

+

---------

-

(b) GROUNDED MODE

t

DUT*

*DUT: Device Under Test

Figure 1-8 Two-Terminal Pair Measurement Method

-4-

1

I

Shield box

J

Probe

I

\

(b)

\

I

Prober

(a)

‘---/-Test cable (coaxial type)

Insulator (rubber, teflon, etc.)

( HP NO. 8120-4195 )

(b) Enlargement of the connector

HIGH

LOW

l:vy Coaxial-we probe

Chuck -//7//71/1/

(c) Enlargement of the probe end

Figure 1-9 How to Connect with the Prober

-5-

2. EVALUATION OF C-V/G-V CHARACTERISTICS

This chapter explains how to use the C-V characteristics
to calculate other parameters. This analysis is performed
when evaluating the quality of semiconductor processes.

2. 1 C-V Measurement
Figure 2-1 shows two examples of C-V/G-V measurement

using the HP 4280A.
In Figure 2-1 (a), the 4280A is shown controlled by an

HP 9826A Desktop Computer. Using an HP-IB control­led prober, many DUTs on a wafer can be tested auto­matically.

Figure 2-1 (b) shows a system that enables C-V/G-V
characteristics to be plotted on an X-Y recorder using
RECORDER OUTPUT of the 4280A. Normalized data
can be plotted by measuring the capacitance of the oxide
layer (Cox) before the sweep. Cox is then used as the
normalization constant and the 4280A’s math function
is used to plot C/Cox.

The next example shows how to make a C-V measurement

using the HP-IB system shown in Figure 2-l (a). (Refer

to page 17 for a sample program.)

( Example of Measurment >

Figure 2-2 (a) shows n-type MOS diode C-V characteristics
measured under the following conditions:

START V =

-5v
STOP V = 5V
STEP V = 0.05v
HOLD TIME = 10s
STEP DELAY TIME = 1Oms

The C-V characteristics are not accurate for bias from -5
to -2.5V. This is because the measurement was not per-

formed under equilibrium conditions (i.e. the HOLD TIME
of 10s was not long enough). Figure 2-2 (b) shows the
result of a 40s HOLD TIME, performed at equilibrium.
This example shows how the HOLD TIME and STEP DE-

LAY TIME can be chosen to obtain stable measurements.
This test was performed using the connection shown in

Figure 2-3. (Please see page 15 for details.)

(a) Using HP-IB

Recorder output

I

--

I

-__

i! !i\li\

98611A + opt 655
98256A

7470A Plotter

1

7035B X-Y Recorder

Figure 2-1

(b) Using X-Y Recorder

The System for C-V Measurement

-6-

C-V CHARRCTERISTICS

Sample= MO5 DIODE

C&x= 43.551pFl

42EIOR

r-

--------

(a) HOLD TIME = 10 s

C-V CHARRCTERISTICS

Sample= MOS DIODE

Cox= 43.55CpFl

L

(b) HOLD TIME = 40 s

Figure 2-2 C-V Characteristics of MOS Diode

4280R

2. 2 How to Calculate Semiconductor Parameters
To calculate semiconductor parameters from C-V charac-

teristics, the Cox (oxide layer capacitance) must be meas­ured and the Nsub (impurity concentration of substrate)

obtained from the depletion layer capacitance must be

computed. The reliability of parameters largely depends

on the accuracy and resolution of measured Cox and

depletion layer capacitance. The 4280A can be used to

J

obtain sufficiently ac,curate parameters for this purpose.

Internal Bias Source Features

I
L ______ --- ---- A

Figure 2-3 Connection (CNIO)

4280A

I

The 4280A can provide a step-function ( / ) bias
sweep internally. The range of the bias sweep and the bias
step can be set using START V, STOP V, and STEP V.
Also, the HOLD TIME and STEP DELAY TIME are used

to insure that the DUT is tested under equiribrium condi­tions.

Therefore the most suitable measurement conditions

for the DUT are obtained.
Four bias sweep modes are available- ,’ , \ ,

3%) and v, using these modes, the hysteresis of

C-V characteristics can be obtained.

-7-

SWEEP START

OV--7 STEP

/ ’ L M,easurement

HOLD’-

TIME

Time