Keysight M320xA, M330xA User Manual

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators

User’s Guide

Notices

CAUTION

WARNING

Copyright Notice

© Keysight Technologies 2020-2021

No part of this manual may be reproduced in
any form or by any means (including elec­tronic storage and retrieval or translation
into a foreign language) without prior agree­ment and written consent from Keysight
Technologies as governed by United States
and international copyright laws.

Trademarks

UNIX is a registered trademark of UNIX Sys­tem Laboratories in the U.S.A. and other
countries. Target is copyrighted by Thru-Put
Systems, Inc.

Manual Part Number

M3xxx-90003

Edition

1.2, February 2021

Available in electronic format only

Published by

Keysight Technologies, Inc.
1900 Garden of the Gods Road
Colorado Springs, CO 80907 USA

Technology Licenses

The hardware and/or software described in
this document are furnished under a license
and may be used or copied only in accor­dance with the terms of such license.

Declaration of Conformity

Declarations of Conformity for this product
and for other Keysight products may be
downloaded from the Web. Go to

http://www.keysight.com/go/conformity

and click on “Declarations of Conformity.”
You can then search by product number to
find the latest Declaration of Conformity.

U.S. Government Rights

The Software is "commercial computer soft­ware," as defined by Federal Acquisition
Regulation ("FAR") 2.101. Pursuant to FAR

12.212 and 27.405-3 and Department of
Defense FAR Supplement ("DFARS")

227.7202, the U.S. government acquires
commercial computer software under the
same terms by which the software is cus­tomarily provided to the public. Accordingly,
Keysight provides the Software to U.S. gov­ernment customers under its standard com­mercial license, which is embodied in its
End User License Agreement (EULA), a copy
of which can be found at http://www.key-

sight.com/find/sweula. The license set forth

in the EULA represents the exclusive author­ity by which the U.S. government may use,
modify, distribute, or disclose the Software.
The EULA and the license set forth therein,
does not require or permit, among other
things, that Keysight: (1) Furnish technical
information related to commercial computer
software or commercial computer software
documentation that is not customarily pro­vided to the public; or (2) Relinquish to, or
otherwise provide, the government rights in
excess of these rights customarily provided
to the public to use, modify, reproduce,
release, perform, display, or disclose com­mercial computer software or commercial
computer software documentation. No addi­tional government requirements beyond
those set forth in the EULA shall apply,
except to the extent that those terms, rights,
or licenses are explicitly required from all
providers of commercial computer software
pursuant to the FAR and the DFARS and are
set forth specifically in writing elsewhere in
the EULA. Keysight shall be under no obliga­tion to update, revise or otherwise modify
the Software. With respect to any technical
data as defined by FAR 2.101, pursuant to
FAR 12.211 and 27.404.2 and DFARS

227.7102, the U.S. government acquires no
greater than Limited Rights as defined in
FAR 27.401 or DFAR 227.7103-5 (c), as
applicable in any technical data.

Warranty

THE MATERIAL CONTAINED IN THIS DOCU­MENT IS PROVIDED "AS IS," AND IS SUB­JECT TO BEING CHANGED, WITHOUT
NOTICE, IN FUTURE EDITIONS. FURTHER,
TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, KEYSIGHT DISCLAIMS
ALL WARRANTIES, EITHER EXPRESS OR
IMPLIED WITH REGARD TO THIS MANUAL
AND ANY INFORMATION CONTAINED
HEREIN, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANT-

ABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. KEYSIGHT SHALL NOT BE LIABLE
FOR ERRORS OR FOR INCIDENTAL OR CON­SEQUENTIAL DAMAGES IN CONNECTION
WITH THE FURNISHING, USE, OR PERFOR­MANCE OF THIS DOCUMENT OR ANY
INFORMATION CONTAINED HEREIN.
SHOULD KEYSIGHT AND THE USER HAVE A
SEPARATE WRITTEN AGREEMENT WITH
WARRANTY TERMS COVERING THE MATE­RIAL IN THIS DOCUMENT THAT CONFLICT
WITH THESE TERMS, THE WARRANTY
TERMS IN THE SEPARATE AGREEMENT WILL
CONTROL.

Safety Information

A CAUTION notice denotes a hazard. It
calls attention to an operating proce­dure, practice, or the like that, if not
correctly performed or adhered to,
could result in damage to the product
or loss of important data. Do not pro­ceed beyond a CAUTION notice until
the indicated conditions are fully
understood and met.

A WARNING notice denotes a hazard.
It calls attention to an operating pro­cedure, practice, or the like that, if not
correctly performed or adhered to,
could result in personal injury or
death. Do not proceed beyond a
WARNING notice until the indicated
conditions are fully understood and
met.

Contents

1 Understanding PXIe AWGs Theory of Operation

Working with Signal Generation/Channel Structure / 13

Channel Numbering and Compatibility Mode / 13
Channel Waveshape Types / 14

FG vs AWG 14
Using Partner Channel 14

Signal Generation with the Function Generator / 15

Waveform harmonics 16

Signal Generation with the Arbitrary Waveform Generator / 16
Channel Frequency and Phase / 17

Phase coherent vs. phase continuous 17

Channel Amplitude and DC Offset / 18

Working with AWG Waveforms / 19

AWG Programming Process / 19

One-Step AWG programming process 19
Step-by-Step AWG programming process 20

AWG Waveform Queue System / 20

AWG Waveform Queue System Examples 21
Inter-waveform/inter-cycles discontinuities 21
HVI Generation Sequences 21

AWG Prescaler and Sampling Rate / 22

M3201A 22
M3202A 22
Prescaler vs. Upsampling 22

AWG Trigger Mode / 23

External Trigger Connector/Line Usage 23

AWG External Trigger Source / 23
AWG External Trigger Behavior / 24
AWG Markers / 24
AWG FlexCLK Synchronization (models with variable sampling rate) / 24
AWG Waveform Array and *.csv file structure / 27
AWG Waveform Types / 28

Working with Signal Modulation / 29

Frequency and Phase Modulation (Angle Modulator Block) / 29

Programming Information 30

AM and DC Offset (Amplitude Modulator Block) / 31

Mutual Exclusions for Modulations 31
Options (Mutual Exclusions for Modulations) 32
Programming Information 32

IQ Modulation (Quadrature Modulator Block) / 33

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 3

Mathematical Background of IQ Modulation 34
Mutual Exclusions for Modulations 34
Programming Information 34

Working with I/O Triggers / 35

Working with Clock System / 36

Chassis Clock Replacement for High-Precision Applications 36

CLK Output Options / 36
FlexCLK Technology (models w/ variable sampling rate) / 36
CLKref Frequency in AWG Modules with Option CLV / 37

2 Using the KS2201A PathWave Test Sync Executive software

Licensing for KS2201A PathWave Test Sync Executive software / 40

Comparing ProcessFlow GUI with KS2201A HVI API / 41

Working with KS2201A PathWave Test Sync Executive software / 42

Overview on HVI technology / 42

Understanding the HVI elements used in SD1 API / 43

Description of various HVI elements / 44

HVI Engine 44
HVI Actions 44
HVI Events 44
HVI Trigger 44
HVI Instructions 44
FPGA sandbox registers 44

Implementing HVI in SD1 API - Sample Programs / 45

Sample program using Python for HVI instructions / 45

3 Using the PathWave FPGA Board Support Package (BSP)

Licensing for PathWave FPGA BSP support / 48

Comparing FPGAFlow with PathWave FPGA / 49

Differences between FPGAFlow and PathWave FPGA / 49
New features in PathWave FPGA / 49

Working with PathWave FPGA software / 50

Understanding Partial Configuration (PR) / 51

Using BSP with PathWave FPGA software / 53

Understanding BSP composition / 53

Generating a k7z file using PathWave FPGA BSP / 55

4 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Loading k7z file into modules / 64

Using SD1 SFP user interface to load FPGA / 64
Using SD1 API to load FPGA - Basic workflow / 65

Implementing BSP using SD1 API - Sample Programs / 66

Sample program using Python for read write on sandbox region / 66
Sample program using .NET for read write on sandbox region / 68

4 Using Keysight SD1 3.x SFP Software

Installing the Keysight SD1 3.x Software Package / 73

Launching the Keysight SD1 SFP software / 74

Understanding the SD1 SFP features & controls / 76

Understanding main window features and controls / 76

File 77
Window 77
Help 77

Understanding features in Hardware Manager / 78

Understanding AWG SFP features & controls / 82

Understanding AWG SFP main menu features & controls / 83

File 83
Settings 83
View 85
FPGA 86
Help 86

Configuring AWG and Channel Setting dialogs / 87

Setting the Configure AWG Triggers dialog 87
Setting the Onboard Waveform memory dialog 87
Setting the AWG Configuration dialog 89
Setting the AWG Waveform Queue dialog 90
Setting the Trigger / Clock Settings dialog 91

Setting up the Channel configuration panel / 93

Channel n 94
Main 94
Waveform shape 94
Controls for Amplitude, Frequency, Phase & DC offset 95
Using the Channel Visualization Settings dialog 96
Modulation 97
AWG 98

5 Using Keysight SD1 API Command Reference

Keysight Supplied Native Programming Libraries / 100

Support for Other Programming Languages / 101

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 5

Functions in SD1 Programming Libraries / 102

Common References to parameter values / 105
Data transfer rates / 110
Latency in AWGs for various HVI Actions & Instructions / 111

HVI related latency in FPGA User Sandbox 112
TriggerIO and Action Groups 112

SD_Module functions / 115

open / 115
close / 117
moduleCount / 118
getProductName / 119
getSerialNumber / 120
getChassis / 121
getSlot / 122
PXItriggerWrite / 123
PXItriggerRead / 124
getFirmwareVersion / 125
getHardwareVersion / 126
getOptions / 127
getTemperature / 129
getType / 130
isOpen / 131
translateTriggerIOtoExternalTriggerLine / 132
translateTriggerPXItoExternalTriggerLine / 133
runSelfTest / 134

6 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

SD_AOU functions / 135

channelWaveShape / 135
channelFrequency / 137
channelPhase / 139
channelPhaseReset / 141
channelPhaseResetMultiple / 142
channelAmplitude / 143
channelOffset / 145
modulationAngleConfig / 147
modulationAmplitudeConfig / 149
modulationIQconfig / 151
clockIOconfig / 152
waveformLoad / 153
waveformReLoad / 155
waveformFlush / 157
AWG / 158
AWGqueueWaveform / 161
AWGflush / 164
AWGfreezeOnStopEnable / 166
AWGisFreezeOnStopEnabled / 167
AWGstart / 168
AWGstartMultiple / 170
AWGpause / 171
AWGpauseMultiple / 172
AWGresume / 173
AWGresumeMultiple / 174
AWGstop / 175
AWGstopMultiple / 176
AWGjumpNextWaveform / 177
AWGjumpNextWaveformMultiple / 178
AWGisRunning / 179
AWGnWFplaying / 180
AWGtriggerExternalConfig / 181
AWGtrigger / 182
AWGtriggerMultiple / 184
triggerIOconfig / 185
triggerIOwrite / 186
triggerIOread / 188
clockSetFrequency / 189
clockGetFrequency / 191
clockGetSyncFrequency / 193

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 7

clockResetPhase / 195
AWGqueueConfig / 197
AWGqueueConfigRead / 198
AWGqueueMarkerConfig / 199
AWGqueueSyncMode / 201
AWGqueueIsEmpty / 202
AWGqueueIsFull / 203
AWGqueueRemaining / 204
freqToInt / 205
freqGainToInt / 206
phaseToInt / 207
phaseGainToInt / 208
setDigitalFilterMode / 209
voltsToInt / 210
waveformAddToList / 211
waveformListLoad / 212

SD_Wave functions / 213

new / 213
delete / 215
getStatus / 216
getType / 217

SD_Module functions (specific to Pathwave FPGA) / 218

FPGAgetSandBoxRegister / 218
FPGAgetSandBoxRegisters / 219
FPGAload / 220
FPGAreset / 221
FPGATriggerConfig / 222
FPGAconfigureFromK7z / 223
FPGAGetKernelUUID / 224
User FPGA HVI Actions/Events / 225
Module HVI Engine / 226
Module HVI Triggers / 227

SD_SandboxRegister functions / 228

readRegisterBuffer / 228
readRegisterInt32 / 229
writeRegisterBuffer / 230
writeRegisterInt32 / 231
Properties / 232

8 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

6 Using SD1 API functions in sample programs

Basic Work Flow for the AWG / 234

Implementing SD1 API functions — Sample Programs / 235

Sample program for the overall AWG work flow using Python / 235
Sample program for Sine Wave generation using Python / 237
Sample Program for Sawtooth Wave generation from an Array / 239
Sample Program for using AWG Partner Channel as Differential / 241
Sample Program for using 48-bit HVI registers / 244

7 Understanding Error Codes in SD1 API

Description of SD1 Error IDs / 248

8 Documentation References

Accessing Online Help for SD1 3.x software / 252

Links to other documents / 253

Index

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 9

10 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators

User’s Guide

1. Understanding PXIe AWGs Theory of Operation

Working with Signal Generation/Channel Structure 13
Working with AWG Waveforms 19
Working with Signal Modulation 29
Working with I/O Triggers 35
Working with Clock System 36

1 Understanding PXIe AWGs Theory of Operation

Keysight M320xA PXIe Arbitrary Waveform Generators include an embedded Function Generator
(FG), Arbitrary Waveform Generator (AWG), and modulator blocks; together, they form a powerful
signal generator that is capable of generating standard waveforms (sinusoidal, triangular, square,
and DC voltages) or arbitrary waveforms defined by the user and stored on its onboard RAM. With
embedded modulator blocks, the output channels can be modulated in phase, frequency, amplitude,
or IQ to create analog or digital modulation.

12 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

Section 1.1: Working with Signal Generation/Channel Structure

Each channel (Channel 1 to Channel n) has an identical structure that contains a Function Generator
(FG), Arbitrary Waveform Generator (AWG), Frequency and Phase Angle Modulator, Amplitude and
DC Offset Amplitude Modulator, and an IQ Modulator.

Figure 1 Workflow during signal generation

1.1.1: Channel Numbering and Compatibility Mode

Compatibility mode, which can be changed by open(), is available to support legacy modules and
allows the channel numbering (channel enumeration) to start with either CH0 or CH1.

Table 1 API for Channels

Option Description Name Value

Legacy Channel enumeration starts with CH0 COMPATIBILITY_LEGACY 0

Keysight Channel enumeration starts with CH1 COMPATIBILITY_KEYSIGHT 1

Legacy modules refer to SD1 modules that were manufactured by Signadyne before they were
acquired by KeysightTechnologies. If the hardware equipment configuration being used only
contains modules from KeysightTechnologies, channel enumeration should start with CH1.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 13

1 Understanding PXIe AWGs Theory of Operation

1.1.2: Channel Waveshape Types

Each channel has a Function Generator (FG) block that generates basic periodic signals and an
Arbitrary Waveform Generator (AWG) block that generates arbitrary waveforms.

FG vs AWG

When the generation of periodic signals is needed, an FG has many advantages over a pure AWG
solution:

• The FG does not use onboard RAM.

•The “channelWaveShape()”, “channelFrequency()” and “channelPhase()” functions can be

changed in real time without having to modify a static waveform loaded in memory.

• Achieving the same precision in frequency and phase with a pure AWG solution requires a huge

amount of memory.

Table 2 Channel Waveshape Types

WaveShape Description Name Value

HiZ* The output signal is set to HIZ. No output signal is provided. AOU_HIZ -1

No Signal The output signal is set to 0. All other channel settings are maintained. AOU_OFF (default) 0

Sinusoidal Generated by the Function Generator. AOU_SINUSOIDAL 1

Triangular Generated by the Function Generator. AOU_TRIANGULAR 2

Square Generated by the Function Generator. AOU_SQUARE 4

DC Voltage Generated by the Amplitude Modulator. AOU_DC 5

Arbitrary Waveform Generated by the Arbitrary Waveform Generator (See AWG Waveform

Typ es).

Partner Channel Only an even numbered channel (according to Keysight Channel

numbering format) can be set as a partner to the previous odd numbered
channel (for example, CH2 is a partner to CH1). The waveform queue,
load and start functions defined for the odd numbered channel are
automatically called for the respective partner channel.

* Only available for Keysight M3202A PXIe AWG models

AOU_AWG 6

AOU_PARTNER 8

Using Partner Channel

AOU_PARTNER (8) generates signals on the even numbered channel (either 2 or 4), where the
channel partners with the previous odd numbered channel. All functions called for the latter are
automatically called for the respective partner channel. The signal comes from AWG mode and not
the Function Generator. The Partner Channel feature is hidden in the SD1 SFP user interface and can
be enabled using the SD1 API only.

To produce differential signals for channels 1 and 3:
1 (Optional) Create an AWG object with “SD_AOU functions()”.
2 Open an AWG with “open()”.
3 Flush waveforms with “waveformFlush()”.
4Set “channelWaveShape()” to AOU_AWG and AOU_PARTNER on alternate Channels.

For example, set Channels 1 & 3 to AOU_AWG and Channels 2 & 4 to AOU_PARTNER.

5 On each AWG Channel, set the amplitude using “channelAmplitude()”.

14 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

6 On the alternate Partner Channels, set equal and opposite amplitude values using

“channelAmplitude()”.
For example, if you set an amplitude of 1V on Channels 1 & 3, the amplitude on Channels 2 & 4

must be -1V.
7 Load an AWG waveform using “waveformLoad()”.
8 Queue the waveform on the AWG Channels only using “AWGqueueWaveform()”.

The waveform on the Partner Channels are queued automatically.
9 Start the waveform on each Channel simultaneously using “AWGstartMultiple()”.
10 Trigger the waveform on each Channel simultaneously to play the waveforms using

“AWGtriggerMultiple()”.
11 Stop the waveform on each Channel simultaneously using “AWGstopMultiple()”.

To view the corresponding programming steps, see “Sample Program for using AWG Partner

Channel as Differential” on page 241.

Table 3 API function for Channel Waveshapes

Function Name Comments Reference

channelWaveShape Sets the channel waveshape type. channelWaveShape()

1.1.3: Signal Generation with the Function Generator

Each channel has a Function Generator (FG) that generates basic periodic signals (sinusoidal,
triangular, square) and is commonly used to generate the RF carrier in modulation schemes. These
periodic signals can be modulated in frequency, phase, amplitude, or IQ.

Figure 2 Workflow for Function Generator

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 15

1 Understanding PXIe AWGs Theory of Operation

Waveform harmonics

Non-sinusoidal wave shapes (triangular, square, and so on) have high frequency components that
may fall outside the bandwidth of the reconstruction filter if the fundamental frequency is too high. In
this situation, the output analog signal may suffer some distortion due to the missing harmonics,
becoming a sinusoidal as the fundamental frequency approaches the cutoff frequency of the
reconstruction filter.

1.1.4: Signal Generation with the Arbitrary Waveform Generator

Each channel has an Arbitrary Waveform Generator (AWG) block that generates arbitrary waveforms
that can be sent directly to each output channel or they can be used as a modulating signal for the
frequency, phase, amplitude, or IQ modulators.

See “Working with AWG Waveforms” on page 19.

Figure 3 Workflow for Arbitrary Waveform Generator

16 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

1.1.5: Channel Frequency and Phase

Each channel has an Angle Modulator block that has a frequency and phase control. In angle
modulation schemes, these controls set the frequency and phase of the carrier.

See “Frequency and Phase Modulation (Angle Modulator Block)” on page 29.

Understanding PXIe AWGs Theory of Operation 1

Figure 4 Workflow for Channel Frequency and Phase

Phase coherent vs. phase continuous

Changes in the output signal are always phase continuous, not phase coherent. For example, the
frequency is changed from freq1 to freq2 and changed back to freq1, the phase will not be the initial
one. To achieve phase coherent behavior, the channel accumulated phase can be reset using

channelPhaseReset().

Additionally, in HVI operations, the execution time is deterministic, which allows you to calculate the
new phase and adjust it after any frequency change.

Table 4 Programming Function for channel frequency and phase

Function Name Comments Reference

channelFrequency Sets the frequency of the FG channelFrequency()

channelPhase Sets the phase of the FG channelPhase()

channelPhaseReset Resets the accumulated phase channelPhaseReset()

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 17

1 Understanding PXIe AWGs Theory of Operation

1.1.6: Channel Amplitude and DC Offset

Each channel has an Amplitude Modulator block that has an amplitude and DC offset control. These
controls have a combined range from 1.5V to –1.5 V.

See “AM and DC Offset (Amplitude Modulator Block)” on page 31.

Figure 5 Workflow for Channel Amplitude and DC Offset

Table 5 Programming Function for channel amplitude and DC offset

Function Name Comments Reference

channelAmplitude Sets the output amplitude channelAmplitude()

channelOffset Sets the output DC offset channelOffset()

18 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Section 1.2: Working with AWG Waveforms

Each channel has an Arbitrary Waveform Generator (AWG) block that generates arbitrary waveforms.

Understanding PXIe AWGs Theory of Operation 1

Figure 6 Workflow during AWG waveforms

1.2.1: AWG Programming Process

AWG block operation can be configured with a one-step programming process or with a
step-by-step programming process.

One-Step AWG programming process

The “AWG()” function provides a one-step solution to load, queue, and run a single waveform directly
from a file or from an array in the PC. This function simplifies the generation of a single waveform, but
it does not allow control over the following aspects of waveform generation:

• The possibility to prepare the AWG queue with multiple waveforms in advance before starting the

generation; this may be important to create more complex generation sequences.

• The possibility to have a variety of waveforms in the onboard RAM in order to queue them

repeatedly in the AWGs in an efficient way.

• The precise moment when waveforms are transferred from a file to the PC RAM and to the

onboard RAM. This may be important for long waveforms and time-critical applications.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 19

1 Understanding PXIe AWGs Theory of Operation

Step-by-Step AWG programming process

Keysight SD1 Programming Libraries provide full control of all aspects of arbitrary waveform
generation:

1 Create waveforms in the PC RAM with “new()” function. Waveforms can be created from points in

an array or from points in a file stored on hard disk.
2 Transfer waveforms to a module’s onboard RAM with waveformLoad().
3 Queue waveforms in an AWG with AWGqueueWaveform() to create the desired generation

sequence.
4 Select the sync mode of the queue with AWGqueueSyncMode().
5 Start the generation with AWGstart() and provide triggers if required.

See “AWG Waveform Queue System” on page 20.

Figure 7 Waveform programming flow

1.2.2: AWG Waveform Queue System

Each AWG block has a flexible waveform queue system that can be used to configure complex
generation sequences. In order to generate waveforms, they must be loaded into the module
onboard RAM and queued in each corresponding AWG.

The AWG waveform queue system has the following advantages:

• Provides a way to generate a sequence of waveforms one after the other with no discontinuities.

• Allows selection of many parameters (trigger mode, start delay, cycles, prescaler, and so on)

individually per queued waveform.

• Waveforms can have many instances in many AWG queues, but only one copy is required in the

onboard RAM. This feature saves onboard RAM memory.

Each AWG queued waveform has the following parameters:

• Trigger Mode: selects the trigger for the waveform.

• Start Delay: adds an optional delay from the reception of the trigger to the beginning of the

waveform generation.

• Cycles: the number of times the waveform is repeated. Using the appropriate trigger mode, the

AWG can be set to require one trigger per cycle or just one trigger at the beginning of all cycles.

20 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

• Cyclic Mode: sets the repetition cycles for the complete queue. The default mode is “One Shot”

and the complete queue will be reproduced one time. Complete queues with a number of
waveforms with a limited number of cycles can be repeated with AWGqueueConfig().

• For Cyclic mode, the minimum play time per cycle should be 1µs for M3201A/M330xA and 2µs
for M3202A modules.

• For fast trigger rates, it is recommended to consolidate all waveforms into a single bigger
waveform.

• Prescaler: divides the effective waveform sampling rate.

See “AWG Prescaler and Sampling Rate” on page 22.

AWG Waveform Queue System Examples

Figure 8 Flow in an AWG Waveform Queue System

Inter-waveform/inter-cycles discontinuities

The AWG Queue System allows you to queue many waveforms one after the other. It also provides
the capability to set repetition cycles per waveform and repetition cycles for the complete queue. In
all these cases, there are absolutely no discontinuities between waveforms or cycles, providing a
continuous waveform generation from the last sample point of the finished waveform to the first
sample point of the starting waveform.

HVI Generation Sequences

The queue system of the AWGs provide a way to create generation sequences. For more complex
sequences, the best solution is to use Keysight’s PathWave Test Sync Executive software API. This
API is based upon the Hard Virtual Instruments (HVIs) technology, using which you may achieve time
deterministic sequences with nanosecond resolution, providing a hard real-time execution. For more
information about the HVI technology, see Chapter 2, “Using the KS2201A PathWave Test Sync
Executive software”.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 21

1 Understanding PXIe AWGs Theory of Operation

1.2.3: AWG Prescaler and Sampling Rate

You can set a different prescaler value for each of the waveforms queued in the AWG. This prescaler
reduces the effective sampling frequency of each individual waveform in the following manner:

M3201A

0=> fs = 500 MSa/s

>=1 => fs = 100/n MSa/s

M3202A

>=1 => fs = 200/n MSa/s

An important advantage of this method is the possibility to change the sampling frequency in real
time from one waveform to another, reducing waveform sizes and maximizing the flexibility of the
AWG.

Prescaler vs. Upsampling

Note that reducing the effective sampling rate of the waveform with the prescaler is not the same as
using a full Upsampler, as the prescaler does not contain any filter. Therefore, it generates aliasing
inside the reconstruction filter bandwidth. For applications where full Upsampling is required, you
must use an IF Generator or Transceiver with DUC (Digital Up Converter) capabilities.

22 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

1.2.4: AWG Trigger Mode

A different trigger mode can be configured in each queued waveform.

Table 6 AWG Trigger Mode options

Options Description Name Value

Auto (Immediate) The waveform is launched automatically after AWGstart, or when the previous waveform in the

Software / HVI* Software trigger. The AWG is triggered by the AWGtrigger, provided that the AWG is running.

Software / HVI (per
cycle)

External Trigger Hardware trigger. The AWG waits for an external trigger. EXTTRIG 2

External Trigger (per
cycle)

queue finishes

AWGtrigger can be executed from the user application (VI) or from an HVI.

Software trigger. Identical to the previous option, but the trigger is required per each waveform
cycle.

Hardware trigger. Identical to the previous option, but the trigger is required per each waveform
cycle.

* VIHVITRIG is equivalent, but is considered obsolete

Table 7 API functions for AWG Trigger Modes

Function Name Comments Reference

AWG Provides a one-step method to load, queue, and start a single waveform AWG()

AWGqueueWaveform Queues a waveform in the specified AWG AWGqueueWaveform()

AUTOTRIG 0

SWHVITRIG 1

SWHVITRIG_CYCLE 5

EXTTRIG_CYCLE 6

If the queued waveforms are going to use any of the External Trigger modes, the source of this
trigger must be configured using “AWGtriggerExternalConfig()”.

External Trigger Connector/Line Usage

Apart from the AWG trigger settings, an external trigger connector/line may have additional settings
(input/output direction, sampling/synchronization options, and so on) that must be configured for
proper operation.

1.2.5: AWG External Trigger Source

Table 8 AWG External Trigger Source options

Options Description Name Value

External I/O Trigger The AWG trigger is a TRG connector/line of the module. PXI form factor only: this

trigger can be synchronized to CLK10.

PXI Trigger [0 to n] PXI form factor only. The AWG external trigger is a PXI trigger line and it is

synchronized to CLK10.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 23

TRIG_EXTERNAL 0

TRIG_PXI + Trigger No. 4000 + Trigger No.

1 Understanding PXIe AWGs Theory of Operation

1.2.6: AWG External Trigger Behavior

Table 9 AWG External Trigger Behavior options

Options Description Name Value

Active High Trigger is active when it is at level high TRIG_HIGH 1

Active Low Trigger is active when it is at level Low TRIG_LOW 2

Rising Edge Trigger is active on the rising edge TRIG_RISE 3

Falling Edge Trigger is active on the falling edge TRIG_FALL 4

1.2.7: AWG Markers

A different marker can be configured for each AWG channel. All waveforms must already be queued
using “AWGqueueMarkerConfig()” in one of the module’s AWGs.

1.2.8: AWG FlexCLK Synchronization (models with variable sampling rate)

The internal diagram and the operation of the M3201A/M3202A PXIe AWGFlexCLK system is shown
in “FlexCLK Technology (models w/ variable sampling rate)” on page 36. This advanced technology
allows you to change the sampling frequency of the AWGs (CLKsys), while maintaining full
synchronization capabilities due to the internal CLKsync signal. CLKsync is an internal signal used to
start the AWGs and it is aligned with CLKsys and PXI CLK10. Its frequency depends on the FlexCLK,
resulting in the following scenarios:

= f

f

CLKsync

When both frequencies coincide, there is no phase uncertainty between both signals and a trigger
synchronized with PXI CLK10 will start the AWGs always with the same skew, independently of the
clock boot conditions. This ensures proper synchronization between different modules.

PXI_CLK10

24 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

Figure 9 Block diagram depicting proper synchronization between modules

f

CLKsync!

= f

PXI_CLK10

When both frequencies do not coincide, both signals are still aligned, but there is a phase
uncertainty due to their frequency difference. In this case, if a trigger synchronized with PXI CLK10 is
sent to the system, there might be a skew between the start of different AWGs.

Figure 10 Block diagram depicting skew between the start of different AWG modules

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 25

1 Understanding PXIe AWGs Theory of Operation

This phase uncertainty can be easily corrected using clockResetPhase(). This function sets the
modules in a sync mode and the next trigger is used to reset the phase of the CLKsync and CLKsys
signals, not to start the AWGs. In this way, the phase uncertainty between different modules or
between different boot conditions can be eliminated, resulting in a predictable and repeatable skew.

Figure 11 Block diagram depicting synchronization between modules using the clockResetPhase function

26 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

1.2.9: AWG Waveform Array and *.csv file structure

The two possible sources of waveforms are an array in the PC RAM and a file in the PC HDD. The
memory array is just an array of waveform points, without header and without any particular
structure. A waveform file is simply a text file with values separated by commas (*.csv).

Figure 12 Block diagram depicting waveform file structure

The “waveformType” is a parameter that tells the module which kind of waveform it used to configure
the AWG internally.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 27

1 Understanding PXIe AWGs Theory of Operation

NOTE

1.2.10: AWG Waveform Types

See “waveformType” in waveform file or in the description for the new() function.

Table 10 Waveform types and corresponding values

Waveform Type Description Name Value

Analog 16 Bits Analog normalized waveforms (-1 to 1) defined with doubles WAVE_ ANALOG_16 0

Analog 32 Bits Analog normalized waveforms (-1 to 1) defined with doubles WAVE_ANALOG_32 8

Analog 16 Bits Dual Analog normalized waveforms (-1 to 1) defined with doubles, with two components (A and B) WAVE_ANALOG_16_DUAL 7

Analog 32 Bits Dual Analog normalized waveforms (-1 to 1) defined with doubles, with two components (A and B) WAVE_ANALOG_32_DUAL 9

IQ* Analog normalized waveforms (-1 to 1) defined with doubles, with two components (I and Q) WAVE_IQ 2

IQ Polar* Analog waveforms (-1 to 1 module, -180 to +180 phase) defined with doubles, with two

components (Magnitude and Phase)

Digital Digital waveforms defined with integers WAVE_DIGITAL 5

*When using IQ or IQ Polar, each component will only play at a maximum rate of 500 MSa/s.

WAVE_IQPOLAR 3

The M3201A PXIe AWG and both the M3300A & M3302A PXIe Combos do
not support both Analog 32 Bits (Single) and Analog 32 Bits Dual
waveforms.

28 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Section 1.3: Working with Signal Modulation

Signals can be modulated in frequency, phase, amplitude, or IQ.

1.3.1: Frequency and Phase Modulation (Angle Modulator Block)

The output signal of the Function Generator (FG) block or the Arbitrary Waveform Generator (AWG)
block can be modulated.

Understanding PXIe AWGs Theory of Operation 1

Figure 13 Block diagram depicting functionality of Angle Modulator

Table 11 Angle Modulation options

Options Description Name Value

No Modulation Modulation is disabled. AOU_MOD_OFF (default) 0

Frequency Modulation AWG is used to modulate the Channel frequency. AOU_MOD_FM 1

Frequency Modulation (32 bits)* AWG is used to modulate the Channel frequency. AOU_MOD_FM_32b 1

Phase Modulation AWG is used to modulate the Channel phase. AOU_MOD_Phase 2

*Models with Option DM1 dual modulation capability (amplitude and angle modulation simultaneously)

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 29

1 Understanding PXIe AWGs Theory of Operation

The modulating signal is generated using the AWG associated to that particular channel, for
example, AWG1 for channel 1.

The angle modulator allows you to create any analog/digital frequency or phase modulation. For
example: FM, FSK, PM, PSK, DPSK, and so on.

The output signal of a Channel using the frequency modulation is described using the following
equation:

where,

• A is the channel amplitude (set by “channelAmplitude()”)

• G is the deviation gain or peak frequency deviation (set by “modulationAngleConfig()”). Note
that G is only used for 16-bit waveforms.

• AWG(t) is the normalized modulating signal generated by the AWGs.

•sin[2π(f

t) + Øc] is the carrier signal, generated with the Function Generators.

c

As an example, for the generation of an FM signal with an amplitude of 0.8 Vp, a modulation index (h)
equal to 0.5 and a maximum frequency of the modulating signal of 10 MHz, the settings must be
A=0.8 and G=5,000,000 (where, G = h*max.freq[AWG(t)]).

The output signal of a Channel using the phase modulation is described by the following equation:

where,

• A is the channel amplitude (set by “channelAmplitude()”)

• G is the deviation gain or peak phase deviation (set by “modulationAngleConfig()”). Note that
G is only used for 16-bit waveforms.

• AWG(t) is the normalized modulating signal generated by the AWGs.

•cos[2π(f

t) + Øc] is the carrier signal, generated with the Function Generators.

c

As an example, for the generation of a PM signal with an amplitude of 0.8 Vp and a modulation index
(h) equal to 180, the settings must be A=0.8 and G=180 (G=h).

Output(t) = A . sin[2π(f

Output(t) = A . cos[2πf

+ G . AWG(t)) . t + Øc]

c

t + Øc + G . AWG(t)]

c

Programming Information

Table 12 APIfor Angle Modulation functions

Function Comments Details

modulationAngleConfig Configures the angle modulator modulationAngleConfig()

AWG functions Control the modulating signal AWG functions under SD_AOU functions

FG functions Control the carrier signal Channel functions under SD_AOU functions

30 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

1.3.2: AM and DC Offset (Amplitude Modulator Block)

The amplitude modulator can be used to modulate the amplitude or change the DC offset of the
output signal.

Mutual Exclusions for Modulations

Internally, IQ modulation uses the amplitude and the angle modulators, so they cannot be used when
the module is working in IQ mode.

Figure 14 Block diagram depicting functionality of Amplitude Modulator

The modulating signal is generated using the AWG associated with a particular channel (for example,
AWG1 corresponds to Channel 1). The Amplitude Modulator can be used to create analog/digital
amplitude modulation (for example, AM, ASK, and so on).

The output signal of a channel using the Amplitude Modulator is described using the following
equation:

Output(t) = (A + G . AWG(t)) . cos(2πf

where,

• A is the channel amplitude (set by “channelAmplitude()”)

• G is the deviation gain (set by “modulationAmplitudeConfig()”). Note that G is only used for
16-bit waveforms.

• AWG(t) is the normalized modulating signal generated by the AWGs.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 31

t + Øc)

c

1 Understanding PXIe AWGs Theory of Operation

•cos[2π(fct) + Øc] is the carrier signal, generated with the Function Generators.

As an example, for generation of an AM signal with an amplitude of 0.8 Vp and a modulation index (h)
equal to 0.5, the settings must be A=0.8 and G=0.32 (G = h . A

The output signal of a channel using the amplitude modulator to modulate the offset is described
using the following equation:

where,

• A is the channel amplitude (set by “channelAmplitude()”)

• G is the deviation gain (set by “modulationAmplitudeConfig()”). Note that G is only used for
16-bit waveforms.

• AWG(t) is the normalized modulating signal generated by the AWGs.

•cos[2π(f

t) + Øc] is the carrier signal, generated with the Function Generators.

c

Options (Mutual Exclusions for Modulations)

The Amplitude Modulator can be used with signals coming from the Function Generator directly, the
AWG, or the frequency/phase modulators. Therefore, the latter can be combined with amplitude
modulation at will (although it only makes sense for frequency/amplitude modulations, because for
phase/amplitude modulations there is a dedicated IQ operation, “IQ Modulation (Quadrature

Modulator Block)” on page 33, which uses the internal amplitude and the angle modulators.

2

).

Output(t) = A . cos(2πfct + Øc) + G . AWG(t)

Table 13 Amplitude Modulation options

Functions Description Const. Value

No Modulation Modulation is disabled. The channel amplitude and offset are only set by

the main registers.

Amplitude Modulation The modulating signal is used to modulate the channel amplitude. AOU_MOD_AM 1

Offset Modulation The modulating signal is used to modulate the channel offset. AOU_MOD_OFFSET 2

AOU_MOD_OFF 0 (default)

Programming Information

Table 14 APIfor Amplitude Modulation functions

Function Comments Details

modulationAmplitudeConfig Configures the amplitude modulator modulationAmplitudeConfig()

AWG functions Control the modulating signal AWG functions under SD_AOU functions

FG functions Control the carrier signal Channel functions under SD_AOU functions

32 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

NOTE

1.3.3: IQ Modulation (Quadrature Modulator Block)

The output signal of the Function Generator can be modulated simultaneously in amplitude and
angle (frequency or phase). This allows the creation of an IF signal with amplitude modulation while
the frequency is scanned. However, the most common use of dual modulations is the amplitude and
angle modulation decomposed to in-phase (I) and quadrature (Q) components, commonly known as
IQ modulation. In order to make the creation of IQ modulations easier, there are dedicated
programming functions for that purpose.

Figure 15 Block diagram depicting functionality of Quadrature (IQ) Modulator

The modulating signals are generated using the IQ Modulation (Quadrature Modulator Block)
associated to that particular channel, for example, AWG1 for channel 1. In this case, the waveform
loaded into the AWG is composed by the two waveforms (for example, I and Q components, see
“AWG FlexCLK Synchronization (models with variable sampling rate)” on page 24).

IQ waveforms are sometimes called complex waveforms due to the
mathematical form I(t)+iQ(t).

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 33

1 Understanding PXIe AWGs Theory of Operation

The output signal of a channel using the IQ modulator is described using the following equation:

Output(t) = (A / √2) . [AWG

where,

• A is the channel amplitude (set by “channelAmplitude()”)

•AWG

•cos[2π(f

(t) and AWGQ(t) are the normalized modulating signals generated by the AWGs.

I

t) + Øc] and sin[2π(fct) + Øc] are the carrier signals, generated with the Function

c

Generators.

You may also use the IQ modulator with amplitude and phase components:

where,

• A is the channel amplitude (set by “channelAmplitude()”)

•AWG

•cos[2π(f

(t) and AWGØ(t) are the normalized modulating signals generated by the AWGs.

A

t) + Øc] is the carrier signal, generated with the Function Generators.

c

Mathematical Background of IQ Modulation

The IQ modulation is based on the decomposition of the output signal in sinus and cosinus:

A . cos(2πf

where,

• I = A . cos(Ø)

• Q = A . sin(Ø)

The IQ components become very useful to set the amplitude (A) and the phase (Ø) of the output
signal, resulting in IQ modulation (or QAM, Quadrature Amplitude Modulation).

where,

• I = A . cos(Ø)

• Q = A . sin(Ø)

(t) . cos(2πfct + Øc) — AWGQ(t) . sin(2πfct + Øc)]

I

Output(t) = A . AWGA(t) . cos(2πfct + Øc + π/2 . AWGØ(t))

t + Øc + Ø) = A . cos(2πfct + Øc)cos(Ø) — A . sin(2πfct + Øc)sin(Ø)

c

A . cos(2πf

t + Øc + Ø) = I . cos(2πfct + Øc) — Q . sin(2πfct + Øc)

c

Mutual Exclusions for Modulations

Internally, IQ modulation uses the amplitude and the angle modulators so they cannot be used when
the module is working in IQ mode.

Programming Information

Table 15 APIfor IQ Modulation functions

Function Comments Details

modulationIQConfig Configures the IQ modulator modulationIQconfig()

AWG functions Control the modulating signal AWG functions under SD_AOU functions

FG functions Control the carrier signal Channel functions under SD_AOU functions

34 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

Section 1.4: Working with I/O Triggers

The M3201A/M3202A PXIe AWG has general purpose input/output triggers (TRG connectors/lines).
A trigger can be used as a general purpose digital IO or as a trigger input, and can be sampled using
the options shown below in Trigger Synchronization/Sampling Options. Because the Keysight
M3201A and M3202A PXIe AWGs have different output latencies, triggering both at the same time
from HVI will always result in a 65 to 70 ns offset between their outputs.

Table 16 I/O Trigger types and corresponding values

Typ e Description Name Value

Trigger Output (readable) TRG operates as a general purpose digital output signal, that can be written

by the user software.

Trigger Input TRG operates as a trigger input, or as general purpose digital input signal,

that can be read by the user software.

Table 17 Trigger Synchronization types and corresponding values

Typ e Description Name Value

Non-synchronized mode The trigger is sampled with an internal 100 MHz clock. SYNC_NONE 0

Synchronized mode (PXI form factor only) The trigger is sampled using CLK10. SYNC_CLK10 1

AOU_TRG_OUT 0

AOU_TRG_IN 1

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 35

1 Understanding PXIe AWGs Theory of Operation

Section 1.5: Working with Clock System

The M3201A/M3202A PXIe AWG uses an internally generated high-quality clock (CLKref) which is
phase-locked to the chassis clock. Therefore, this clock is an extremely jitter-cleaned copy of the
chassis clock. This implementation achieves a jitter and phase noise above 100 Hz which is
independent of the chassis clock, depending on it only for the absolute frequency precision and long
term stability. A copy of CLKref is available at the CLK connector.

CLKref is used as a reference to generate CLKsys, the high-frequency clock used to sample data.

Chassis Clock Replacement for High-Precision Applications

For applications where clock stability and precision is crucial (for example: GPS, experimental
physics, etc.), you can replace the chassis clock with an external reference.

In the case of PXI/PXIe, this is possible via a chassis clock input connector or with a PXI/PXIe timing
module. These options are not available in all chassis; see the corresponding chassis specifications.

1.5.1: CLK Output Options

Table 18 Clock Output options

Options Description Name Value

Disable The CLK connector is disabled. N/A 0 (default)

CLKref Output A copy of the reference clock is available at the CLK connector. N/A 1

1.5.2: FlexCLK Technology (models w/ variable sampling rate)

The sampling frequency of the M3201A/M3202A PXIe AWG (CLKsys frequency) can be changed
using the advanced clocking system.

Figure 16 Block Diagram depicting the Advanced Flex Clock System in PXIe AWGs

FlexCLK System, where:

• CLKref is the internal reference clock, and is phase-locked to the chassis clock.

• CLKsys is the system clock used to sample data.

36 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Understanding PXIe AWGs Theory of Operation 1

NOTE

• CLKsync is an internal clock used for the synchronization features of the M3201A/M3202A PXIe
AWG.

• PXI CLK10 is the 10 MHz clock of the PXI/PXIe backplane.

The CLKsys frequency can be changed within the range indicated in the Data Sheet of the
corresponding product [clockSetFrequency()]. The CLKsync frequency changes with the CLKsys
frequency as per the following equation:

f

= GreatestCommonDivisor (f

CLKsync

PXI_CLK10

, f

CLKsys

/ 5)

The CLKsync frequency is returned by clockSetFrequency().

Table 19 CLKsync frequency mode options

Options Description Name Value

Low Jitter Mode The clock system is set to achieve the lowest jitter, sacrificing tuning speed. CLK_LOW_JITTER 0

Fast Tuning Mode The clock system is set to achieve the lowest tuning time, sacrificing jitter

performance.

1.5.3: CLKref Frequency in AWG Modules with Option CLV

In M3201A-CLV modules, CLKref frequency (freqCLKref) changes as follows, as a function of CLKsys
frequency (freqCLKsys):

• Between 400 MHz and 500 MHz => freqCLKref = freqCLKsys/40

• Between 300 MHz and 400 MHz => freqCLKref = freqCLKsys/30

• Between 200 MHz and 300 MHz => freqCLKref = freqCLKsys/20

• Between 150 MHz and 200 MHz => freqCLKref = freqCLKsys/15

• Between 100 MHz and 150 MHz => freqCLKref = freqCLKsys/10

• Below 100 MHz => error

In M3202A-CLV modules, CLKref frequecy (freqCLKref) changes as follows, as a function of CLKsys
frequency (freqCLKsys):

• Between 800 MHz and 1000 MHz => freqCLKref = freqCLKsys/80

• Between 600 MHz and 800 MHz => freqCLKref = freqCLKsys/60

• Between 400 MHz and 600 MHz => freqCLKref = freqCLKsys/40

• Below 400 MHz => error

The clockGetSyncFrequency() function returns a default value of 2.5 MHz
for AWG modules with option CLF. For AWG cards with the option CLV, it is
modified and set according to the sync frequency formula defined in the
Data sheet.

CLK_FAST_TUNE 1

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 37

1 Understanding PXIe AWGs Theory of Operation

38 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators

User’s Guide

2. Using the KS2201A PathWave Test Sync Executive software

Licensing for KS2201A PathWave Test Sync Executive software 40
Comparing ProcessFlow GUI with KS2201A HVI API 41
Working with KS2201A PathWave Test Sync Executive software 42
Understanding the HVI elements used in SD1 API 43
Implementing HVI in SD1 API - Sample Programs 45

This chapter provides an introduction to the KS2201A PathWave Test Sync Executive Software and
describes its implementation in the SD1 3.x API. For detailed information about the elements in
KS2201A PathWave Test Sync Executive Software and its API, refer to the KS2201A PathWave Test
Sync Executive User Guide.

2 Using the KS2201A PathWave Test Sync Executive Software

Section 2.1: Licensing for KS2201A PathWave Test Sync Executive software

Hardware license option (-HV1) on the M3xxxA modules

All M3xxxA modules support HVI technology. However, the hardware license option -HV1 must be
available on each module that is required to be programmed using the PathWave Test Sync
Executive software and for usability with SD1 3.x software. The newer M3xxxA cards are shipped with
the newest versions of firmware and SD1 software, which support the KS2201A PathWave Test Sync
Executive software. During procurement, you may choose to procure the -HV1 hardware option.

To use an older module with the KS2201A PathWave Test Sync Executive software, the firmware and
SD1 software must be upgraded. KS2201A PathWave Test Sync Executive software requires that
Keysight SD1 SFP software version 3.x be installed on the same machine. Also, the PXIe M3xxxA
modules products must have Firmware versions greater than or equal to 4.0 (for M320xA AWGs /
M330xA Combos) and greater than or equal to 2.0 (for M310xA Digitizers). For more information
regarding the supported firmware and software versions, refer to the SD1 3.x Software Startup
Guide.

Software license option for the KS2201A software

Refer to the KS2201A PathWave Test Sync Executive User Guide to know about the licenses that you
must procure for the KS2201A PathWave Test Sync Executive software.

40 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the KS2201A PathWave Test Sync Executive Software 2

NOTE

Section 2.2: Comparing ProcessFlow GUI with KS2201A HVI API

Beginning with SD1 3.x software release, the M3601A Hard Virtual
Instrument (HVI) Design Environment (ProcessFlow) is replaced by the
KS2201A PathWave Test Sync Executive Software for HVI integration. Both
the GUI elements and the API functions from the former HVI design
environment are not supported in the SD1 3.x software.

Tabl e 20 summarizes the main operations necessary in an HVI design as performed from the point of

view of the M3601A HVI GUI use model and the KS2201A HVI API use model. You may use this table
of equivalence to transition from ProcessFlow to the KS2201A PathWave Test Sync Executive
software.

Table 20 Differences in operations of ProcessFlow and KS2201A HVI API

Operations ProcessFlow Use Model KS2201A HVI API Use Model

HVI Design Flow First, a “.HVIprj” project file must be created using M3601A GUI

HVI Sequence It is implemented by means of a graphical flowchart. Each HVI

HVI SyncSequence The concept of HVI SyncSequences is not available in the

HVI Resources (Chassis,
Triggers, M9031A modules,
and so on)

Program HVI Sequences You may program HVI sequences by adding flowchart boxes

HVI Compile, Load, Run Once an “.HVI” file is open from a script, you can assign each

to design the required HVI sequences in form of flow-charts. A
binary “.HVI” file is generated from the “.HVIprj” file once the HVI
sequence design is final. The “.HVI” file must be open from code
to integrate the HVI solution into the application code.

Engine in each instrument has a single or main HVI Sequence
associated. All statements, both local and synchronized, are
added to it graphically.

M3601A flowcharts.

Connected chassis are automatically recognized. M9031A
boards are transparent to the M3601A software. PXI trigger
resources that can be allocated to the HVI solution are chosen
from the “Chassis settings” window.

using the M3601A GUI. Configure settings for statements in the
“Properties” window of each flowchart box.

sequence to an HW engine for it to be compiled, loaded to HW,
and executed. Project “.HVIprj” files can be also tested directly
from the M3601A GUI using the “Compile and Run” function.

Application code must import the “keysight_pathwave_hvi”
library to use the HVI API. HVI sequences can be created using
programs directly into the application code without importing
external files.

KtHviSequence class enables you to create a Local HVI
sequence using programs that run “locally” on a specific HVI
engine in a specific instrument. Local Sequences are accessed
using ‘SyncMultiSequenceBlock’ statement placed in a
SyncSequence (KtHviSyncSequence). The HVI top sequence is a
SyncSequence that contains SyncStatements.

KtHviSyncSequence class enables you to add synchronized
operations (Sync Statements) common to all HVI engines within
the HVI instance. The HVI top sequence is a SyncSequence that
contains SyncStatements. Local instructions are added and
executed within Local Sequences that can be accessed by
adding a ‘SyncMultiSequenceBlock’ in a SyncSequence.

HVI resources can be configured using “KtHviPlatform” class and
all the classes inside it.

You may program both HVI SyncSequences and HVI (Local)
Sequences with the API methods add_XXX(), where ‘XXX’ is the
statement name.

API SW methods can
compile the sequence using (hvi.compile()),
load it to hardware using (hvi.load_to_hw()),
run the sequence using (hvi.run()).

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 41

2 Using the KS2201A PathWave Test Sync Executive Software

Section 2.3: Working with KS2201A PathWave Test Sync Executive software

Beginning with Keysight SD1 3.x release, the KS2201A PathWave Test Sync Executive software has
been introduced to enhance the functionalities of one or more PXIe modules both individually and
interactively. This software has a new API based environment for developing and running programs
with a new generation of Keysight’s Hard Virtual Instrument (HVI) technology. The KS2201A software
enables programmatic development and execution of synchronous real-time operations across
multiple instruments. It enables you to program multiple instruments together so they can act
together with other instruments, like one instrument.

2.3.1: Overview on HVI technology

Keysight’s Hardware Virtual Instrumentation (HVI) technology provides the capability to create
time-deterministic execution sequences with precise synchronization by deploying FPGA hardware
simultaneously among the constituent instruments. This makes the technology a powerful tool in
MIMO systems, such as massive-scale quantum control networks.

A virtual instrument may be considered to function like any other instrument in the system; its main
objective being to digitally sequence events and instructions in the application while synchronizing
multiple modules. This instrument, (referred to in this document as the HVI instrument),
accomplishes this by running one or more “engines” synchronously by referencing a common digital
clock that all instruments (engines) operate on.

The KS2201A PathWave Test Sync Executive software provides you with the capability of designing
HVI sequences using an Application Programming Interface (API) available in both Python and C#
coding languages. The HVI Application Programming Interface (API) is the set of programming
classes and methods that allows the user to create and program an HVI instance. HVI API currently
supports Python v3.7. The HVI core functionality is extended by the PXIe M3xxxA modules using the
SD1 API. The core HVI features and the SD1 API extensions that are specific to M3xxxA, allow a
heterogeneous array of instruments and resources to coexist on a common framework.

All the PXIe M3xxxA modules support HVI technology. When Keysight SD1 is installed on a PXI
system, it installs the drivers required to interact with the M3xxxA series modules. The SD1 API
classes in the Keysight SD1 Library contain HVI add-on interfaces provided as an extension of the
instrument. These add-on interfaces provide access to instrument specific HVI features such as
triggering a digitizer acquisition, outputting a waveform, queuing a waveform, etc.

The primary HVI elements defined for the SD1 API and the corresponding API functions are described
in the following sections.

42 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the KS2201A PathWave Test Sync Executive Software 2

Section 2.4: Understanding the HVI elements used in SD1 API

The HVI Core API exposes all HVI functions and defines base interfaces and classes, which are used
to create an HVI, control the hardware execution flow, and operate with data, triggers, events and
actions, but it alone does not include the ability to control operations specific to the M3xxxA product
family. It is the HVI instrument extensions specific to M3xxxA modules that enable instrument
functionalities in an HVI. Such functions are exposed by the module specific add-on HVI definitions.
The SD1 API describes the instrument specific resources and operations that can be executed or
used within HVI sequences.

Figure 17 & Figure 18 display the AWG and Digitizer specific HVI definitions, which are added to the

SD1 library.

Figure 17 M310xA specific HVI definitions

Figure 18 M320xA specific HVI definitions

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 43

2 Using the KS2201A PathWave Test Sync Executive Software

2.4.1: Description of various HVI elements

HVI Engine

An HVI Engine block controls the functions of the instrument and the timing of operations. For HVI to
control an SD1 module, the latter requires an HVI Engine. The HVI Engine is included directly in the
instrument hardware or it can be programmed using the SD1 API into the Field programmable Gate
Array (FPGA) on each module. The HVI Engine executes sequences, which are made up of
Statements.

To define an HVI Engine in SD1 API, see the API syntax in Module HVI Engine.

HVI Actions

An HVI Action is defined for module-specific operations, such as playing waveform in an AWG or
starting an acquisition in Digitizers.

To define an HVI Action in SD1 API, see the API syntax for various HVI actions in SD_AOU functions
and SD_Module functions (specific to Pathwave FPGA).

HVI Events

An HVI Event is defined to occur when specific conditions are met during module-specific
operations, such as when an AWG queue is flushed or when a DAQ is empty.

To define an HVI Event in SD1 API, see the API syntax for various HVI events in SD_AOU functions
and SD_Module functions (specific to Pathwave FPGA).

HVI Trigger

An HVI Trigger is defined to activate the logic signal triggering source and perform various triggering
operations, which are shared between instruments to initiate module-related operations,
communicate states or other information.

To define an HVI Trigger in SD1 API, see the API syntax in Module HVI Triggers.

HVI Instructions

An HVI Instruction is defined to configure various settings related to the module. There are two types
of HVI instructions:

• Product specific (custom) HVI instructions—can change a module’s setting (such as amplitude,

frequency, etc.) or trigger a functionality in the module (such as output a waveform, trigger a data
acquisition, etc.).

• HVI core instructions (general purpose)—provide global, non-module specific or custom

functions, such as register arithmetic, read/write general purpose I/O triggers, execution actions,
etc.

To define an HVI Trigger in SD1 API, see the API syntax in SD_AOU functions.

FPGA sandbox registers

For the modules that contain an FPGA with a user-configurable sandbox, HVI can, potentially (if the
configuration of the module allows it), access (read/write) the registers that you define in that
sandbox. To accomplish this, you must obtain the “.k7z” file for the FPGA sandbox, generated by the
PathWave FPGA application. This file contains all the necessary information to access the registers
by name.

To define FPGA Action/Event in SD1 API, see the API syntax in User FPGA HVI Actions/Events.

44 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the KS2201A PathWave Test Sync Executive Software 2

Section 2.5: Implementing HVI in SD1 API - Sample Programs

The following section shows a sample program where HVI is implemented in SD1 API to create an
HVI sequence, add HVI main engine, define HVI trigger, assign ‘module hvi instruction set’ functions
followed by compiling the HVI sequence and loading it onto the hardware. Based on your
requirements, you may add ‘module hvi actions’ as well as ‘module hvi events’ functions to the HVI
sequence.

The SD1 API functions related to HVI are covered in Chapter 5, “Using Keysight SD1 API Command
Reference”.

Refer to the KS2201A PathWave Test Sync Executive User Guide to know more about the HVI Python
API.

2.5.1: Sample program using Python for HVI instructions

import sys

import keysight_hvi as kthvi

sys.path.append(r'C:\Program Files\Keysight\SD1\Libraries\Python')

import keysightSD1

awg = keysightSD1.SD_AOU()

awg.openWithSlot("M3201A", 1, 4)

sys_def = kthvi.SystemDefinition("mySystem")

sys_def.chassis.add_auto_detect()

sys_def.engines.add(awg.hvi.engines.main_engine, 'SdEngine0')

trigger_resources = [kthvi.TriggerResourceId.PXI_TRIGGER0,
kthvi.TriggerResourceId.PXI_TRIGGER1]

sys_def.sync_resources = trigger_resources

sys_def.non_hvi_core_clocks = [10e6]

sequencer = kthvi.Sequencer("mySequencer", sys_def)

sync_block = sequencer.sync_sequence.add_sync_multi_sequence_block("AWGsequence",10)

sequence = sync_block.sequences['SdEngine0']

test_channel = 1

instrLabel = "awgSetWaveshape"

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 45

2 Using the KS2201A PathWave Test Sync Executive Software

instruction0 = sequence.add_instruction(instrLabel, 20,
awg.hvi.instruction_set.set_waveshape.id)

instruction0.set_parameter(awg.hvi.instruction_set.set_waveshape.channel.id, test_channel)

instruction0.set_parameter(awg.hvi.instruction_set.set_waveshape.value.id,
awg.hvi.instruction_set.set_waveshape.value.AOU_SINUSOIDAL)

instrLabel = "awgSetFrequency"

instruction1 = sequence.add_instruction(instrLabel, 20,
awg.hvi.instruction_set.set_frequency.id)

instruction1.set_parameter(awg.hvi.instruction_set.set_frequency.channel.id, test_channel)

instruction1.set_parameter(awg.hvi.instruction_set.set_frequency.value.id, 1e7)

instrLabel = "awgSetAmplitude"

instruction1 = sequence.add_instruction(instrLabel, 20,
awg.hvi.instruction_set.set_amplitude.id)

instruction1.set_parameter(awg.hvi.instruction_set.set_amplitude.channel.id, test_channel)

instruction1.set_parameter(awg.hvi.instruction_set.set_amplitude.value.id, 1)

# Compile HVI sequences

try:

hvi = sequencer.compile()

except kthvi.CompilationFailed as ex:

compile_status = ex.compile_status

print(compile_status.to_string())

raise ex

print("HVI Compiled")

# Load HVI to HW: load sequences, configure actions/triggers/events, lock resources, etc.

hvi.load_to_hw()

print("HVI Loaded to HW")

# Execute HVI in non-blocking mode

# This mode allows SW execution to interact with HVI execution

hvi.run(hvi.no_wait)

print("HVI Running...")

46 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators

User’s Guide

3. Using the PathWave FPGA Board Support Package (BSP)

Licensing for PathWave FPGA BSP support 48
Comparing FPGAFlow with PathWave FPGA 49
Working with PathWave FPGA software 50
Using BSP with PathWave FPGA software 53
Generating a k7z file using PathWave FPGA BSP 55
Loading k7z file into modules 64
Implementing BSP using SD1 API - Sample Programs 66

This chapter provides an introduction to the PathWave FPGA Board Support Package (BSP) and
describes its implementation in the SD1 3.x API. For detailed information about using the PathWave

FPGA 2020 Update 1.0 software along with BSP for supported modules, refer to the PathWave FPGA
Customer Documentation and the BSP guides for the respective modules.

3 Using the PathWave FPGA Board Support Package (BSP)

Section 3.1: Licensing for PathWave FPGA BSP support

All instruments that can be programmed with PathWave FPGA BSP will enable programming using
the licensing option -FP1. You are required to procure an -FP1 license option for each instrument
that must be programmed. For example, if you are purchasing ten M3202A AWG cards, each
M3202A requires an individual -FP1 license option enabled.

New Hardware - Latest Software

The new modules for M3201A AWG 1G, M3202A AWG 500 and M3102A DIG500, M3102A DIG100,
M3302A Combo 500 500 and M3300A Combo 500 100, where you have the -FP1 license option
enabled are supported only with SD1 software version 3.x (or later) installed on your machine. If you
have SD1 version 2.x.x installed on your machine, you must upgrade the software for hardware
compatibility. For more information regarding the supported firmware and software versions, refer to
the SD1 3.x Software Startup Guide.

Latest Software - New Hardware

Keysight SD1 SFP software version 3.x or later recognize only those PXIe M3xxxA products that have
Firmware versions greater than or equal to 4.0 (for M320xA AWGs / M330xA Combos) and greater
than or equal to 2.0 (for M310xA Digitizers). You may either update the firmware on your modules or
contact Keysight Sales to upgrade your hardware. After upgrading your hardware, you must have the

-FP1 license option enabled to make it compatible with the latest version of SD1 software.

The M3201A / M3202A may be purchased as a 4 channel configuration, each of which may include
an option to specify either a fixed or a variable sampling clock.

The M3102A / M3100A may be purchased as a 4 channel configuration, which have fixed sampling
clock.

These modules may also be purchased to include one of two possible Xilinx FPGAs:
1 xc7k410tffg676-2
2 xc7k325tffg676-2

The xc7k410tffg676-2 part offers a substantial increase in the amount of FPGA resources available to
the user for custom logic. The following table outline the FPGA resources, which are available for
custom logic for each part.

Table 21 Available FPGA Resources for custom logic on each module

xc7k325tffg676-2 xc7k410tffg676-2

Resource Type 4 Channel 4 Channel

Slice LUTs 82800 102000

Slice Registers 165600 204000

DSP Blocks 360 660

Block RAM (RAMB18) 360 660

48 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

NOTE

Section 3.2: Comparing FPGAFlow with PathWave FPGA

Beginning with SD1 3.x software release, the M3602A Graphical FPGA
Development Environment (FPGAFlow) is replaced by the KF9000A
PathWave FPGA software for FPGA programming. The files generated by
FPGAFlow are not supported in the SD1 3.x software.

The following sections describe the differences between FPGAFlow and PathWave FPGA software
along with the new features introduced in the latter software.

3.2.1: Differences between FPGAFlow and PathWave FPGA

While most of the features are same, but there are subtle differences in the appearances and certain
aspects of both the FPGA programming environments. Tab le 2 2 highlights such differences.

Table 22 Differences between FPGAFlow and PathWave FPGA

l

FPGAFlow PathWave FPGA

Support limited to Legacy Signadyne boards Support for larger number of Keysight developed boards

Uses one or more BitGen servers to generate the output bitstream Uses Xilinx Vivado Design Suite locally on Host Machine to generate the output bitstream

Generates “sbp” file, which is loaded on the legacy module’s FPGA Generates “k7z” file, which is loaded on the FPGA of the new modules

3.2.2: New features in PathWave FPGA

Apart from the differences listed above, the PathWave FPGA software has certain new elements:

• IPs can be defined using IP-XACT file. This gives you information about the IP name, version,

interfaces, category, and so on.

• A repository of IPs that are using IP-XACT can be loaded concurrently.

• Block designs are now called sub-modules.

• Multiple boards are supported using the BSP technology.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 49

3 Using the PathWave FPGA Board Support Package (BSP)

NOTE

Section 3.3: Working with PathWave FPGA software

Beginning with Keysight SD1 3.x release, the KF9000A PathWave FPGA Programming Environment
(commonly known as PathWave FPGA), powered by Xilinx Vivado Design Suite, has been introduced
for FPGA designing on supported Keysight modules.

Some applications require the use of custom on-board real-time processing, which might not be
covered by the comprehensive off-the-shelf functionalities of standard hardware products. For these
applications, Keysight supplies Option -FP1 (Enabled FPGA Programming) that provide the capability
to program the on-board FPGA. With PathWave FPGA, development time is dramatically reduced
and you can focus exclusively on expanding the functionality of the standard instrument, instead of
developing a complete new one.

PathWave FPGA is a graphical environment that provides a complete FPGA design flow for rapid
FPGA development from design creation to simulation to Gateware deployment to
Hardware/Gateware verification on Keysight hardware with Open FPGA. This environment provides a
design flow from schematic to bitstream file generation with the click of a button.

The PathWave FPGA 2020 is a licensed software. Contact Keysight Support
for more information on procuring the respective licenses.

Once you have installed the PathWave FPGA 2020 software, you can launch its user interface from
the Start menu. Alternatively, you may use the corresponding command line or scripts to launch the
application.

Figure 19 Default window for PathWave FPGA 2020 Update 1.0 software

50 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

In Keysight PathWave, FPGA code is represented as boxes (called blocks) with IO ports. An empty
project contains the “Default Product Blocks”, and the “Design IO Blocks” that provide the outer
interface of the design. You can add/remove blocks from the Keysight Block Library, External Blocks,
or Xilinx IP cores.

To know about the required prerequisite software, system requirements and licensing information for
the PathWave FPGA 2020 Update 1.0 software, refer to the “Getting Started” section of the

PathWave FPGA Customer Documentation. To view the installation procedure, refer to the “Installing
PathWave FPGA 2020 Update 1.0 software” section and to view how to launch the software, refer to

the “Launching the PathWave FPGA BSP” section in the SD1 3.x Software Startup Guide.

3.3.1: Understanding Partial Configuration (PR)

The FPGA configurable region utilizes Xilinx FPGA partial reconfiguration technology to allow you to
design and configure a defined section of the supported M3xxxA FPGA without the need to power
down or reboot the M3xxxA module or host computer, respectively.

PathWave FPGA supports the design flow in the Partial Reconfiguration (PR) technology. In a PR
flow, a full FPGA reconfiguration is only necessary once for a given static region version. The
sandboxes can be reconfigured anytime, without a full reconfiguration, and without stopping the
current operation of the FPGA.

Partial Reconfiguration enables performing dynamic change of modules within an active design. By
implementing multiple configurations in this flow, you can achieve full bitstream for each
configuration and partial bitstream for each reconfigurable module.

While FPGA technology facilitates direct programming and re-programming of modules without
going through re-fabrication with a modified design; the partial reconfiguration technique allows the
modification of an operating FPGA design by loading a partial configuration file. The logic in the
FPGA design is divided into two different types, reconfigurable logic and static logic. The static logic
remains functional and is unaffected by the loading of a partial bitstream file, whereas the
reconfigurable logic is replaced by the contents of that bitstream file.

Figure 20 Block diagram depicting partial reconfiguration using bitstream files

Partial Reconfiguration (PR) is modifying a subset of logic in an operating FPGA design by
downloading a partial bitstream. In some cases, a complete FPGA reconfiguration might be
preferable (better routing, timing closure, and so on). This is also supported by PathWave FPGA, as
long as a reboot is not required after the reconfiguration process.

The PathWave FPGA software does not, by itself, provide access to the waveform and digitizer
controls for the supported Keysight M3xxxA PXIe modules. You must install the module-specific
Board Support Package (BSP) to leverage the features within the PathWave FPGA software for FPGA
designing and for loading your customized code onto the Keysight instrument.

The design part in Keysight FPGA consists of two regions: the static region and the sandbox region.
The static region for each supported module is defined within BSP and cannot be modified. This
region defines the implementation of the FPGA interfaces to external resources, and defines the

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 51

3 Using the PathWave FPGA Board Support Package (BSP)

interfaces to the sandbox. A static region implementation can define one or more sandbox regions in
an FPGA design. The sandbox region contains the user specific FPGA design. The interface of the
sandbox depends on the static region implementation.

Figure 21 Block diagram representing layout of Static and Sandbox regions

52 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

Section 3.4: Using BSP with PathWave FPGA software

3.4.1: Understanding BSP composition

In embedded systems, the board support package (BSP) is the layer of software containing
hardware-specific drivers and other routines that allow a particular operating system (traditionally a
real-time operating system, or RTOS) to function in a particular hardware environment (a computer
or CPU card), integrated with the RTOS itself. Third-party hardware developers, who wish to support
a particular RTOS must create a BSP that allows that RTOS to run on their platform. In most cases
the RTOS image and license, the BSP containing it, and the hardware are bundled together by the
hardware vendor. BSPs are typically customizable, allowing you to specify the drivers and routines,
which should be included in the software build based on their selection of hardware and software
options. (source: Wikipedia)

The Board Support Package (BSP), installed separately from PathWave FPGA, comprises of two
parts—an FPGA Support Package (FSP) and a Runtime Support Package (RSP). A BSP configuration
file contains all the necessary information to identify the configuration, which includes static region
implementation, an RSP implementation, build scripts, examples, project templates, and
documentation.

• The FSP is that portion of the BSP that allows you to build a bitstream file for the target FPGA. It is

consumed by PathWave FPGA to support design creation and sandbox compilation; everything
that is performed without the physical hardware. The FPGA Support Package allows you, as a
PathWave FPGA user, to create a design targeting your instrument. It includes descriptions of the
sandbox interfaces, template PathWave FPGA projects, and files required for compiling a sandbox
image from HDL sources. An FSP fulfills the ‘design-time requirements’ of PathWave FPGA, which
covers everything prior to loading a bit image onto the instrument.

• The RSP is that portion of the BSP that allows you to control your target FPGA. It provides a ‘C’

API that you can use to load design images onto hardware, verify your FPGA bitstream image and
perform simple register and streaming accesses to the sandbox. An RSP requires a hardware
driver with the following capabilities:

• Hardware discovery/enumeration

• Program the FPGA sandbox regions

• Read and write registers inside the sandbox

• Read and write to streaming interfaces inside the sandbox (if the sandbox has streaming
interfaces)

Both PathWave FPGA software and the BSP work together and cannot be used individually.

The block diagram shown in Figure 22 indicates how the bitstream file is generated using both the
PathWave FPGA software and BSP together for any specific supported PXIe module.

Figure 22 Bitstream file compilation flow using PathWave FPGA and BSP

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 53

3 Using the PathWave FPGA Board Support Package (BSP)

PathWave FPGA manages bitstream file generation using a scripted flow of the FPGA tools. The
scripts for building a specific design are provided by the FSP. The FSP build script can also add
metadata, which are delivered to the RSP. The bitstream file and metadata are packaged into a
Keysight PathWave FPGA program archive file with the filename extension *.k7z.

To load a bitstream image on the FPGA, PathWave FPGA supplies the program archive file to the
RSP. The RSP unpacks the contents of the program archive file and checks that the image is
compatible. The original bitstream file and the metadata are then passed to the instrument-specific
portion of the RSP, which eventually configures the FPGA with the bitstream file.

The output from a PathWave FPGA design compilation is saved in a Keysight PathWave FPGA
program archive file, with a k7z extension. To understand how to generate the k7z file onto a module,
see “Generating a k7z file using PathWave FPGA BSP” on page 55.

Hereafter, you may load the k7z file onto the required hardware using the Keysight SD1 3.x SFP
software’s user interface or the corresponding SD1 API functions. To understand how to load the k7z
file onto a module, see “Loading k7z file into modules” on page 64.

54 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

Section 3.5: Generating a k7z file using PathWave FPGA BSP

After you install BSP for one or more modules, you can proceed with creating a new project to design
the sandbox region for the corresponding modules.

Following steps give you a quick glance into creating a new sandbox project using PathWave FPGA
2020 software for FPGA designing followed by generating a bitstream file for one or more supported
PXIe modules. This example uses the BSP file for an M3102A module.

You can also perform most of the steps shown below using command line arguments. Refer to the
“Advanced Features” section of the PathWave FPGA Customer Documentation.

1 On the main window of the PathWave FPGA 2020 software, click the icon for new project.

A new sandbox project dialog appears.

Figure 23 Creating a new Sandbox project

2Click Next >.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 55

3 Using the PathWave FPGA Board Support Package (BSP)

3 For the Project Type, choose the BSP corresponding to one of the modules whose FPGA you wish

to update.

Figure 24 Selecting the module-specific BSP

4Click Next >.

56 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

5 For the Project Options, choose the BSP options and Board Configurations you wish to include in

your FPGA design logic for the selected module.

Figure 25 Selecting various options for FPGA design logic

6Click Next >.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 57

3 Using the PathWave FPGA Board Support Package (BSP)

7 For the Project Template, either choose the default template offered within the PathWave FPGA

design environment or choose blank to start a new custom design logic.

Figure 26 Selecting the PathWave FPGA project template

8Click Next >.

58 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

9 Verify all information displayed in the Project Summary. To make any amendments, click Back. If

the selected options for the corresponding BSP are satisfactory, click Finish.

Figure 27 Viewing the project summary information

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 59

3 Using the PathWave FPGA Board Support Package (BSP)

Various blocks are displayed, which are part of the default template in the PathWave FPGA
2020 software.

Figure 28 Viewing FPGA design blocks in the default template

10 Customize the configuration as per your requirements using one or more elements from the

Design Interfaces and IP Catalog panels.
For more information regarding the configurable region of the M3xxxA FPGA interfaces and BSP

IP Repository, refer to the BSP User Guide for the corresponding modules, which can be
accessed via Help > BSPs Help menu options in the PathWave FPGA 2020 software. The guides
for the supported modules are:

• M3102A PXIe Digitizers

• M3100A PXIe Digitizers

• M3201A PXIe Arbitrary Waveform Generators

• M3202A PXIe Arbitrary Waveform Generators

• M3302A PXIe AWG and Digitizer Combination

• M3300A PXIe AWG and Digitizer Combination

60 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

11 After you have finished designing your logic, you can proceed with the k7z file generation. Click

the Generate Bit File... icon as shown in Figure 29.

Figure 29 Initiating Bit File generation for the selected module

If you do not have the Xilinx Vivado Design Suite on the same machine where PathWave FPGA
2020 software and BSP are installed, the following error is prompted when you click the
Generate Bit File... icon.

Refer to PathWave FPGA Customer Documentation for more information on installing the
software and the licenses for the Xilinx Vivado Design Suite.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 61

3 Using the PathWave FPGA Board Support Package (BSP)

12 On the FPGA Hardware Build window that appears, click Run.

Figure 30 Generating FPGA Hardware Build

62 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

Depending on the configuration, the software takes some time before finishing the process of
k7z file generation.

Figure 31 Progress status for the k7z file generation

Once the Bitstream file (which is the k7z file) is generated, your custom FPGA logic is ready to be
loaded on the selected module using either the SD1 API or the Load Firmware feature (under FPGA
menu of the Module panel in the SFP software).

Other than configuring and designing your FPGA Logic using the PathWave FPGA 2020 Update 1.0
software, you can perform one or more of the following operations:

• Build your FPGA Logic

• Generate the Bit File (covered briefly in this section)

• Verify the Bit File

• Simulate your FPGA Logic

• Simulation Testbench Designing

• Test Bench Address Mapping

• Work with Advanced features

• Using Command Line Arguments

• Migrating a design to a new BSP

• Changing a Submodule Project Target Hardware

• Debugging in Hardware

For detailed instructions on performing these steps and to understand the features of the PathWave
FPGA 2020 software, refer to the PathWave FPGA Help file accessible via the Help menu of the
software. For information about the features and various elements along with understanding the
workflow associated with the PathWave FPGA 2020 Update 1.0 software, refer to the “User Guide”
section of the PathWave FPGA Customer Documentation.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 63

3 Using the PathWave FPGA Board Support Package (BSP)

Section 3.6: Loading k7z file into modules

After a bitstream file (k7z) is generated using the PathWave FPGA software, you may use either the
SD1 3.x software user interface or the SD1 API functions to load the FPGA on the corresponding
module and also, verify design compatibility on that module.

3.6.1: Using SD1 SFP user interface to load FPGA

To load the FPGA using SD1 3.x software,
1 From the Start menu, launch Keysight SD1 SFP.

2 From the main menu of a specific module’s dialog, click FPGA > Load firmware....

Figure 32 Accessing FPGA firmware loader option in SD1

64 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

3 On the Firmware Loader dialog that appears, click the button to browse for the required k7z file for

that particular module.

Figure 33 Firmware Loader window for the selected module

4Click Load to initiate the process of FPGA loading.

If the progress bar displays “Loading successful” and “100%”, it indicates that the FPGA is updated
as well as the FPGA design logic is compatible on hardware.

3.6.2: Using SD1 API to load FPGA - Basic workflow

To load the FPGA using SD1 3.x API,
1 Import system and Keysight SD1 libraries.
2 Open the module with open().
3 Load FPGA sandbox using *.k7z file with FPGAload().
4 (Optional) Read/Write into registers using functions defined in SD_SandboxRegister functions.
5 (Optional) Perform FPGA related operations using other functions defined in SD_Module

functions (specific to Pathwave FPGA).

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 65

3 Using the PathWave FPGA Board Support Package (BSP)

Section 3.7: Implementing BSP using SD1 API - Sample Programs

3.7.1: Sample program using Python for read write on sandbox region

# ----------------------------

# import required libraries

import sys

sys.path.append('C:\Program Files\Keysight\SD1\Libraries\Python')

import keysightSD1

# Set details for the connected module

product=''

chassis=1

slot=9

# open a module

module=keysightSD1.SD_Module()

moduleID=module.openWithSlot(product,chassis,slot)

if moduleID < 0:

print ("Module open error: ",moduleID)

else:

print("Module is: ",moduleID)

# Loading FPGA sandbox using the *.k7z file

error = module.FPGAload(r'..\myHardwareTest.k7z')

numRegisters = 4

# Get list of Registers from the sandbox

registers = module.FPGAgetSandBoxRegisters(numRegisters)

# Print the register properties in register list

for register in registers:

print(register.Name);

print(register.Length);

print(register.Address);

print(register.AccessType);

registerName = 'Register_Bank_A'

# Get Sandbox Register with name "Register_Bank_A"

registerA = module.FPGAgetSandBoxRegister(registerName)

# Write data to Register_Bank_A

66 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

error = registerA.writeRegisterInt32(9)

registerNameB = 'Register_Bank_B'

# Get Sandbox Register with name "Register_Bank_B"

registerB = module.FPGAgetSandBoxRegister(registerNameB)

# Write data to Register_Bank_B

error = registerB.writeRegisterInt32(9)

registerNameC = 'Register_Bank_C'

# Get Sandbox Register with name "Register_Bank_C"

sandbox_register_C = module.FPGAgetSandBoxRegister(registerNameC)

# Read data from Register_Bank_B

error = sandbox_register_C.readRegisterInt32()

memoryMap = 'Host_mem_1'

# Get Sandbox memoryMap with name "Host_mem_1"

memory_Map = module.FPGAgetSandBoxRegister(memoryMap)

# Write buffer to memory map

memory_Map.writeRegisterBuffer(0, [1,2,3, 4, 5, 6],
keysightSD1.SD_AddressingMode.AUTOINCREMENT, keysightSD1.SD_AccessMode.DMA)

# Read buffer from memory map

c_value = memory_Map.readRegisterBuffer(0, 6, keysightSD1.SD_AddressingMode.AUTOINCREMENT,
keysightSD1.SD_AccessMode.NONDMA)

print(c_value)

module.close()

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 67

3 Using the PathWave FPGA Board Support Package (BSP)

3.7.2: Sample program using .NET for read write on sandbox region

class Program

{

static void Main(string[] args)

{

SD_AOU awg = new SD_AOU();

// Open awg module

awg.open("", 1, 9);

//Loading FPGA sandbox using .K7z file

int error = awg.FPGAload(@"..\myHardwareTest.k7z");

//Get Sandbox register list

List<SD_SandBoxRegister> registers = awg.FPGAGetSandBoxRegisters(4);

//Print register properties

foreach(SD_SandBoxRegister register in registers)

{

Console.WriteLine(register.Name);

Console.WriteLine(register.Address);

Console.WriteLine(register.Length);

Console.WriteLine(register.AccessType);

}

int[] buffer = { 5, 4, 3, 2 };

int[] registerBuffer = new int[4];

//Write data buffer to register with index 0

registers[0].WriteRegisterBuffer(0, buffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.DMA);

//Read buffer from register with index 0

registers[0].ReadRegisterBuffer(0, registerBuffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.DMA);

SD_SandBoxRegister registerA= awg.FPGAGetSandBoxRegisterByName("Register_Bank_A");

//Write data to register Register_Bank_A

registerA.WriteRegisterInt32(2);

int registerBValue = registerA.ReadRegisterInt32();

SD_SandBoxRegister hostMem = awg.FPGAGetSandBoxRegisterByName("Host_mem_1");

int indexOffset = 2;

//Write data buffer to Host_mem_1 with indexOffset 2

68 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

hostMem.WriteRegisterBuffer(indexOffset, buffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.NONDMA);

//Read data buffer to Host_mem_1 with indexOffset 2

hostMem.ReadRegisterBuffer(indexOffset, registerBuffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.DMA);

}

}

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 69

3 Using the PathWave FPGA Board Support Package (BSP)

70 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators

User’s Guide

4. Using Keysight SD1 3.x SFP Software

Installing the Keysight SD1 3.x Software Package 73
Launching the Keysight SD1 SFP software 74
Understanding the SD1 SFP features & controls 76
Understanding AWG SFP features & controls 82

This chapter describes how to use Keysight SD1 SFP software.

4 Using Keysight SD1 3.x SFP Software

KeysightM3201A/M3202A PXIe AWGs, M3100A/M3102A PXIe Digitizers, and M3300A/M3302A
PXIe AWG/Digitizer Combos can be operated as classical bench-top instruments using Keysight SD1
SFP software; no programming is required.

Keysight SD1 SFP Software provides a fast and intuitive way of operating KeysightM3201A/M3202A
PXIe AWGs, M3100A/M3102A PXIe Digitizers, and M3300A/M3302A PXIe AWG/Digitizer Combos.

Based on your preference, you may also perform various operations using the programming library
provided within Keysight SD1 Core API. An API function is available for almost every control within
the user interface. You can build and run custom scripts to carry out various operations / workflow,
which can be performed by the SD1 SFP user interface.

The sections in this chapter cover the functionality of each SD1 SFP feature available in its user
interface, along with describing the workflow required to perform some specific operations.
Wherever applicable, the API function corresponding to the feature/control has been specified for
reference.

To know about the programming libraries and the available API functions, see Chapter 5, “Using
Keysight SD1 API Command Reference” followed by Chapter 6, “Using SD1 API functions in sample
programs”.

72 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

Section 4.1: Installing the Keysight SD1 3.x Software Package

The Keysight SD1 3.x Software Package includes:

• Keysight SD1 3.x SFP Software

• KF9000A PathWave FPGA Programming Environment (commonly known as PathWave FPGA

software)—required for FPGAlogic designing

• PathWave FPGA Board Support Package (BSP)—required for FPGAlogic designing

• KS2201A PathWave Test Sync Executive Software—required for integration with HVItechnology

Prior to installing the software package components listed above, the following software must be
installed on your machine that runs a Windows 10 (64-bit) Operating System.

Prerequisites • Keysight IO Libraries Suite 2018 (version 18.0 or later)

• Microsoft .NET 3.5 or later

• Any API interface

• Python 64-bit version 3.7.x or later

• Any C# /.NET Compiler

• Any C/C++ Compiler

• Xilinx Vivado Design Suite (required with PathWave FPGA software)

• License options

•Option -FP1 (to enable FPGA programming through PathWave FPGA BSP)

•Option -HV1 (to implement HVI technology using the PathWave Test Sync Executive software)

Refer to the SD1 3.x Software Startup Guide for download links and installation instructions.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 73

4 Using Keysight SD1 3.x SFP Software

Section 4.2: Launching the Keysight SD1 SFP software

After the Keysight SD1 3.x SFP software is installed, click Start > Keysight > Keysight SD1 SFP.

Figure 34 Launching SD1 SFP software from the Start menu

The Keysight SD1 3.x SFP software window is displayed, as shown in Figure 35 and Figure 36.

When SD1 SFP is launched, it identifies all Keysight PXIe hardware modules that are connected to
the embedded controller or desktop computer and opens a corresponding soft front panel for each
piece of hardware. As shown in Figure 35, the soft front panel for the M3201A AWG and M3302A
(AWG & Digitizer) Combo are displayed by default, which indicates these modules are connected.

Figure 35 SD1 SFP software window (online mode with M3201A and M3302A cards connected)

If one or more modules are not inserted into the chassis (or disconnected), the soft front panel for
each of such modules is displayed as “Demo module” on the Keysight SD1 3.x SFP software. See

Figure 36.

74 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

Figure 36 SD1 SFP software (offline mode without any card connected)

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 75

4 Using Keysight SD1 3.x SFP Software

Section 4.3: Understanding the SD1 SFP features & controls

As the name indicates, the Soft Front Panel (SFP) provides you controls so that you may configure
settings associated with the front panel features (namely, Channel, Clock and Trigger) on the
connected PXIe AWG, Digitizer and Combo cards. Considering the basic functionality of an AWG and
a Digitizer, the appearance and functions on each SFP window for AWG modules are different from
that for the Digitizer modules.

The SFP windows that are specific to AWG modules correspond to:

• M3202A AWG 1G

• M3201A AWG 500

• AWG front panel of the M3302A AWG 500 DIG 500 Combo

• AWG front panel of the M3300A AWG 500 DIG 100 Combo

The SFP windows that are specific to Digitizer modules correspond to:

• M3102A DIG 500

• M3100A DIG 100

• DIG front panel of the M3302A AWG 500 DIG 500 Combo

• DIG front panel of the M3300A AWG 500 DIG 100 Combo

The SD1 SFP user interface, primarily, consists of three types of windows:
1 Main window—includes controls for displaying each module window and hardware configuration.
2 AWG Module SFP window—includes front panel controls for performing operations pertaining to

AWGs.

3 Digitizer Module SFP window—includes front panel controls for performing operations pertaining

to Digitizers.

In the offline (Demo) mode, even though the front panel controls appear to be available and even
configurable, they are meant for demonstrative purposes only. On the other hand, when connected,
each module has its respective SFP window and all controls and functions are available. The
following sections describe the controls that appear on each window.

4.3.1: Understanding main window features and controls

Figure 37 shows the SD1 SFP main window without any overlapping SFP window.

Figure 37 SD1 SFP main window

The controls under each menu item are further described in the order displayed above.

76 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

1. File

Figure 38 Controls in the File menu

• Exit—Click File > Exit to close the SD1 SFP main window along with any SFP windows that may be

displayed.

2. Window

Figure 39 Controls in the Window menu

• The menu under Window lists the names assigned to the connected modules. By default, a tick

mark appears against each entry, indicating that the corresponding SFP window is active. Any
name that does not appear indicates that the module is not connected. An offline instance for
each module is available in the Demo Modules sub-menu.

1 To close any SFP window that is open, clear the tick from the corresponding entry.
2 To open an SFP window for a module that is connected, click the corresponding entry.

• Demo Modules—The drop-down sub-menu under Window > Demo Modules lists the names of each

module. You may perform the steps described above, but the corresponding SFP windows that
appear are meant for demonstration purpose only.

3. Help

Figure 40 Controls in the Help menu

• Hardware Manager...—Click Help > Hardware Manager... to launch the Hardware Manager window.

See “Understanding features in Hardware Manager” on page 78 for more information on features
available in the Hardware Manager window.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 77

4 Using Keysight SD1 3.x SFP Software

•About—Click Help > About to view the About Keysight SD1 SFP window. This window conveys the SD1

SFP software’s version installed on your machine.

Figure 41 About Keysight SD1 SFP window

4.3.2: Understanding features in Hardware Manager

The features in this window are described below in the order shown in Figure 42.

Figure 42 Hardware Manager window

78 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

1 File—The File menu has two items, which are:

Figure 43 Controls in the File menu for Hardware Manager

• Refresh HW list—This feature requires an active network connection to fetch information

from the database. Click File > Refresh HW list so that the SD1 SFP software checks the
Firmware database for any new Firmware version for each M3xxxA module that is
displayed in the Modules area below. If an updated firmware version is found
corresponding to one or more modules, the firmware version is updated/refreshed in the
Available FW Version list. Performing the Refresh HW list is recommended prior to
proceeding with Firmware update using the SD1 SFP software on one or more connected
modules.

• Load update package...—In case your machine is offline, that is, does not have an active

network connection, this feature is useful to load an updated and pre-saved firmware
package so that you can still proceed with firmware updates on one or more connected
M3xxxA modules. Click File > Load update package... to access the Load SDM package...
window, as shown in Figure 44. Navigate to the folder where the firmware update file is
saved. Open the required SDM package file with extension *.sdpkg. You may proceed with
firmware update on the module which the SDM package file corresponds to.

Figure 44 Accessing firmware update file from Load SDM package window

2 Help—The Help > Database Version to view the version of the Firmware update file Database

server.

Figure 45 Control in the Help menu for Hardware Manager

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 79

4 Using Keysight SD1 3.x SFP Software

NOTE

Figure 46 Database Version window

3 Software—This area displays the installed version of the Keysight SD1 SFP software and

programming libraries along with that of the compatible driver.

4 Module—This area consists of the following information:

• Chassis—the Chassis number where the M3xxxA cards are inserted into. Related API

• <M3xxxA>—the model number for one or more modules that are inserted into the specific

Keysight SD1 SFP 3.x software does not recognize cards that have
Firmware version less than 4.0 (for M32xxA/M33xxA modules) or less than

2.0 (for M31xxA modules).

function: “getChassis()”.

Chassis number. The following information is displayed for each module. Related API
function: “getType()”.

Figure 47 Information pertaining to each module in the Hardware Manager window

• Instance name—Product Name assigned to the software instance when the SD1 SFP

detects the connected module. Format is <M3xxxA>#<serial-number>. Related API
function: “getProductName()”.

• Serial Number—Serial number of the connected module. Related API function:

“getSerialNumber()”.

• Options—Hardware license options that are enabled on this module. Related API

function: “getOptions()”.

• HW Version—Hardware version of the module. Related API function:

“getHardwareVersion()”.

• Status—Indicates the current status of the module. ‘ok’ indicates devices is working

properly.

• HW PID—The Product ID number of the Hardware. Indicates which physical options

are available on the product.

• FW PID—The Product ID number of the Firmware. Indicates which firmware elements

are available on the product.

80 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

• Slot—the slot number in the Chassis where the M3xxxA module is inserted into. Related

API function: “getSlot()”.

• Firmware Version—the firmware version currently installed on each M3xxxA module.

Related API function: “getFirmwareVersion()”.

• Available FW Version—’None’ if only the modules are connected but the machine does not

have an active network connection; else, the latest firmware version number that is
available on the Database server.

• Update—By default, the option is ‘No’ for each module. Change to ‘Yes’ for one or more

modules where you wish to perform a firmware update.

5 Update Selected HW—Click the Update Selected HW button to proceed with firmware update on

your selected module, where you have set the Update flag to Yes . The SD1 SFP software then
displays a confirmation prompt asking you to verify if you wish to proceed with the firmware
update using the version listed in the Available FW Version list for the selected module on the
respective Chassis & Slot numbers. For firmware update instructions, refer to SD1 3.x Software
Startup Guide.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 81

4 Using Keysight SD1 3.x SFP Software

NOTE

Section 4.4: Understanding AWG SFP features & controls

For all those modules that are connected to the Chassis, the respective soft front panel for the
M3201A/M3202A PXIe AWG and that for the AWG part of the M3300A/M3302A Combo appear
automatically when SD1SFP is launched. By default, the SFP window for the AWG appears blank,
that is, without any configuration parameters, as shown for M3201A module in Figure 48.

The controls are common across all AWG SFP windows. However, the
number of AWGs / Channels that appear depends on the module type.
M32xxA modules support only 4 AWGs/Channels whereas the M33xxA
Combos support only 2 AWGs/Channels.

On this window,

• the default name, which is assigned by the SD1 SFP user interface, is displayed on the bar at the
top.

• the hardware options enabled on the module followed by the serial number, Chassis number and
Slot number are displayed on the bar at the bottom.

• most of the controls appear within the main menu items, which are explained in the following
section.

• a shortcut for some of the controls, which are available under the main menu items, are displayed
below the main menu.

Figure 48 SFP for the connected M3201A after SD1 SFP software is launched

82 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

4.4.1: Understanding AWG SFP main menu features & controls

The controls under each menu item are further described in the order displayed in Figure 48. Images
in this section pertain mainly to M3201A AWG module’s SFP only, but are applicable across all AWG
module SFP windows.

1. File

Figure 49 Controls in the File menu of the AWG SFP

• Change Name...—Click File > Change Name... to open the Change name module dialog box. This
feature works in the same manner for Digitizer SFPs also.

Figure 50 Change name module dialog box

•In the Name: text field, enter an alternate name of your choice.

•Click OK.

The new name appears on the bar at the top of the corresponding module’s SFP window.

• Hide—Click File > Hide to close the module’s SFP window instance.

• To show/open the same window again, click Window > <module name> from the main menu of
the Keysight SD1 SFP software. See description for “Window” in “Understanding main window

features and controls” on page 76.

2. Settings

Here, the controls for AWG are available in the upper part.

Figure 51 Controls in the Settings menu of the AWG SFP

• AWG External Triggers...—Click Settings > AWG External Triggers... to open the Configure AWG Triggers
dialog box. See “Setting the Configure AWG Triggers dialog” on page 87 for more description.

• Related API function: “AWGtriggerExternalConfig()”

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 83

4 Using Keysight SD1 3.x SFP Software

• AWG Memory...—Click Settings > AWG Memory... to open the Onboard waveform memory dialog box.
See “Setting the Onboard Waveform memory dialog” on page 87 for more description.

• AWG Configuration...—Click Settings > AWG Configuration... to open the AWG Configuration dialog
box. See “Setting the AWG Configuration dialog” on page 89 for more description.

• Related API functions: “AWGqueueSyncMode()”, “AWGqueueConfig()”,
“AWGqueueConfigRead()”

• AWG Queue—Click Settings > AWG Queue > AWGn... (where, n = AWG number) to open the
corresponding AWG n Waveform Queue dialog box. See “Setting the AWG Waveform Queue dialog”
on page 90 for more description.

• Related API functions: “AWGqueueWaveform()”, “AWGflush()”

Figure 52 Controls in AWG Queue sub-menu

• AWG Trigger—Click Settings > AWG Trigger > Send Trigger to send a trigger to the selected AWGs in
the same sub-menu. By default, all AWGs are selected.

• Related API functions: “AWGtrigger()”, “AWGtriggerMultiple()”

Figure 53 Controls in AWG Trigger sub-menu

•Click one or more AWG n (where, n = AWG number) entries to clear the tick mark; thereby,
refraining them from receiving the trigger when you click Send Trigger.

• Alternatively, you may use the shortcut controls to send trigger to AWGs.

Figure 54 Shortcut controls for sending trigger to AWGs

• Reset Accumulated Phase—Click Settings > Reset Accumulated Phase > Reset Phase to reset any
accumulated phase on the selected Channels in the same sub-menu. By default, all Channels are
selected.

• Related API functions: “channelPhaseReset()”, “channelPhaseResetMultiple()”

84 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

Figure 55 Controls in Reset Accumulated Phase sub-menu

•Click one or more Ch n (where, n = Channel number) entries to clear the tick mark; thereby,
refraining them from undergoing phase reset when you click Reset Phase.

• Alternatively, you may use the shortcut controls to reset phase on the Channels.

Figure 56 Shortcut controls for resetting accumulated phase on Channels

• Trigger/Clock...—Click Settings > Trigger/Clock... to open the Trigger / Clock Settings dialog box. See
“Setting the Trigger / Clock Settings dialog” on page 91 for more description.

• Related API functions: “triggerIOconfig()”, “clockIOconfig()”

3. View

Figure 57 Control in the View menu of the AWG SFP

• New Panel...—Click View > New Panel... to open the Add new panel dialog box.

Figure 58 Add new panel dialog box

•From the Channel: drop-down options, select a Channel number, which you wish to configure
on the connected AWG module.

•Click OK.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 85

4 Using Keysight SD1 3.x SFP Software

Figure 59 New panel for Channel configuration dialog box along with its various shortcut controls

• Repeat the previous steps to add more AWG Channels.

• Alternatively, you may click the shortcut icons shown in Figure 59 to open the Add new panel
dialog box.

The description for the attributes in the channel configuration panel is covered in “Setting up the

Channel configuration panel” on page 93.

4. FPGA

Figure 60 Control in the FPGA menu of the AWG SFP

• Load firmware...—Click FPGA > Load firmware... to open the Firmware Loader dialog box, where you
can load the bitstream file (*.k7z) onto the FPGA sandbox region of the corresponding module. For
more information on how to load the bitstream file onto the FPGA sandbox region, see “Using SD1

SFP user interface to load FPGA” on page 64.

• Related API function: “FPGAload()”

5. Help

Figure 61 Control in the Help menu of the AWG SFP

• Module User Guide...—Click Help > Module User Guide... to view the documentation corresponding
to AWG/Combo modules in Online Help format. For more information, see “Accessing Online Help

for SD1 3.x software” on page 252.

86 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

4.4.2: Configuring AWG and Channel Setting dialogs

1. Setting the Configure AWG Triggers dialog

If you are using an external trigger source to send trigger to one or more AWGs, you must configure
the Configure AWG Triggers dialog box.

Figure 62 Configure AWG Triggers dialog box

1 Select one or more rows to enable external triggering for AWG n, where n = AWG number.
2 Trigger Mode indicates the mode when the trigger signal must be sent. From the Trigger Mode

drop-down options, select one of the following options:

• Disabled—(default) indicates that external triggering is disabled for the selected AWG.

• Active High—indicates that the trigger signal must be sent when active high voltage on the
signal is attained.

• Active Low—indicates that the trigger signal must be sent when active low voltage on the signal
is attained.

• Rising Edge—indicates that the trigger signal must be sent when the rising edge on the signal is
attained.

• Falling Edge—indicates that the trigger signal must be sent when the falling edge on the signal
is attained.

3 Trigger Line indicates the line medium to be used for the trigger signal to be sent. This field is

enabled for all Trigger Mode options except for Disabled. From the Trigger Line drop-down options,
select one of the following options:

• Extern 1 / Extern 2—indicates that line 1 / line 2 from the external triggering source is used to
send the trigger signal.

• PXI n (where, n = 0 to 7)—indicates that lines 0 to 7 from the PXI trigger source can be used to
send the trigger signal.

4 Sync—By default, the setting to synchronize the AWG with the trigger source is enabled. You may

clear the check box to disable synchronization.

5Click OK to save any changes and return to the AWG module window.

2. Setting the Onboard Waveform memory dialog

You must configure the Onboard waveform memory dialog box to load a waveform (in *.csv file format)
onto the module’s onboard RAM.

By default, the Keysight SD1 SFP software provides some waveform files in *.csv format as examples
during installation. The default location for these files is C:\Users\Public\Documents\Keysight\SD1\

Examples\Waveforms. You may also create and save waveform files of your own and save them in
*.csv format.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 87

4 Using Keysight SD1 3.x SFP Software

Figure 63 Onboard waveform memory dialog box

1Click ‘+’ to view and add one or more waveform files from the local disk of your machine.

Alternatively, if you click the cell in the Source column, a folder icon appears, which you can click
to perform the same action.

Figure 64 Alternate way of browsing for waveform files

2From the Open window that appears, select a pre-defined waveform or navigate to select any

other waveform file of your choice and click Open.

Figure 65 Default waveform files folder displayed in Open window

The waveform file is added to the first row of the Onboard waveform memory dialog box.
The SD1 SFP software auto-assigns numbers in the Number column to each waveform file you

add. In the Name column, it displays the name defined for the waveform type in the CSV file. The
cell in the Source column displays the file location on the local disk of your machine.

88 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

Figure 66 Onboard waveform memory dialog box appearance after waveform files are added

3 In this dialog box, you may modify the following elements:

a Click ‘x’ that appears in column ‘1’ to remove a row. The SD1 SFP software prompts a

confirmation dialog. Click Yes to remove else No to retain.

b Number—Indicates the register number on the onboard memory where the waveform is loaded.

Double-click to edit one or more numbers in their respective cell to change the order of listing
of waveforms. The list is rearranged automatically to appear in ascending order of numbers.

c Name—Indicates the waveform type defined within the CSV file that you have opened. If

required, double-click to edit one or more names in their respective cell. Note that changing
the waveform name on the Onboard waveform memory dialog box does not change the name
within the CSV file on disk.

4 Repeat the previous steps to add one or more waveform files to this window and modify number

and names, if needed.

5Click OK to save any changes and return to the AWG module window.

3. Setting the AWG Configuration dialog

Each AWG block has a flexible waveform queue system that can be used to configure complex
generation sequences. To define the queue modes for each AWG, configure the AWG Configuration
dialog box.

Figure 67 AWG Configuration dialog box

1Click an AWGn (where, n = AWG number) tab to configure the queue modes. Note that the queue

configuration options that appear under each AWG tab are the same.

2 Select the Config check box so that the Queue Sync Mode and Queue Mode fields become

configurable.

3 Queue Sync Mode— This setting configures the synchronization mode of the queue. From the

drop-down options, select:

• Immediate—(default) Set this option to queue waveform immediately after AWG has started, or
when the previous waveform in the queue finishes.

• Sync 100 (10MHz)—Set this option to synchronize the AWG to the 10 MHz reference clock.

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 89

4 Using Keysight SD1 3.x SFP Software

4 Queue Mode—This setting configures the repetition cycles for the complete queue. From the

drop-down options, select:

• One Shot—(default) Set this option for the complete queue to be reproduced one time only.

• Cyclic—Set this option for the complete queue to be reproduced for more than one cycles.

5 Repeat steps 1 to 4 to configure AWG Queue modes for other AWG Channels.
6Click OK to save any changes and return to the AWG module window.

4. Setting the AWG Waveform Queue dialog

To define the order in which the waveforms must be queued along with their timing settings on each
AWG Channel, use the AWG n Waveform Queue (where, n = AWG Channel number). You can queue
only those waveforms, which have already been loaded onto the Onboard Waveform Memory.

Figure 68 AWG Waveform Queue dialog box

1Click ‘+’ to add one or more waveform files from the Onboard Waveform Memory.

Alternatively, if you double-click the cell in the Name column, it converts into a drop-down field,
where you can select a waveform from the list that is already loaded in the Onboard Waveform
Memory.

Figure 69 Alternate way of forming the waveform queue list

The SD1 SFP software auto-assigns position numbers in the Position column for each waveform
that you have included in the list. The Waveform column displays the waveform name as you have
set in the Onboard Waveform Memory window. By default, the Trigger Mode column is set to AUTO
whereas the Start Delay (ns), Cycles and Prescaler are set to ‘0’.

Figure 70 AWG Waveform Queue dialog box appearance after waveforms are added

90 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

2 In this dialog box, you may modify the following elements:

a Click ‘x’ that appears in column ‘1’ to remove a row. The SD1 SFP software prompts a

confirmation dialog. Click Yes to remove else No to retain.

b Position—Indicates the position where the waveform must appear in the generated queue.

Double-click to edit one or more numbers in their respective cell to change the order of
positioning of waveforms in the queue. The list is rearranged automatically to appear in
ascending order of numbers.

c Waveform—Indicates the waveform name as defined in the Onboard waveform memory dialog. If

you click ‘+’ to add waveforms on each row, it pulls the waveform name that appears in
waveform memory register # 0 by default. To change the waveform type, double-click the cell
in a specific row and select the waveform name from the drop-down list as shown in Figure 70.

d Trigger Mode—Indicates the triggering method to launch the waveforms queued in an AWG.

Double-click the cell for each row to modify the value. Select one of the following options:

• AUTO—(default) Trigger signal is set to launch waveform immediately after the AWG has

started or when the previous waveform in the queue finishes.

• SW/HVI START—Set this option so that the AWG is triggered by the condition set in the

Configure AWG Triggers dialog in the SD1 SFP software, provided that the AWG is running.

• SW/HVI CYCLE—Set this option so that the AWG is triggered by the condition set in the

Configure AWG Triggers dialog in the SD1 SFP software, provided that the AWG is running.
However, in this case, trigger is required for each waveform cycle.

• EXTERNAL START—Set this option so that the AWG is triggered by an external Trigger

source.

• EXTERNAL CYCLE—Set this option so that the AWG is triggered by an external Trigger

source. However, a trigger is required for each waveform cycle.

e Start Delay (ns)—Set the delay between the trigger and the waveform launch in tens of ns.
f Cycles—Set the number of times the waveform is played once launched. The value ‘0’ specifies

infinite cycles.

g Prescaler—Set the waveform prescaler value, to reduce the effective sampling rate by a value of

prescaler x 5.

3 Repeat the previous steps to add one or more waveforms to the queue and modify the settings as

required.

4Click OK to save any changes and return to the AWG module window.

5. Setting the Trigger / Clock Settings dialog

If you are using an External Trigger / Clock source, you can control the point when the trigger must
be applied. Use the Trigger / Clock Settings dialog to perform this action.

Figure 71 Trigger / Clock Settings dialog box

1 Select the check box for External Clock, External Trigger, or both to indicate which external source is

being used.

2 External Clock—From the Value drop-down options, select:

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 91

4 Using Keysight SD1 3.x SFP Software

• Output Disabled—indicates that the signal from the external clock source is not included in the
AWG output.

• Output Enabled—indicates that the signal from the external clock source is included in the AWG
output.

3 External Trigger—From the Value drop-down options, select:

• Input—Indicates that the signal from the external trigger source is used only to trigger the input
AWG waveform.

• Output + Input—Indicates that the signal from the external trigger source is used to trigger both
the AWG input and output waveforms.

4Click OK to save any changes and return to the AWG module window.

92 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

4.4.3: Setting up the Channel configuration panel

The main purpose of the AWG SFP window is to generate one or more waveforms per Channel. When
you add one or more new panels to the SFP window, the Channel configuration area panel appears
for the selected Channel. This section describes the various elements that are available in the
highlighted region in Figure 72. You may add more Channels to configure the waveform settings, as
needed. See “Understanding AWG SFP main menu features & controls” on page 83 to add new
panels.

Using Keysight SD1 3.x SFP Software 4

Figure 72 Channel configuration panel in M3xxxA AWG SFP window

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 93

4 Using Keysight SD1 3.x SFP Software

Consider Figure 73 to understand each element of the Channel configuration panel in the order
shown.

Figure 73 Various features on the Channel configuration panel

1. Channel n

• The title of each panel is set for the Channel number you select when adding a new panel. Here, n
represents the Channel number, which is different for the type of M3xxxxA module you select.

• M3202A AWG 1G — 4 Channels

• M3200A AWG 500 — 4 Channels

• M3302A AWG 500 DIG 500 — 2 AWG Channels

• M3300A AWG 500 DIG 100 — 2 AWG Channels

The number of Channels depend on the selected module’s AWG SFP window.

2. Main

• This tab contains the primary elements to generate waveforms using the internal Function
Generator or the Arbitrary Waveform Generator along with the settings to configure the
waveform’s display characteristics.

3. Waveform shape

• This drop-down contains the primary elements to generate waveforms using the internal Function
Generator or the Arbitrary Waveform Generator along with the settings to configure the
waveform’s display characteristics. Note that the SFP starts generating the waveforms using the
Function Generator as soon as you select one from the list.

• Related API function: “channelWaveShape()”

Figure 74 Options in the Waveform shape drop-down box

• Off—The output signal is set to ‘0’. All other channel settings are maintained.

• Sinusoidal—The output signal is generated as sinusoidal. It is generated by the Function
Generator.

• Triangular—The output signal is generated as triangular. It is generated by the Function
Generator.

• Square—The output signal is generated as square. It is generated by the Function Generator.

94 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

• DC Voltage—The output signal is generated as a DC Signal. It is generated by the Function
Generator.

• AWG n (n = AWG number for the respective Channel)—The output signal is generated based on
the waveforms defined within the AWG Queue for the respective AWG. See “Setting the AWG

Waveform Queue dialog” on page 90 for more information. It is generated by the Arbitrary

Waveform Generator.

• Partner Channel—Only an even numbered channel (according to Keysight Channel numbering
format) can be set as a partner to the previous odd numbered channel (for example, CH2 is a
partner to CH1). The waveform queue, load and start functions defined for the odd numbered
channel are automatically called for the respective partner channel.

• HiZ—Selecting this check box indicates that the output signal is set to HIZ (High Impedance)
and no output signal is provided. This feature is available for Keysight M3202A PXIe AWG
models only.

Figure 75 HiZ option available in M3202A PXIe AWG models

4. Controls for Amplitude, Frequency, Phase & DC offset

The four parameters define the waveform characteristics that is being generated.

• Amplitude—defines the amplitude range on the waveform generated by both the Function
Generator and the Arbitrary Waveform Generator. The number of Waveform points set for each
waveform type is multiplied by the value set in the user interface to determine the actual
amplitude. Default unit is ‘Volts’ and the range is between ‘±1.5V’ for all AWG modules.

• Related API function: “channelAmplitude()”

• Frequency (MHz)—defines the frequency of transmission on the waveform generated by the
Function Generator only. Default unit is ‘MHz’ and can be set to a maximum value of ‘200 MHz’
for all AWG modules that have sampling rate of 500 MSa/s whereas M3202A AWG with 1GSa/s
has a maximum frequency limit of ‘400 MHz’. Note that for the waveforms generated by the AWG,
the frequency is defined within the CSV file and not controlled via the SD1 user interface.

• Related API function: “channelFrequency()”

• Phase—defines the phase of the output waveform generated by the Function Generator only.
Default unit is ‘Degrees’ and the range is between ‘±360’ for all AWG modules. This phase is
continuous and can be made coherent by using the “Reset Accumulated Phase” feature for the
respective Channel number. See description for “Reset Accumulated Phase” in “Understanding

AWG SFP main menu features & controls” on page 83 for more information. Note that for the

waveforms generated by the AWG, the phase is defined within the CSV file and not controlled via
the SD1 user interface.

• Related API function: “channelPhase()”

• DC offset—defines the offset range on the waveform generated by both the Function Generator
and the Arbitrary Waveform Generator. The number of Waveform points set for each waveform
type is multiplied by the value set in the user interface to determine the actual offset. Default unit
is ‘Volts’ and the range is between ‘±1.5V’ for all AWG modules.

• Related API function: “channelOffset()”

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 95

4 Using Keysight SD1 3.x SFP Software

The controls for configuring values work in the same manner across all AWG SFP windows.

• Horizontal sliders—By default, markers in the center indicate that the respective parameter range
between both negative and positive values, whereas the markers that appear on the left indicate
only positive values.

• Editable value field—Click within the field where the value for each parameter is shown and edit
the respective values.

• Vertical sliders—Included each value field is a vertical slider for incrementing or decrementing the
values within the defined ranges.

5. Using the Channel Visualization Settings dialog

To access the Channel Visualization Settings dialog, click the icon on the Channel configuration
panel.

Figure 76 Default Channel Visualization Settings dialog for M3202A AWG 1G module

Figure 77 Default Channel Visualization Settings dialog for all other AWG modules

This dialog box provides advanced settings for each of the parameters that are displayed up front on
the Channel configuration panel. Here, you can:

• Define minimum and maximum values within the defined ranges for each parameter

• Define custom step sizes used for incrementing/decrementing the values in the defined range

• Define other options as units for each parameter as shown in Tabl e 2 3.

• Define values by entering in the value fields or using the vertical sliders.

•Click OK to save any changes and return to the AWG module window.

96 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

Using Keysight SD1 3.x SFP Software 4

Table 23 Alternate units and range values for each parameter

\

Parameter Alternate units

Minimum Maximum

Amplitude Volts -1500.0 1500.0

Range value

Hz 0.00 200000000.00

Frequency

kHz 0.00 200000.00

Phase (default step size is 0.17) rad (Radians) -6.28 6.28

DC offset Volts -1500.0 1500.0

400000000.00 (for AWG 1G)

400000.00 (for AWG 1G)

6. Modulation

On the Channel configuration panel, click the Modulation tab to view the settings to include one or
more modulating signals in the output waveform from the Function Generator or the AWG.

Figure 78 Default view of the Modulation tab

Figure 79 Options available in each segment of the Modulation tab

You may choose to include the following combinations of modulation signals from the drop-down
options in each segment. If required, set the deviation value for the corresponding field:

• Disabled (default option, no modulation signal will be included)

• Frequency Modulation only—Related API function: “modulationAngleConfig()”

• Phase Modulation only—Related API function: “modulationAngleConfig()”

• Amplitude Modulation only—Related API function: “modulationAmplitudeConfig()”

• Offset Modulation only—Related API function: “modulationAmplitudeConfig()”

• Both Frequency and Amplitude Modulation

• Both Frequency and Offset Modulation

• Both Phase and Amplitude Modulation

• Both Phase and Offset Modulation

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide 97

4 Using Keysight SD1 3.x SFP Software

• IQ Modulation only (deviation is not required to be set)—Related API function:
“modulationIQconfig()”

For more information regarding the Angle and Amplitude modulation techniques available here, see
“Working with Signal Modulation” on page 29. Once configured, you may switch to the Main tab to
view the applied modulation signal. See Figure 80 for an example.

Figure 80 Single/Combination of modulation signals applied

7. AWG

As mentioned earlier, the standard waveforms using the Function Generator start generating as soon
as you select a waveform from the drop-down options for Waveform shape. However, if you select the
AWG n option, you must manually click the Play button, as shown in Figure 81, to start waveform
generation using the AWG, as defined in the AWG Waveform Queue window. If modulation is applied,
the modulation signal is added to the output waveform. As explained earlier, only Amplitude and DC
Offset parameter values can be modified on these waveforms.

• Related API functions: “AWG()”, “AWGstart()”, “AWGstartMultiple()”, “AWGpause()”,
“AWGpauseMultiple()”, “AWGresume()”, “AWGresumeMultiple()”, “AWGstop()”,
“AWGstopMultiple()”

Figure 81 Play button to generate AWG waveforms only

98 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide

SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators

User’s Guide

5. Using Keysight SD1 API Command Reference

Keysight Supplied Native Programming Libraries 100
Support for Other Programming Languages 101
Functions in SD1 Programming Libraries 102
SD_Module functions 115
SD_AOU functions 135
SD_Wave functions 213
SD_Module functions (specific to Pathwave FPGA) 218
SD_SandboxRegister functions 228

Programs can run on an embedded controller or desktop computer and be controlled with Keysight
SD1 Programming Libraries. Keysight supplies a comprehensive set of highly optimized software
instructions that controls off-the-shelf functionalities of Keysight hardware. These software
instructions are compiled into the Keysight SD1 Programming Libraries. The use of customizable
software to create user-defined control, test and measurement systems is commonly referred as
Virtual Instrumentation. In Keysight documentation, the concept of a Virtual Instrument (or VI)
describes user software that uses programming libraries and is executed by a computer.

5 Using Keysight SD1 API Command Reference

Section 5.1: Keysight Supplied Native Programming Libraries

Keysight provides ready-to-use native programming libraries for a comprehensive set of
programming languages, such as C, Visual Studio (C#, VB), Python, etc., ensuring full software
compatibility and seamless multi-vendor integration. Ready-to-use native libraries are supplied for
the following programming languages and compilers:

Table 24 List of programming languages and compilers

Language Compiler Library Files

Microsoft Visual Studio .NET .NET Library *.dll

C

C++ Any C++ compiler Header only *.h

C# Microsoft Visual Studio .NET .NET Library *.dll

Python Any Python compiler Python Library *.py

Basic Microsoft Visual Studio .NET .NET Library *.dll

MinGW (Qt)

C Library *.h, *.lib

Any C compiler

100 SD1 3.x Software for M320xA / M330xA Arbitrary Waveform Generators User’s Guide