SD1 3.x Software for
M310xA / M330xA Digitizers
User’s Guide
Notices
CAUTION
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M3xxx-90004
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1.2, February 2021
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Contents
1 Understanding PXIe Digitizers Theory of Operation
2 Using the KS2201A PathWave Test Sync Executive Software
Understanding Digitizer’s operation / 11
Channel Numbering and Compatibility Mode / 11
Input settings / 12
Full Scale, Impedance and Coupling 12
Prescaler 13
Analog Trigger / 14
Data Acquisition (DAQs) / 15
Operation 15
DAQ Trigger 17
Working with I/O Triggers / 19
Working with Clock System / 20
Chassis Clock Replacement for High-Precision Applications 20
CLK Output Options / 20
FlexCLK Technology (models w/ variable sampling rate) / 20
Licensing for KS2201A PathWave Test Sync Executive software / 24
Comparing ProcessFlow GUI with KS2201A HVI API / 25
Working with KS2201A PathWave Test Sync Executive software / 26
Overview on HVI technology / 26
Understanding the HVI elements used in SD1 API / 27
Description of various HVI elements / 28
HVI Engine 28
HVI Actions 28
HVI Events 28
HVI Trigger 28
HVI Instructions 28
FPGA sandbox registers 28
Implementing HVI in SD1 API - Sample Programs / 29
Sample program using Python for HVI instructions / 29
3 Using the PathWave FPGA Board Support Package (BSP)
Licensing for PathWave FPGA BSP support / 32
Comparing FPGAFlow with PathWave FPGA / 33
Differences between FPGAFlow and PathWave FPGA / 33
New features in PathWave FPGA / 33
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 3
Working with PathWave FPGA software / 34
Understanding Partial Configuration (PR) / 35
Using BSP with PathWave FPGA software / 37
Understanding BSP composition / 37
Generating a k7z file using PathWave FPGA BSP / 39
Loading k7z file into modules / 48
Using SD1 SFP user interface to load FPGA / 48
Using SD1 API to load FPGA / 49
Implementing BSP using SD1 API - Sample Programs / 50
Sample program using Python for read write on sandbox region / 50
Sample program using .NET for read write on sandbox region / 52
4 Using Keysight SD1 3.x SFP Software
Installing the Keysight SD1 3.x Software Package / 55
Launching the Keysight SD1 SFP software / 56
Understanding the SD1 SFP features & controls / 58
Understanding main window features and controls / 58
File 59
Window 59
Help 59
Understanding features in Hardware Manager / 60
Understanding Digitizer SFP features & controls / 64
Understanding DIG SFP main menu features & controls / 65
File 65
Settings 65
FPGA 66
Help 67
Other DIG SFP features & controls / 67
Time 67
Display 67
Points 67
Trigger 67
Channel 68
Single 68
Run 68
Frequency 68
Window 70
Channel n 70
Display 70
Configuring DAQ and Trigger/Clock Setting dialogs / 70
Setting the Configure DAQ Triggers dialog 70
4 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Setting the DAQ Settings dialog 71
Setting the Trigger / Clock Settings dialog 71
5 Using Keysight SD1 API Command Reference
Keysight Supplied Native Programming Libraries / 74
Support for Other Programming Languages / 75
Functions in SD1 Programming Libraries / 76
Common References to parameter values / 79
Data transfer rates / 83
Latency in Digitizers for various HVI Actions & Instructions / 84
HVI related latency in FPGA User Sandbox 84
TriggerIO and Action Groups 86
SD_Module functions / 88
open / 88
close / 90
moduleCount / 91
getProductName / 92
getSerialNumber / 93
getChassis / 94
getSlot / 95
PXItriggerWrite / 96
PXItriggerRead / 97
getFirmwareVersion / 98
getHardwareVersion / 99
getOptions / 100
getTemperature / 102
getType / 103
isOpen / 104
translateTriggerIOtoExternalTriggerLine / 105
translateTriggerPXItoExternalTriggerLine / 106
runSelfTest / 107
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 5
SD_AIN functions / 108
channelCoupling / 108
channelFullScale / 109
channelImpedance / 110
channelInputConfig / 111
channelMaxFullScale / 112
channelMinFullScale / 113
channelPrescaler / 114
channelPrescalerConfig / 115
channelPrescalerConfigMultiple / 117
channelTriggerConfig / 118
DAQanalogTriggerConfig / 120
DAQconfig / 122
DAQdigitalTriggerConfig / 126
DAQread / 127
DAQstart / 129
DAQstartMultiple / 131
DAQstop / 132
DAQstopMultiple / 133
DAQpause / 134
DAQpauseMultiple / 135
DAQresume / 136
DAQresumeMultiple / 137
DAQflush / 138
DAQflushMultiple / 139
DAQnPoints / 140
DAQtrigger / 141
DAQtriggerMultiple / 142
DAQtriggerConfig / 143
DAQcounterRead / 144
triggerIOconfig / 145
triggerIOwrite / 146
triggerIOread / 148
clockSetFrequency / 149
clockGetFrequency / 151
clockGetSyncFrequency / 153
clockIOconfig / 155
clockResetPhase / 156
DAQbufferPoolConfig / 158
DAQbufferAdd / 159
DAQbufferGet / 160
6 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
DAQbufferPoolRelease / 161
DAQbufferRemove / 162
DAQtriggerExternalConfig / 163
FFT / 164
voltsToInt / 165
SD_Module functions (specific to Pathwave FPGA) / 166
FPGAgetSandBoxRegister / 166
FPGAgetSandBoxRegisters / 167
FPGAload / 168
FPGAreset / 169
FPGATriggerConfig / 170
FPGAconfigureFromK7z / 171
FPGAGetKernelUUID / 172
User FPGA HVI Actions/Events / 173
Module HVI Engine / 174
Module HVI Triggers / 175
SD_SandboxRegister functions / 176
readRegisterBuffer / 176
readRegisterInt32 / 177
writeRegisterBuffer / 178
writeRegisterInt32 / 179
Properties / 180
6 Using SD1 API functions in sample programs
Basic Work Flow for the Digitizer / 182
Implementing SD1 API functions — Sample Programs / 183
Sample program for the overall Digitizer work flow using Python / 183
Sample program for Auto-triggering input waveform using Python / 184
Sample program for DAQ multiple triggering using Python / 188
Sample program for PXI triggering on DAQs using Python / 191
7 Understanding Error Codes in SD1 API
Description of Error & Warning IDs / 196
Description of SD1 Error IDs / 196
Description of SD1 Warning IDs / 198
8 Documentation References
Accessing Online Help for SD1 3.x software / 200
Links to other documents / 201
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 7
Index
8 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
SD1 3.x Software for M310xA / M330xA Digitizers
User’s Guide
1. Understanding PXIe Digitizers Theory of Operation
Understanding Digitizer’s operation 11
Working with I/O Triggers 19
Working with Clock System 20
1 Understanding PXIe Digitizers Theory of Operation
Keysight M31/M33XX digitizers are part of the new M3XXXA family of FPGA-programmable AWGs
and Digitizers. These high-performance digitizers with high channel density have an advanced data
acquisition system (DAQ), includes easy-to-use programming libraries and provides optional
real-time sequencing and decision making capability using the Hard Virtual Instrumentation (HVI)
technology with precise timing and multi-module synchronization. Graphical FPGA programing
allows for FPGA customization without HDL programming expertise and performance penalty. This is
a new family of FPGA-Programmable Digitizers with precise multi-module synchronization and real
time sequencing technology (HVI).
10 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Understanding PXIe Digitizers Theory of Operation 1
Section 1.1: Understanding Digitizer’s operation
The M31/M33XXA Digitizers has a flexible and powerful input structure to acquire signals (Figure 1).
Figure 1 M31/M33XXA Digitizers input functional block diagram
1.1.1: Channel Numbering and Compatibility Mode
Tabl e 1 shows Keysight standards for the output labeling (channel enumeration starts with CH1).
Compatibility mode, which can be changed by open(), is available to support legacy modules and
allows the channel numbering (channel enumeration) to start with either CH0 or CH1.
Modules are opened by default with the enumeration mode of its front panel. However, it is possible
to open them in compatibility mode, forcing enumeration to the selected option. This option might
be needed when different modules coexist.
Table 1 Compatibility mode options
Option Description Name Value
Legacy Channel enumeration starts with CH0 COMPATIBILITY_LEGACY 0
Keysight Channel enumeration starts with CH1 COMPATIBILITY_KEYSIGHT 1
Legacy modules refer to SD1 modules that were manufactured by Signadyne before they were
acquired by KeysightTechnologies. If the hardware equipment configuration being used only
contains modules from KeysightTechnologies, channel enumeration should start with CH1.
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 11
1 Understanding PXIe Digitizers Theory of Operation
1.1.2: Input settings
The M31/M33XXA Digitizers provides a block that allows the user to configure all the input settings
such as input impedance, full scale, coupling, prescaler, and so on.
Figure 2 Input settings in the M31/M33XXA Digitizers functional block diagram
Full Scale, Impedance and Coupling
Depending on the product specifications the user can configure the input full scale value, the input
impedance (Tab le 2) and the input coupling (Tab le 3).
Product-dependent Settings: This section describes all the possible input settings, but in reality they
are product-dependent. Check the corresponding Product Data Sheet to see if they are applicable.
Table 2 Input Impedance options
Option Description Name Value
High Impedance Input impedance is high (value is product dependent, check the
corresponding Data Sheet)
50Ω Input impedance is 50Ω AIN_IMPEDANCE_50 1
Table 3 Input Coupling options
Option Description Name Value
DC DC coupling AIN_COUPLING_DC 0
AC AC coupling AIN_COUPLING_AC 1
AIN_IMPEDANCE_HZ 0
12 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Understanding PXIe Digitizers Theory of Operation 1
NOTE
The full scale parameter adjusts automatically the input gain to maximize the input dynamic range.
Tabl e 4 shows the accepted range of voltage values for full scale, as a function of impedance.
Table 4 Full Scale Voltage range as a function of Impedance
Impedance Option Voltage range for DIG500 Voltage range for DIG100
HiZ 0.1V to 8V 0.1V to 10V
50Ω 0.0625V to 4V 0.2V to 3V
Prescaler
The prescaler is used to reduce the effective input sampling rate, capturing 1 out of n samples and
discarding the rest. The resulting sampling rate is as follows:
Figure 3 Resulting sampling rate when prescaler is applied
where, f
fs = f
is final effective sampling frequency
s
f
CLKsys
/ (5 * prescaler)
CLKsys
is the Clock System
prescaler is an integer value (4 bits)
Prescaler vs. Downsampling/Decimation:The prescaler cannot be
considered as a full decimation or down-sampling block as it does not
contain any filters and therefore, it generates aliasing. For applications
where full downsampling is required, you must choose an IF Keysight
Digitizer or Transceiver, which provides DDC (Digital Down Conversion).
Table 5 Programming functions related to the input prescaler
Function Name Description API function
channelPrescalerConfig Configures the input prescaler channelPrescalerConfig()
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 13
1 Understanding PXIe Digitizers Theory of Operation
1.1.3: Analog Trigger
The analog trigger block processes the input data and generates a digital trigger that can be used by
any Data Acquisition Block (“Data Acquisition (DAQs)” on page 15).
Figure 4 Analog trigger processor in the M31/M33XXA Digitizers functional block diagram
You can select the threshold and the trigger mode. The available trigger modes are shown in Table 6 .
Table 6 Analog Trigger Mode options
Option Description Name Value
Positive Edge Trigger is generated when the input signal is rising and crosses the
threshold
Negative Edge Trigger is generated when the input signal is falling and crosses the
threshold
Both Edges Trigger is generated when the input signal crosses the threshold, no
matter if it is rising or falling
Table 7 Programming functions related to analog triggers
Function Name Description API function
channelTriggerConfig Configures the analog trigger for each channel channelTriggerConfig()
AIN_RISING_EDGE 1
AIN_FALLING_EDGE 2
AIN_BOTH_EDGES 3
14 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
1.1.4: Data Acquisition (DAQs)
The Data Acquisition (DAQ) is a powerful and flexible block which acquires incoming words and
sends them to the user PC using dedicated DMA channels (Figure 5).
Understanding PXIe Digitizers Theory of Operation 1
Figure 5 DAQ units in the M31/M33XXA Digitizers functional block diagram
Operation
The words acquisition requires two easy steps:
1 Configuration: A call to the function “DAQconfig()” allows the user to configure, among others,
the trigger method (Table 8 ), the number of DAQ cycles to perform (number of triggers), the
number of acquired words per cycle (DAQpointsPerCycle), and the number of words that must be
acquired before interrupting the PC (DAQpoints). Figure 6 illustrates the flexibility of the DAQ
block operation.
2 Data read:
a Using “DAQread()”: a blocking/non-blocking function that returns the array of acquired words
(DAQdata).
b Using a callback function: a user function that is automatically called when the configured
amount of data (set with DAQpoints) is available.
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 15
1 Understanding PXIe Digitizers Theory of Operation
Figure 6 M31/M33XXA Digitizers words acquisition operation
Pausing and Resuming the DAQ: The function “DAQpause()” pauses the DAQ operation (triggers are
discarded). The acquisition can be resumed calling “DAQresume()”. A “DAQstop()” is performed
automatically when the DAQ block reaches the specified number of acquisition cycles.
Figure 7 Examples of the DAQ operation
Onboard memory and DAQpoints selection: The acquired words are first stored in a DAQ buffer
located in the module onboard RAM and then sent to the PC RAM via the ultra-fast PXI Express bus
(Figure 6) using dedicated DMA channels. This DAQ buffer, and therefore the minimum amount of
onboard RAM needed for an application, is directly the size of the data array, which you want to
16 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Understanding PXIe Digitizers Theory of Operation 1
NOTE
receive in each “DAQread()” or callback function call. This data array, called (DAQdata), contains
(DAQpoints) words. Therefore, its size is calculated as DAQpoints x 2 bytes/word (in the case of the
M31/M33XXA Digitizers). The size of this DAQ buffer must be chosen according to two criteria:
• High speed transients: the DAQ onboard buffer can store bursts of words at higher rates than the
PXIe and the computer can handle. Larger buffers allow handling longer high speed bursts.
• PC load: The DAQ buffer must be chosen to allow the PC enough time to process each DAQ buffer
(DAQdata) and to handle interrupts and process-context switching tasks. For example, if a
computer requires 500 ms to process DAQdata, the buffer size must be such that it can store more
than 500 ms of input words without interrupting the computer. The DAQ block facilitates the task
of adjusting the PC processing rate with the introduction of the DAQ cycles (Figure 6).
The amount of required PC RAM is double the amount of required onboard
RAM.
Prescaler: The DAQ block has an input prescaler which can be configured to discard words, reducing
the effective acquisition data rate “DAQconfig()”.
DAQ counter: The DAQ block has a dedicated counter to store the number of acquired words since the
last call to “DAQconfig()” or “DAQflush()”. This counter can be read with “DAQcounterRead()”.
DAQ Trigger
As previously explained, you can configure the trigger for the acquisition. The available trigger modes
for the DAQ are shown in Tab le 8 . Note that not all trigger methods are available in all modules.
Table 8 DAQ Trigger Mode options
Option Description Name Value
Auto (Immediate) The acquisition starts automatically after a call to function DAQstart AUTOTRIG 0
Software / HVI Software trigger. The acquisition is triggered by the function DAQtrigger,
Hardware Digital
Tri gger
Hardware Analog
Tri gger
DAQtrigger provided that the DAQ is running. DAQtrigger can be
executed from the user application (VI) or from an HVI.
Hardware trigger. The DAQ waits for an external digital trigger (see
Table 9 External Hardware Digital Trigger Source for the DAQ).
Hardware trigger. The DAQ waits for an external analog trigger (only
products with analog inputs).
As shown in Tab le 8, you have the following options for hardware triggers:
• Hardware Digital Trigger: If the DAQ is set to use a digital hardware trigger, you must configure it
using the function “DAQdigitalTriggerConfig()”. The available digital hardware trigger options are
shown in Tab le 9 and Table 1 0. If external I/O trigger is selected in “DAQdigitalTriggerConfig()”,
you must configure additional settings of this particular I/O line, such as input/output direction,
sampling/synchronization options, etc. (“Working with I/O Triggers” on page 19).
• Hardware Analog Trigger: (Only products with analog inputs) If the DAQ is set to use an analog
hardware trigger, you must configure it using the function “DAQanalogTriggerConfig()”. The
Analog Trigger Block of the corresponding analog input channel must also be configured.
SWHVITRIG 1
HWDIGTRIG 2
HWANATRIG 3
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 17
1 Understanding PXIe Digitizers Theory of Operation
Table 9 External Hardware Digital Trigger Source for the DAQ
Option Description Name Value
External I/O
Tri gger
PXI Trigger PXI form factor only. The DAQ trigger is a PXI trigger line and it is
Table 10 Trigger behavior for the DAQ
Option Description Name Value
None No trigger has been activated TRIGGER_NONE 0
Active High Trigger is active when it is at level high TRIGGER_HIGH 1
Active Low Trigger is active when it is at level Low TRIGGER_LOW 2
Rising Edge Trigger is active on the rising edge TRIGGER_RISE 3
Falling Edge Trigger is active on the falling edge TRIGGER_FALL 4
The DAQ trigger is a TRG connector/line of the product (I/O Triggers).
PXI form factor only: this trigger can be synchronized to CLK10.
synchronized to CLK10.
TRIG_EXTERNAL 0
TRIG_PXI 1
18 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Understanding PXIe Digitizers Theory of Operation 1
Section 1.2: Working with I/O Triggers
The M3100A/M3102A PXIe Digitizers have general purpose input/output triggers (TRG
connectors/lines). A trigger can be used as a general purpose digital IO or as a trigger input, and can
be sampled using the options shown below in Trigger Synchronization/Sampling Options.
Table 11 I/O Trigger types and corresponding functions
Typ e Description Name Value
Trigger Output (readable) TRG operates as a general purpose digital output signal, that can be written
by the user software.
Trigger Input TRG operates as a trigger input, or as general purpose digital input signal,
that can be read by the user software.
Table 12 Trigger Synchronization options
Typ e Description Name Value
Non-synchronized mode The trigger is sampled with an internal 100 MHz clock. SYNC_NONE 0
Synchronized mode (PXI form factor only) The trigger is sampled using CLK10. SYNC_CLK10 1
AIN_TRG_OUT 0
AIN_TRG_IN 1
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 19
1 Understanding PXIe Digitizers Theory of Operation
Section 1.3: Working with Clock System
The M3100A/M3102A PXIe Digitizer uses an internally generated high-quality clock (CLKref) which is
phase-locked to the chassis clock. Therefore, this clock is an extremely jitter-cleaned copy of the
chassis clock. This implementation achieves a jitter and phase noise above 100 Hz which is
independent of the chassis clock, depending on it only for the absolute frequency precision and long
term stability. A copy of CLKref is available at the CLK connector.
CLKref is used as a reference to generate CLKsys, the high-frequency clock used to sample data.
Chassis Clock Replacement for High-Precision Applications
For applications where clock stability and precision is crucial (for example: GPS, experimental
physics, etc.), you can replace the chassis clock with an external reference.
In the case of PXI/PXIe, this is possible via a chassis clock input connector or with a PXI/PXIe timing
module. These options are not available in all chassis; see the corresponding chassis specifications.
1.3.1: CLK Output Options
Table 13 Clock Output options
Options Description Name Value
Disable The CLK connector is disabled. N/A 0 (default)
CLKref Output A copy of the reference clock is available at the CLK connector. N/A 1
1.3.2: FlexCLK Technology (models w/ variable sampling rate)
The sampling frequency of the M3100A/M3102A PXIe Digitizers (CLKsys frequency) can be changed
using the advanced clocking system.
Figure 8 Block Diagram depicting the Advanced Flex Clock System in PXIe DIGs
FlexCLK System, where:
• CLKref is the internal reference clock, and is phase-locked to the chassis clock.
• CLKsys is the system clock used to sample data.
20 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Understanding PXIe Digitizers Theory of Operation 1
• CLKsync is an internal clock used for the synchronization features of the M3100A/M3102A PXIe
Digitizers.
• PXI CLK10 is the 10 MHz clock of the PXI/PXIe backplane.
The CLKsys frequency can be changed within the range indicated in the Data Sheet of the
corresponding product [clockSetFrequency()]. The CLKsync frequency changes with the CLKsys
frequency as per the following equation:
f
= GreatestCommonDivisor (f
CLKsync
PXI_CLK10
, f
CLKsys
/ 5)
The CLKsync frequency is returned by clockSetFrequency().
Table 14 CLKsync frequency mode options
Options Description Name Value
Low Jitter Mode The clock system is set to achieve the lowest jitter, sacrificing tuning speed. CLK_LOW_JITTER 0
Fast Tuning Mode The clock system is set to achieve the lowest tuning time, sacrificing jitter
performance.
CLK_FAST_TUNE 1
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 21
1 Understanding PXIe Digitizers Theory of Operation
22 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
SD1 3.x Software for M310xA / M330xA Digitizers
User’s Guide
2. Using the KS2201A PathWave Test Sync Executive Software
Licensing for KS2201A PathWave Test Sync Executive software 24
Comparing ProcessFlow GUI with KS2201A HVI API 25
Working with KS2201A PathWave Test Sync Executive software 26
Understanding the HVI elements used in SD1 API 27
Implementing HVI in SD1 API - Sample Programs 29
This chapter provides an introduction to the KS2201A PathWave Test Sync Executive Software and
describes its implementation in the SD1 3.x API. For detailed information about the KS2201A
PathWave Test Sync Executive Software and its API, refer to the KS2201A PathWave Test Sync
Executive Software User Guide.
2 Using the KS2201A PathWave Test Sync Executive Software
Section 2.1: Licensing for KS2201A PathWave Test Sync Executive software
Hardware license option (-HV1) on the M3xxxA modules
All M3xxxA modules support HVI technology. However, the hardware license option -HV1 must be
available on each module that is required to be programmed using the KS2201A PathWave Test
Sync Executive software and for usability with SD1 3.x software. The newer M3xxxA cards are
shipped with the newest versions of firmware and SD1 software, which support the PathWave Test
Sync Executive software. During procurement, you may choose to procure the -HV1 hardware
option.
To use an older module with the KS2201A PathWave Test Sync Executive software, the firmware and
SD1 software must be upgraded. KS2201A PathWave Test Sync Executive software requires that
Keysight SD1 SFP software version 3.x be installed on the same machine. Also, the PXIe M3xxxA
modules products must have Firmware versions greater than or equal to 4.0 (for M320xA AWGs /
M330xA Combos) and greater than or equal to 2.0 (for M310xA Digitizers). For more information
regarding the supported firmware and software versions, refer to the SD1 3.x Software Startup
Guide.
Software license option for the KS2201A software
Refer to the KS2201A PathWave Test Sync Executive User Guide to know about the licenses that you
must procure for the KS2201A PathWave Test Sync Executive software.
24 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Using the KS2201A PathWave Test Sync Executive Software 2
NOTE
Section 2.2: Comparing ProcessFlow GUI with KS2201A HVI API
Beginning with SD1 3.x software release, the M3601A Hard Virtual
Instrument (HVI) Design Environment (ProcessFlow) is replaced by the
KS2201A PathWave Test Sync Executive Software for HVI integration. Both
the GUI elements and the API functions from the former HVI design
environment are not supported in the SD1 3.x software.
Tabl e 15 summarizes the main operations necessary in an HVI design as performed from the point of
view of the M3601A HVI GUI use model and the KS2201A HVI API use model. You may use this table
of equivalence to transition from ProcessFlow to the KS2201A PathWave Test Sync Executive
software.
Table 15 Differences in operations of ProcessFlow and KS2201A HVI API
Operations ProcessFlow Use Model KS2201A HVI API Use Model
HVI Design Flow First, a “.HVIprj” project file must be created using M3601A GUI
HVI Sequence It is implemented by means of a graphical flowchart. Each HVI
HVI SyncSequence The concept of HVI SyncSequences is not available in the
HVI Resources (Chassis,
Triggers, M9031A modules,
and so on)
Program HVI Sequences You may program HVI sequences by adding flowchart boxes
HVI Compile, Load, Run Once an “.HVI” file is open from a script, you can assign each
to design the required HVI sequences in form of flow-charts. A
binary “.HVI” file is generated from the “.HVIprj” file once the HVI
sequence design is final. The “.HVI” file must be open from code
to integrate the HVI solution into the application code.
Engine in each instrument has a single or main HVI Sequence
associated. All statements, both local and synchronized, are
added to it graphically.
M3601A flowcharts.
Connected chassis are automatically recognized. M9031A
boards are transparent to the M3601A software. PXI trigger
resources that can be allocated to the HVI solution are chosen
from the “Chassis settings” window.
using the M3601A GUI. Configure settings for statements in the
“Properties” window of each flowchart box.
sequence to an HW engine for it to be compiled, loaded to HW,
and executed. Project “.HVIprj” files can be also tested directly
from the M3601A GUI using the “Compile and Run” function.
Application code must import the “keysight_pathwave_hvi”
library to use the HVI API. HVI sequences can be created using
programs directly into the application code without importing
external files.
KtHviSequence class enables you to create a Local HVI
sequence using programs that run “locally” on a specific HVI
engine in a specific instrument. Local Sequences are accessed
using ‘SyncMultiSequenceBlock’ statement placed in a
SyncSequence (KtHviSyncSequence). The HVI top sequence is a
SyncSequence that contains SyncStatements.
KtHviSyncSequence class enables you to add synchronized
operations (Sync Statements) common to all HVI engines within
the HVI instance. The HVI top sequence is a SyncSequence that
contains SyncStatements. Local instructions are added and
executed within Local Sequences that can be accessed by
adding a ‘SyncMultiSequenceBlock’ in a SyncSequence.
HVI resources can be configured using “KtHviPlatform” class and
all the classes inside it.
You may program both HVI SyncSequences and HVI (Local)
Sequences with the API methods add_XXX(), where ‘XXX’ is the
statement name.
API SW methods can
compile the sequence using (hvi.compile()),
load it to hardware using (hvi.load_to_hw()),
run the sequence using (hvi.run()).
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 25
2 Using the KS2201A PathWave Test Sync Executive Software
Section 2.3: Working with KS2201A PathWave Test Sync Executive software
Beginning with Keysight SD1 3.x release, the KS2201A PathWave Test Sync Executive software has
been introduced to enhance the functionalities of one or more PXIe modules both individually and
interactively. PathWave Test Sync Executive is a new API based environment for developing and
running programs with a new generation of Keysight’s Hard Virtual Instrument (HVI) technology. The
KS2201A software enables programmatic development and execution of synchronous real-time
operations across multiple instruments. It enables you to program multiple instruments together so
they can act together with other instruments, like one instrument.
2.3.1: Overview on HVI technology
Keysight’s Hardware Virtual Instrumentation (HVI) technology provides the capability to create
time-deterministic execution sequences with precise synchronization by deploying FPGA hardware
simultaneously among the constituent instruments. This makes the technology a powerful tool in
MIMO systems, such as massive-scale quantum control networks.
A virtual instrument may be considered to function like any other instrument in the system; its main
objective being to digitally sequence events and instructions in the application while synchronizing
multiple modules. This instrument, (referred to in this document as the HVI instrument),
accomplishes this by running one or more “engines” synchronously by referencing a common digital
clock that all instruments (engines) operate on.
The KS2201A PathWave Test Sync Executive software provides you with the capability of designing
HVI sequences using an Application Programming Interface (API) available in both Python and C#
coding languages. The HVI Application Programming Interface (API) is the set of programming
classes and methods that allows the user to create and program an HVI instance. HVI API currently
supports Python v3.7. The HVI core functionality is extended by the PXIe M3xxxA modules using the
SD1 API. The core HVI features and the SD1 API extensions that are specific to M3xxxA, allow a
heterogeneous array of instruments and resources to coexist on a common framework.
All the PXIe M3xxxA modules support HVI technology. When Keysight SD1 is installed on a PXI
system, it installs the drivers required to interact with the M3xxxA series modules. The SD1 API
classes in the Keysight SD1 Library contain HVI add-on interfaces provided as an extension of the
instrument. These add-on interfaces provide access to instrument specific HVI features such as
triggering a digitizer acquisition, outputting a waveform, queuing a waveform, etc.
The primary HVI elements defined for the SD1 API and the corresponding API functions are described
in the following sections.
26 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Using the KS2201A PathWave Test Sync Executive Software 2
Section 2.4: Understanding the HVI elements used in SD1 API
The HVI Core API exposes all HVI functions and defines base interfaces and classes, which are used
to create an HVI, control the hardware execution flow, and operate with data, triggers, events and
actions, but it alone does not include the ability to control operations specific to the M3xxxA product
family. It is the HVI instrument extensions specific to M3xxxA modules that enable instrument
functionalities in an HVI. Such functions are exposed by the module specific add-on HVI definitions.
The SD1 API describes the instrument specific resources and operations that can be executed or
used within HVI sequences.
Figure 9 & Figure 10 display the AWG and Digitizer specific HVI definitions, which are added to the
SD1 library.
Figure 9 M310xA specific HVI definitions
Figure 10 M320xA specific HVI definitions
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 27
2 Using the KS2201A PathWave Test Sync Executive Software
2.4.1: Description of various HVI elements
HVI Engine
An HVI Engine block controls the functions of the instrument and the timing of operations. For HVI to
control an SD1 module, the latter requires an HVI Engine. The HVI Engine is included directly in the
instrument hardware or it can be programmed using the SD1 API into the Field programmable Gate
Array (FPGA) on each module. The HVI Engine executes sequences, which are made up of
Statements.
To define an HVI Engine in SD1 API, see the API syntax in Module HVI Engine.
HVI Actions
An HVI Action is defined for module-specific operations, such as playing waveform in an AWG or
starting an acquisition in Digitizers.
To define an HVI Action in SD1 API, see the API syntax for various HVI actions in SD_AIN functions
and SD_Module functions (specific to Pathwave FPGA).
HVI Events
An HVI Event is defined to occur when specific conditions are met during module-specific
operations, such as when an AWG queue is flushed or when a DAQ is empty.
To define an HVI Event in SD1 API, see the API syntax for various HVI events in SD_AIN functions and
SD_Module functions (specific to Pathwave FPGA).
HVI Trigger
An HVI Trigger is defined to activate the logic signal triggering source and perform various triggering
operations, which are shared between instruments to initiate module-related operations,
communicate states or other information.
To define an HVI Trigger in SD1 API, see the API syntax in Module HVI Triggers.
HVI Instructions
An HVI Instruction is defined to configure various settings related to the module. There are two types
of HVI instructions:
• Product specific (custom) HVI instructions—can change a module’s setting (such as amplitude,
frequency, etc.) or trigger a functionality in the module (such as output a waveform, trigger a data
acquisition, etc.).
• HVI core instructions (general purpose)—provide global, non-module specific or custom
functions, such as register arithmetic, read/write general purpose I/O triggers, execution actions,
etc.
To define an HVI Trigger in SD1 API, see the API syntax in SD_AIN functions.
FPGA sandbox registers
For the modules that contain an FPGA with a user-configurable sandbox, HVI can, potentially (if the
configuration of the module allows it), access (read/write) the registers that you define in that
sandbox. To accomplish this, you must obtain the “.k7z” file for the FPGA sandbox, generated by the
PathWave FPGA application. This file contains all the necessary information to access the registers
by name.
To define FPGA Action/Event in SD1 API, see the API syntax in User FPGA HVI Actions/Events.
28 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
Using the KS2201A PathWave Test Sync Executive Software 2
Section 2.5: Implementing HVI in SD1 API - Sample Programs
The following section shows a sample program where HVI is implemented in SD1 API to create an
HVI sequence, add HVI main engine, define HVI trigger, assign ‘module hvi instruction set’ functions
followed by compiling the HVI sequence and loading it onto the hardware. Based on your
requirements, you may add ‘module hvi actions’ as well as ‘module hvi events’ functions to the HVI
sequence.
The SD1 API functions related to HVI are covered in Chapter 5, “Using Keysight SD1 API Command
Reference”.
Refer to the KS2201A PathWave Test Sync Executive User Guide to know more about the HVI Python
API.
2.5.1: Sample program using Python for HVI instructions
import sys
import matplotlib.pyplot as plt
import keysight_hvi as kthvi
sys.path.append(r'C:\Program Files\Keysight\SD1\Libraries\Python')
import keysightSD1
dig = keysightSD1.SD_AIN()
dig.openWithSlot("M3102A", 1, 9)
sys_def = kthvi.SystemDefinition("mySystem")
sys_def.chassis.add_auto_detect()
sys_def.engines.add(dig.hvi.engines.main_engine, 'SdEngine0')
trigger_resources = [kthvi.TriggerResourceId.PXI_TRIGGER0,
kthvi.TriggerResourceId.PXI_TRIGGER1]
sys_def.sync_resources = trigger_resources
sys_def.non_hvi_core_clocks = [10e6]
sequencer = kthvi.Sequencer("mySequencer", sys_def)
sync_block = sequencer.sync_sequence.add_sync_multi_sequence_block("AWGsequence",10)
sequence = sync_block.sequences['SdEngine0']
test_channel = 1
test_daq_points = 500
test_daq_cycles = 10
dig.channelInputConfig(test_channel, 2, keysightSD1.AIN_Impedance.AIN_IMPEDANCE_50,
keysightSD1.AIN_Coupling.AIN_COUPLING_DC)
SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 29
2 Using the KS2201A PathWave Test Sync Executive Software
instrLabel = "daqConfig"
instruction0 = sequence.add_instruction(instrLabel, 20, dig.hvi.instruction_set.daq_config.id)
instruction0.set_parameter( dig.hvi.instruction_set.daq_config.channel.id, test_channel)
instruction0.set_parameter( dig.hvi.instruction_set.daq_config.cycles.id, test_daq_cycles)
instruction0.set_parameter( dig.hvi.instruction_set.daq_config.daq_points_per_cycle.id,
test_daq_points)
instruction0.set_parameter( dig.hvi.instruction_set.daq_config.trigger_delay.id, 0)
instruction0.set_parameter( dig.hvi.instruction_set.daq_config.trigger_mode.id,
dig.hvi.instruction_set.daq_config.trigger_mode.AUTOTRIG)
# Compile HVI sequences
try:
hvi = sequencer.compile()
except kthvi.CompilationFailed as ex:
compile_status = ex.compile_status
print(compile_status.to_string())
raise ex
print("HVI Compiled")
# Load HVI to HW: load sequences, configure actions/triggers/events, lock resources, etc.
hvi.load_to_hw()
print("HVI Loaded to HW")
# Execute HVI in non-blocking mode
# This mode allows SW execution to interact with HVI execution
hvi.run(hvi.no_wait)
print("HVI Running...")
print("Plotting measured data... Press enter to exit")
print("")
rawReadoutBufferI = dig.DAQread(test_channel, test_daq_points * test_daq_cycles, 200)
# Plot acquisition data
plt.clf()
plt.plot(rawReadoutBufferI, 'r-')
plt.show()
30 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide
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