Keysight M310xA, M330xA User Manual

SD1 3.x Software for
M310xA / M330xA Digitizers

User’s Guide

Notices

CAUTION

WARNING

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M3xxx-90004

Edition

1.2, February 2021

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Contents

1 Understanding PXIe Digitizers Theory of Operation

2 Using the KS2201A PathWave Test Sync Executive Software

Understanding Digitizer’s operation / 11

Channel Numbering and Compatibility Mode / 11
Input settings / 12

Full Scale, Impedance and Coupling 12
Prescaler 13

Analog Trigger / 14
Data Acquisition (DAQs) / 15

Operation 15
DAQ Trigger 17

Working with I/O Triggers / 19

Working with Clock System / 20

Chassis Clock Replacement for High-Precision Applications 20

CLK Output Options / 20
FlexCLK Technology (models w/ variable sampling rate) / 20

Licensing for KS2201A PathWave Test Sync Executive software / 24

Comparing ProcessFlow GUI with KS2201A HVI API / 25

Working with KS2201A PathWave Test Sync Executive software / 26

Overview on HVI technology / 26

Understanding the HVI elements used in SD1 API / 27

Description of various HVI elements / 28

HVI Engine 28
HVI Actions 28
HVI Events 28
HVI Trigger 28
HVI Instructions 28
FPGA sandbox registers 28

Implementing HVI in SD1 API - Sample Programs / 29

Sample program using Python for HVI instructions / 29

3 Using the PathWave FPGA Board Support Package (BSP)

Licensing for PathWave FPGA BSP support / 32

Comparing FPGAFlow with PathWave FPGA / 33

Differences between FPGAFlow and PathWave FPGA / 33
New features in PathWave FPGA / 33

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 3

Working with PathWave FPGA software / 34

Understanding Partial Configuration (PR) / 35

Using BSP with PathWave FPGA software / 37

Understanding BSP composition / 37

Generating a k7z file using PathWave FPGA BSP / 39

Loading k7z file into modules / 48

Using SD1 SFP user interface to load FPGA / 48
Using SD1 API to load FPGA / 49

Implementing BSP using SD1 API - Sample Programs / 50

Sample program using Python for read write on sandbox region / 50
Sample program using .NET for read write on sandbox region / 52

4 Using Keysight SD1 3.x SFP Software

Installing the Keysight SD1 3.x Software Package / 55

Launching the Keysight SD1 SFP software / 56

Understanding the SD1 SFP features & controls / 58

Understanding main window features and controls / 58

File 59
Window 59
Help 59

Understanding features in Hardware Manager / 60

Understanding Digitizer SFP features & controls / 64

Understanding DIG SFP main menu features & controls / 65

File 65
Settings 65
FPGA 66
Help 67

Other DIG SFP features & controls / 67

Time 67
Display 67
Points 67
Trigger 67
Channel 68
Single 68
Run 68
Frequency 68
Window 70
Channel n 70
Display 70

Configuring DAQ and Trigger/Clock Setting dialogs / 70

Setting the Configure DAQ Triggers dialog 70

4 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Setting the DAQ Settings dialog 71
Setting the Trigger / Clock Settings dialog 71

5 Using Keysight SD1 API Command Reference

Keysight Supplied Native Programming Libraries / 74

Support for Other Programming Languages / 75

Functions in SD1 Programming Libraries / 76

Common References to parameter values / 79
Data transfer rates / 83
Latency in Digitizers for various HVI Actions & Instructions / 84

HVI related latency in FPGA User Sandbox 84
TriggerIO and Action Groups 86

SD_Module functions / 88

open / 88
close / 90
moduleCount / 91
getProductName / 92
getSerialNumber / 93
getChassis / 94
getSlot / 95
PXItriggerWrite / 96
PXItriggerRead / 97
getFirmwareVersion / 98
getHardwareVersion / 99
getOptions / 100
getTemperature / 102
getType / 103
isOpen / 104
translateTriggerIOtoExternalTriggerLine / 105
translateTriggerPXItoExternalTriggerLine / 106
runSelfTest / 107

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 5

SD_AIN functions / 108

channelCoupling / 108
channelFullScale / 109
channelImpedance / 110
channelInputConfig / 111
channelMaxFullScale / 112
channelMinFullScale / 113
channelPrescaler / 114
channelPrescalerConfig / 115
channelPrescalerConfigMultiple / 117
channelTriggerConfig / 118
DAQanalogTriggerConfig / 120
DAQconfig / 122
DAQdigitalTriggerConfig / 126
DAQread / 127
DAQstart / 129
DAQstartMultiple / 131
DAQstop / 132
DAQstopMultiple / 133
DAQpause / 134
DAQpauseMultiple / 135
DAQresume / 136
DAQresumeMultiple / 137
DAQflush / 138
DAQflushMultiple / 139
DAQnPoints / 140
DAQtrigger / 141
DAQtriggerMultiple / 142
DAQtriggerConfig / 143
DAQcounterRead / 144
triggerIOconfig / 145
triggerIOwrite / 146
triggerIOread / 148
clockSetFrequency / 149
clockGetFrequency / 151
clockGetSyncFrequency / 153
clockIOconfig / 155
clockResetPhase / 156
DAQbufferPoolConfig / 158
DAQbufferAdd / 159
DAQbufferGet / 160

6 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

DAQbufferPoolRelease / 161
DAQbufferRemove / 162
DAQtriggerExternalConfig / 163
FFT / 164
voltsToInt / 165

SD_Module functions (specific to Pathwave FPGA) / 166

FPGAgetSandBoxRegister / 166
FPGAgetSandBoxRegisters / 167
FPGAload / 168
FPGAreset / 169
FPGATriggerConfig / 170
FPGAconfigureFromK7z / 171
FPGAGetKernelUUID / 172
User FPGA HVI Actions/Events / 173
Module HVI Engine / 174
Module HVI Triggers / 175

SD_SandboxRegister functions / 176

readRegisterBuffer / 176
readRegisterInt32 / 177
writeRegisterBuffer / 178
writeRegisterInt32 / 179
Properties / 180

6 Using SD1 API functions in sample programs

Basic Work Flow for the Digitizer / 182

Implementing SD1 API functions — Sample Programs / 183

Sample program for the overall Digitizer work flow using Python / 183
Sample program for Auto-triggering input waveform using Python / 184
Sample program for DAQ multiple triggering using Python / 188
Sample program for PXI triggering on DAQs using Python / 191

7 Understanding Error Codes in SD1 API

Description of Error & Warning IDs / 196

Description of SD1 Error IDs / 196
Description of SD1 Warning IDs / 198

8 Documentation References

Accessing Online Help for SD1 3.x software / 200

Links to other documents / 201

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 7

Index

8 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

SD1 3.x Software for M310xA / M330xA Digitizers

User’s Guide

1. Understanding PXIe Digitizers Theory of Operation

Understanding Digitizer’s operation 11
Working with I/O Triggers 19
Working with Clock System 20

1 Understanding PXIe Digitizers Theory of Operation

Keysight M31/M33XX digitizers are part of the new M3XXXA family of FPGA-programmable AWGs
and Digitizers. These high-performance digitizers with high channel density have an advanced data
acquisition system (DAQ), includes easy-to-use programming libraries and provides optional
real-time sequencing and decision making capability using the Hard Virtual Instrumentation (HVI)
technology with precise timing and multi-module synchronization. Graphical FPGA programing
allows for FPGA customization without HDL programming expertise and performance penalty. This is
a new family of FPGA-Programmable Digitizers with precise multi-module synchronization and real
time sequencing technology (HVI).

10 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Understanding PXIe Digitizers Theory of Operation 1

Section 1.1: Understanding Digitizer’s operation

The M31/M33XXA Digitizers has a flexible and powerful input structure to acquire signals (Figure 1).

Figure 1 M31/M33XXA Digitizers input functional block diagram

1.1.1: Channel Numbering and Compatibility Mode

Tabl e 1 shows Keysight standards for the output labeling (channel enumeration starts with CH1).

Compatibility mode, which can be changed by open(), is available to support legacy modules and
allows the channel numbering (channel enumeration) to start with either CH0 or CH1.

Modules are opened by default with the enumeration mode of its front panel. However, it is possible
to open them in compatibility mode, forcing enumeration to the selected option. This option might
be needed when different modules coexist.

Table 1 Compatibility mode options

Option Description Name Value

Legacy Channel enumeration starts with CH0 COMPATIBILITY_LEGACY 0

Keysight Channel enumeration starts with CH1 COMPATIBILITY_KEYSIGHT 1

Legacy modules refer to SD1 modules that were manufactured by Signadyne before they were
acquired by KeysightTechnologies. If the hardware equipment configuration being used only
contains modules from KeysightTechnologies, channel enumeration should start with CH1.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 11

1 Understanding PXIe Digitizers Theory of Operation

1.1.2: Input settings

The M31/M33XXA Digitizers provides a block that allows the user to configure all the input settings
such as input impedance, full scale, coupling, prescaler, and so on.

Figure 2 Input settings in the M31/M33XXA Digitizers functional block diagram

Full Scale, Impedance and Coupling

Depending on the product specifications the user can configure the input full scale value, the input
impedance (Tab le 2) and the input coupling (Tab le 3).

Product-dependent Settings: This section describes all the possible input settings, but in reality they
are product-dependent. Check the corresponding Product Data Sheet to see if they are applicable.

Table 2 Input Impedance options

Option Description Name Value

High Impedance Input impedance is high (value is product dependent, check the

corresponding Data Sheet)

50Ω Input impedance is 50Ω AIN_IMPEDANCE_50 1

Table 3 Input Coupling options

Option Description Name Value

DC DC coupling AIN_COUPLING_DC 0

AC AC coupling AIN_COUPLING_AC 1

AIN_IMPEDANCE_HZ 0

12 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Understanding PXIe Digitizers Theory of Operation 1

NOTE

The full scale parameter adjusts automatically the input gain to maximize the input dynamic range.

Tabl e 4 shows the accepted range of voltage values for full scale, as a function of impedance.

Table 4 Full Scale Voltage range as a function of Impedance

Impedance Option Voltage range for DIG500 Voltage range for DIG100

HiZ 0.1V to 8V 0.1V to 10V

50Ω 0.0625V to 4V 0.2V to 3V

Prescaler

The prescaler is used to reduce the effective input sampling rate, capturing 1 out of n samples and
discarding the rest. The resulting sampling rate is as follows:

Figure 3 Resulting sampling rate when prescaler is applied

where, f

fs = f

is final effective sampling frequency

s

f

CLKsys

/ (5 * prescaler)

CLKsys

is the Clock System

prescaler is an integer value (4 bits)

Prescaler vs. Downsampling/Decimation:The prescaler cannot be
considered as a full decimation or down-sampling block as it does not
contain any filters and therefore, it generates aliasing. For applications
where full downsampling is required, you must choose an IF Keysight
Digitizer or Transceiver, which provides DDC (Digital Down Conversion).

Table 5 Programming functions related to the input prescaler

Function Name Description API function

channelPrescalerConfig Configures the input prescaler channelPrescalerConfig()

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 13

1 Understanding PXIe Digitizers Theory of Operation

1.1.3: Analog Trigger

The analog trigger block processes the input data and generates a digital trigger that can be used by
any Data Acquisition Block (“Data Acquisition (DAQs)” on page 15).

Figure 4 Analog trigger processor in the M31/M33XXA Digitizers functional block diagram

You can select the threshold and the trigger mode. The available trigger modes are shown in Table 6 .

Table 6 Analog Trigger Mode options

Option Description Name Value

Positive Edge Trigger is generated when the input signal is rising and crosses the

threshold

Negative Edge Trigger is generated when the input signal is falling and crosses the

threshold

Both Edges Trigger is generated when the input signal crosses the threshold, no

matter if it is rising or falling

Table 7 Programming functions related to analog triggers

Function Name Description API function

channelTriggerConfig Configures the analog trigger for each channel channelTriggerConfig()

AIN_RISING_EDGE 1

AIN_FALLING_EDGE 2

AIN_BOTH_EDGES 3

14 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

1.1.4: Data Acquisition (DAQs)

The Data Acquisition (DAQ) is a powerful and flexible block which acquires incoming words and
sends them to the user PC using dedicated DMA channels (Figure 5).

Understanding PXIe Digitizers Theory of Operation 1

Figure 5 DAQ units in the M31/M33XXA Digitizers functional block diagram

Operation

The words acquisition requires two easy steps:
1 Configuration: A call to the function “DAQconfig()” allows the user to configure, among others,

the trigger method (Table 8 ), the number of DAQ cycles to perform (number of triggers), the
number of acquired words per cycle (DAQpointsPerCycle), and the number of words that must be
acquired before interrupting the PC (DAQpoints). Figure 6 illustrates the flexibility of the DAQ
block operation.

2 Data read:

a Using “DAQread()”: a blocking/non-blocking function that returns the array of acquired words

(DAQdata).

b Using a callback function: a user function that is automatically called when the configured

amount of data (set with DAQpoints) is available.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 15

1 Understanding PXIe Digitizers Theory of Operation

Figure 6 M31/M33XXA Digitizers words acquisition operation

Pausing and Resuming the DAQ: The function “DAQpause()” pauses the DAQ operation (triggers are
discarded). The acquisition can be resumed calling “DAQresume()”. A “DAQstop()” is performed
automatically when the DAQ block reaches the specified number of acquisition cycles.

Figure 7 Examples of the DAQ operation

Onboard memory and DAQpoints selection: The acquired words are first stored in a DAQ buffer
located in the module onboard RAM and then sent to the PC RAM via the ultra-fast PXI Express bus
(Figure 6) using dedicated DMA channels. This DAQ buffer, and therefore the minimum amount of
onboard RAM needed for an application, is directly the size of the data array, which you want to

16 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Understanding PXIe Digitizers Theory of Operation 1

NOTE

receive in each “DAQread()” or callback function call. This data array, called (DAQdata), contains
(DAQpoints) words. Therefore, its size is calculated as DAQpoints x 2 bytes/word (in the case of the
M31/M33XXA Digitizers). The size of this DAQ buffer must be chosen according to two criteria:

• High speed transients: the DAQ onboard buffer can store bursts of words at higher rates than the

PXIe and the computer can handle. Larger buffers allow handling longer high speed bursts.

• PC load: The DAQ buffer must be chosen to allow the PC enough time to process each DAQ buffer

(DAQdata) and to handle interrupts and process-context switching tasks. For example, if a
computer requires 500 ms to process DAQdata, the buffer size must be such that it can store more
than 500 ms of input words without interrupting the computer. The DAQ block facilitates the task
of adjusting the PC processing rate with the introduction of the DAQ cycles (Figure 6).

The amount of required PC RAM is double the amount of required onboard
RAM.

Prescaler: The DAQ block has an input prescaler which can be configured to discard words, reducing
the effective acquisition data rate “DAQconfig()”.

DAQ counter: The DAQ block has a dedicated counter to store the number of acquired words since the
last call to “DAQconfig()” or “DAQflush()”. This counter can be read with “DAQcounterRead()”.

DAQ Trigger

As previously explained, you can configure the trigger for the acquisition. The available trigger modes
for the DAQ are shown in Tab le 8 . Note that not all trigger methods are available in all modules.

Table 8 DAQ Trigger Mode options

Option Description Name Value

Auto (Immediate) The acquisition starts automatically after a call to function DAQstart AUTOTRIG 0

Software / HVI Software trigger. The acquisition is triggered by the function DAQtrigger,

Hardware Digital
Tri gger

Hardware Analog
Tri gger

DAQtrigger provided that the DAQ is running. DAQtrigger can be
executed from the user application (VI) or from an HVI.

Hardware trigger. The DAQ waits for an external digital trigger (see

Table 9 External Hardware Digital Trigger Source for the DAQ).

Hardware trigger. The DAQ waits for an external analog trigger (only
products with analog inputs).

As shown in Tab le 8, you have the following options for hardware triggers:

• Hardware Digital Trigger: If the DAQ is set to use a digital hardware trigger, you must configure it

using the function “DAQdigitalTriggerConfig()”. The available digital hardware trigger options are
shown in Tab le 9 and Table 1 0. If external I/O trigger is selected in “DAQdigitalTriggerConfig()”,
you must configure additional settings of this particular I/O line, such as input/output direction,
sampling/synchronization options, etc. (“Working with I/O Triggers” on page 19).

• Hardware Analog Trigger: (Only products with analog inputs) If the DAQ is set to use an analog

hardware trigger, you must configure it using the function “DAQanalogTriggerConfig()”. The
Analog Trigger Block of the corresponding analog input channel must also be configured.

SWHVITRIG 1

HWDIGTRIG 2

HWANATRIG 3

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 17

1 Understanding PXIe Digitizers Theory of Operation

Table 9 External Hardware Digital Trigger Source for the DAQ

Option Description Name Value

External I/O
Tri gger

PXI Trigger PXI form factor only. The DAQ trigger is a PXI trigger line and it is

Table 10 Trigger behavior for the DAQ

Option Description Name Value

None No trigger has been activated TRIGGER_NONE 0

Active High Trigger is active when it is at level high TRIGGER_HIGH 1

Active Low Trigger is active when it is at level Low TRIGGER_LOW 2

Rising Edge Trigger is active on the rising edge TRIGGER_RISE 3

Falling Edge Trigger is active on the falling edge TRIGGER_FALL 4

The DAQ trigger is a TRG connector/line of the product (I/O Triggers).
PXI form factor only: this trigger can be synchronized to CLK10.

synchronized to CLK10.

TRIG_EXTERNAL 0

TRIG_PXI 1

18 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Understanding PXIe Digitizers Theory of Operation 1

Section 1.2: Working with I/O Triggers

The M3100A/M3102A PXIe Digitizers have general purpose input/output triggers (TRG
connectors/lines). A trigger can be used as a general purpose digital IO or as a trigger input, and can
be sampled using the options shown below in Trigger Synchronization/Sampling Options.

Table 11 I/O Trigger types and corresponding functions

Typ e Description Name Value

Trigger Output (readable) TRG operates as a general purpose digital output signal, that can be written

by the user software.

Trigger Input TRG operates as a trigger input, or as general purpose digital input signal,

that can be read by the user software.

Table 12 Trigger Synchronization options

Typ e Description Name Value

Non-synchronized mode The trigger is sampled with an internal 100 MHz clock. SYNC_NONE 0

Synchronized mode (PXI form factor only) The trigger is sampled using CLK10. SYNC_CLK10 1

AIN_TRG_OUT 0

AIN_TRG_IN 1

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 19

1 Understanding PXIe Digitizers Theory of Operation

Section 1.3: Working with Clock System

The M3100A/M3102A PXIe Digitizer uses an internally generated high-quality clock (CLKref) which is
phase-locked to the chassis clock. Therefore, this clock is an extremely jitter-cleaned copy of the
chassis clock. This implementation achieves a jitter and phase noise above 100 Hz which is
independent of the chassis clock, depending on it only for the absolute frequency precision and long
term stability. A copy of CLKref is available at the CLK connector.

CLKref is used as a reference to generate CLKsys, the high-frequency clock used to sample data.

Chassis Clock Replacement for High-Precision Applications

For applications where clock stability and precision is crucial (for example: GPS, experimental
physics, etc.), you can replace the chassis clock with an external reference.

In the case of PXI/PXIe, this is possible via a chassis clock input connector or with a PXI/PXIe timing
module. These options are not available in all chassis; see the corresponding chassis specifications.

1.3.1: CLK Output Options

Table 13 Clock Output options

Options Description Name Value

Disable The CLK connector is disabled. N/A 0 (default)

CLKref Output A copy of the reference clock is available at the CLK connector. N/A 1

1.3.2: FlexCLK Technology (models w/ variable sampling rate)

The sampling frequency of the M3100A/M3102A PXIe Digitizers (CLKsys frequency) can be changed
using the advanced clocking system.

Figure 8 Block Diagram depicting the Advanced Flex Clock System in PXIe DIGs

FlexCLK System, where:

• CLKref is the internal reference clock, and is phase-locked to the chassis clock.

• CLKsys is the system clock used to sample data.

20 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Understanding PXIe Digitizers Theory of Operation 1

• CLKsync is an internal clock used for the synchronization features of the M3100A/M3102A PXIe

Digitizers.

• PXI CLK10 is the 10 MHz clock of the PXI/PXIe backplane.

The CLKsys frequency can be changed within the range indicated in the Data Sheet of the
corresponding product [clockSetFrequency()]. The CLKsync frequency changes with the CLKsys
frequency as per the following equation:

f

= GreatestCommonDivisor (f

CLKsync

PXI_CLK10

, f

CLKsys

/ 5)

The CLKsync frequency is returned by clockSetFrequency().

Table 14 CLKsync frequency mode options

Options Description Name Value

Low Jitter Mode The clock system is set to achieve the lowest jitter, sacrificing tuning speed. CLK_LOW_JITTER 0

Fast Tuning Mode The clock system is set to achieve the lowest tuning time, sacrificing jitter

performance.

CLK_FAST_TUNE 1

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 21

1 Understanding PXIe Digitizers Theory of Operation

22 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

SD1 3.x Software for M310xA / M330xA Digitizers

User’s Guide

2. Using the KS2201A PathWave Test Sync Executive Software

Licensing for KS2201A PathWave Test Sync Executive software 24
Comparing ProcessFlow GUI with KS2201A HVI API 25
Working with KS2201A PathWave Test Sync Executive software 26
Understanding the HVI elements used in SD1 API 27
Implementing HVI in SD1 API - Sample Programs 29

This chapter provides an introduction to the KS2201A PathWave Test Sync Executive Software and
describes its implementation in the SD1 3.x API. For detailed information about the KS2201A
PathWave Test Sync Executive Software and its API, refer to the KS2201A PathWave Test Sync
Executive Software User Guide.

2 Using the KS2201A PathWave Test Sync Executive Software

Section 2.1: Licensing for KS2201A PathWave Test Sync Executive software

Hardware license option (-HV1) on the M3xxxA modules

All M3xxxA modules support HVI technology. However, the hardware license option -HV1 must be
available on each module that is required to be programmed using the KS2201A PathWave Test
Sync Executive software and for usability with SD1 3.x software. The newer M3xxxA cards are
shipped with the newest versions of firmware and SD1 software, which support the PathWave Test
Sync Executive software. During procurement, you may choose to procure the -HV1 hardware
option.

To use an older module with the KS2201A PathWave Test Sync Executive software, the firmware and
SD1 software must be upgraded. KS2201A PathWave Test Sync Executive software requires that
Keysight SD1 SFP software version 3.x be installed on the same machine. Also, the PXIe M3xxxA
modules products must have Firmware versions greater than or equal to 4.0 (for M320xA AWGs /
M330xA Combos) and greater than or equal to 2.0 (for M310xA Digitizers). For more information
regarding the supported firmware and software versions, refer to the SD1 3.x Software Startup
Guide.

Software license option for the KS2201A software

Refer to the KS2201A PathWave Test Sync Executive User Guide to know about the licenses that you
must procure for the KS2201A PathWave Test Sync Executive software.

24 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the KS2201A PathWave Test Sync Executive Software 2

NOTE

Section 2.2: Comparing ProcessFlow GUI with KS2201A HVI API

Beginning with SD1 3.x software release, the M3601A Hard Virtual
Instrument (HVI) Design Environment (ProcessFlow) is replaced by the
KS2201A PathWave Test Sync Executive Software for HVI integration. Both
the GUI elements and the API functions from the former HVI design
environment are not supported in the SD1 3.x software.

Tabl e 15 summarizes the main operations necessary in an HVI design as performed from the point of

view of the M3601A HVI GUI use model and the KS2201A HVI API use model. You may use this table
of equivalence to transition from ProcessFlow to the KS2201A PathWave Test Sync Executive
software.

Table 15 Differences in operations of ProcessFlow and KS2201A HVI API

Operations ProcessFlow Use Model KS2201A HVI API Use Model

HVI Design Flow First, a “.HVIprj” project file must be created using M3601A GUI

HVI Sequence It is implemented by means of a graphical flowchart. Each HVI

HVI SyncSequence The concept of HVI SyncSequences is not available in the

HVI Resources (Chassis,
Triggers, M9031A modules,
and so on)

Program HVI Sequences You may program HVI sequences by adding flowchart boxes

HVI Compile, Load, Run Once an “.HVI” file is open from a script, you can assign each

to design the required HVI sequences in form of flow-charts. A
binary “.HVI” file is generated from the “.HVIprj” file once the HVI
sequence design is final. The “.HVI” file must be open from code
to integrate the HVI solution into the application code.

Engine in each instrument has a single or main HVI Sequence
associated. All statements, both local and synchronized, are
added to it graphically.

M3601A flowcharts.

Connected chassis are automatically recognized. M9031A
boards are transparent to the M3601A software. PXI trigger
resources that can be allocated to the HVI solution are chosen
from the “Chassis settings” window.

using the M3601A GUI. Configure settings for statements in the
“Properties” window of each flowchart box.

sequence to an HW engine for it to be compiled, loaded to HW,
and executed. Project “.HVIprj” files can be also tested directly
from the M3601A GUI using the “Compile and Run” function.

Application code must import the “keysight_pathwave_hvi”
library to use the HVI API. HVI sequences can be created using
programs directly into the application code without importing
external files.

KtHviSequence class enables you to create a Local HVI
sequence using programs that run “locally” on a specific HVI
engine in a specific instrument. Local Sequences are accessed
using ‘SyncMultiSequenceBlock’ statement placed in a
SyncSequence (KtHviSyncSequence). The HVI top sequence is a
SyncSequence that contains SyncStatements.

KtHviSyncSequence class enables you to add synchronized
operations (Sync Statements) common to all HVI engines within
the HVI instance. The HVI top sequence is a SyncSequence that
contains SyncStatements. Local instructions are added and
executed within Local Sequences that can be accessed by
adding a ‘SyncMultiSequenceBlock’ in a SyncSequence.

HVI resources can be configured using “KtHviPlatform” class and
all the classes inside it.

You may program both HVI SyncSequences and HVI (Local)
Sequences with the API methods add_XXX(), where ‘XXX’ is the
statement name.

API SW methods can
compile the sequence using (hvi.compile()),
load it to hardware using (hvi.load_to_hw()),
run the sequence using (hvi.run()).

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 25

2 Using the KS2201A PathWave Test Sync Executive Software

Section 2.3: Working with KS2201A PathWave Test Sync Executive software

Beginning with Keysight SD1 3.x release, the KS2201A PathWave Test Sync Executive software has
been introduced to enhance the functionalities of one or more PXIe modules both individually and
interactively. PathWave Test Sync Executive is a new API based environment for developing and
running programs with a new generation of Keysight’s Hard Virtual Instrument (HVI) technology. The
KS2201A software enables programmatic development and execution of synchronous real-time
operations across multiple instruments. It enables you to program multiple instruments together so
they can act together with other instruments, like one instrument.

2.3.1: Overview on HVI technology

Keysight’s Hardware Virtual Instrumentation (HVI) technology provides the capability to create
time-deterministic execution sequences with precise synchronization by deploying FPGA hardware
simultaneously among the constituent instruments. This makes the technology a powerful tool in
MIMO systems, such as massive-scale quantum control networks.

A virtual instrument may be considered to function like any other instrument in the system; its main
objective being to digitally sequence events and instructions in the application while synchronizing
multiple modules. This instrument, (referred to in this document as the HVI instrument),
accomplishes this by running one or more “engines” synchronously by referencing a common digital
clock that all instruments (engines) operate on.

The KS2201A PathWave Test Sync Executive software provides you with the capability of designing
HVI sequences using an Application Programming Interface (API) available in both Python and C#
coding languages. The HVI Application Programming Interface (API) is the set of programming
classes and methods that allows the user to create and program an HVI instance. HVI API currently
supports Python v3.7. The HVI core functionality is extended by the PXIe M3xxxA modules using the
SD1 API. The core HVI features and the SD1 API extensions that are specific to M3xxxA, allow a
heterogeneous array of instruments and resources to coexist on a common framework.

All the PXIe M3xxxA modules support HVI technology. When Keysight SD1 is installed on a PXI
system, it installs the drivers required to interact with the M3xxxA series modules. The SD1 API
classes in the Keysight SD1 Library contain HVI add-on interfaces provided as an extension of the
instrument. These add-on interfaces provide access to instrument specific HVI features such as
triggering a digitizer acquisition, outputting a waveform, queuing a waveform, etc.

The primary HVI elements defined for the SD1 API and the corresponding API functions are described
in the following sections.

26 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the KS2201A PathWave Test Sync Executive Software 2

Section 2.4: Understanding the HVI elements used in SD1 API

The HVI Core API exposes all HVI functions and defines base interfaces and classes, which are used
to create an HVI, control the hardware execution flow, and operate with data, triggers, events and
actions, but it alone does not include the ability to control operations specific to the M3xxxA product
family. It is the HVI instrument extensions specific to M3xxxA modules that enable instrument
functionalities in an HVI. Such functions are exposed by the module specific add-on HVI definitions.
The SD1 API describes the instrument specific resources and operations that can be executed or
used within HVI sequences.

Figure 9 & Figure 10 display the AWG and Digitizer specific HVI definitions, which are added to the

SD1 library.

Figure 9 M310xA specific HVI definitions

Figure 10 M320xA specific HVI definitions

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 27

2 Using the KS2201A PathWave Test Sync Executive Software

2.4.1: Description of various HVI elements

HVI Engine

An HVI Engine block controls the functions of the instrument and the timing of operations. For HVI to
control an SD1 module, the latter requires an HVI Engine. The HVI Engine is included directly in the
instrument hardware or it can be programmed using the SD1 API into the Field programmable Gate
Array (FPGA) on each module. The HVI Engine executes sequences, which are made up of
Statements.

To define an HVI Engine in SD1 API, see the API syntax in Module HVI Engine.

HVI Actions

An HVI Action is defined for module-specific operations, such as playing waveform in an AWG or
starting an acquisition in Digitizers.

To define an HVI Action in SD1 API, see the API syntax for various HVI actions in SD_AIN functions
and SD_Module functions (specific to Pathwave FPGA).

HVI Events

An HVI Event is defined to occur when specific conditions are met during module-specific
operations, such as when an AWG queue is flushed or when a DAQ is empty.

To define an HVI Event in SD1 API, see the API syntax for various HVI events in SD_AIN functions and

SD_Module functions (specific to Pathwave FPGA).

HVI Trigger

An HVI Trigger is defined to activate the logic signal triggering source and perform various triggering
operations, which are shared between instruments to initiate module-related operations,
communicate states or other information.

To define an HVI Trigger in SD1 API, see the API syntax in Module HVI Triggers.

HVI Instructions

An HVI Instruction is defined to configure various settings related to the module. There are two types
of HVI instructions:

• Product specific (custom) HVI instructions—can change a module’s setting (such as amplitude,

frequency, etc.) or trigger a functionality in the module (such as output a waveform, trigger a data
acquisition, etc.).

• HVI core instructions (general purpose)—provide global, non-module specific or custom

functions, such as register arithmetic, read/write general purpose I/O triggers, execution actions,
etc.

To define an HVI Trigger in SD1 API, see the API syntax in SD_AIN functions.

FPGA sandbox registers

For the modules that contain an FPGA with a user-configurable sandbox, HVI can, potentially (if the
configuration of the module allows it), access (read/write) the registers that you define in that
sandbox. To accomplish this, you must obtain the “.k7z” file for the FPGA sandbox, generated by the
PathWave FPGA application. This file contains all the necessary information to access the registers
by name.

To define FPGA Action/Event in SD1 API, see the API syntax in User FPGA HVI Actions/Events.

28 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the KS2201A PathWave Test Sync Executive Software 2

Section 2.5: Implementing HVI in SD1 API - Sample Programs

The following section shows a sample program where HVI is implemented in SD1 API to create an
HVI sequence, add HVI main engine, define HVI trigger, assign ‘module hvi instruction set’ functions
followed by compiling the HVI sequence and loading it onto the hardware. Based on your
requirements, you may add ‘module hvi actions’ as well as ‘module hvi events’ functions to the HVI
sequence.

The SD1 API functions related to HVI are covered in Chapter 5, “Using Keysight SD1 API Command
Reference”.

Refer to the KS2201A PathWave Test Sync Executive User Guide to know more about the HVI Python
API.

2.5.1: Sample program using Python for HVI instructions

import sys

import matplotlib.pyplot as plt

import keysight_hvi as kthvi

sys.path.append(r'C:\Program Files\Keysight\SD1\Libraries\Python')

import keysightSD1

dig = keysightSD1.SD_AIN()

dig.openWithSlot("M3102A", 1, 9)

sys_def = kthvi.SystemDefinition("mySystem")

sys_def.chassis.add_auto_detect()

sys_def.engines.add(dig.hvi.engines.main_engine, 'SdEngine0')

trigger_resources = [kthvi.TriggerResourceId.PXI_TRIGGER0,
kthvi.TriggerResourceId.PXI_TRIGGER1]

sys_def.sync_resources = trigger_resources

sys_def.non_hvi_core_clocks = [10e6]

sequencer = kthvi.Sequencer("mySequencer", sys_def)

sync_block = sequencer.sync_sequence.add_sync_multi_sequence_block("AWGsequence",10)

sequence = sync_block.sequences['SdEngine0']

test_channel = 1

test_daq_points = 500

test_daq_cycles = 10

dig.channelInputConfig(test_channel, 2, keysightSD1.AIN_Impedance.AIN_IMPEDANCE_50,
keysightSD1.AIN_Coupling.AIN_COUPLING_DC)

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 29

2 Using the KS2201A PathWave Test Sync Executive Software

instrLabel = "daqConfig"

instruction0 = sequence.add_instruction(instrLabel, 20, dig.hvi.instruction_set.daq_config.id)

instruction0.set_parameter( dig.hvi.instruction_set.daq_config.channel.id, test_channel)

instruction0.set_parameter( dig.hvi.instruction_set.daq_config.cycles.id, test_daq_cycles)

instruction0.set_parameter( dig.hvi.instruction_set.daq_config.daq_points_per_cycle.id,
test_daq_points)

instruction0.set_parameter( dig.hvi.instruction_set.daq_config.trigger_delay.id, 0)

instruction0.set_parameter( dig.hvi.instruction_set.daq_config.trigger_mode.id,
dig.hvi.instruction_set.daq_config.trigger_mode.AUTOTRIG)

# Compile HVI sequences

try:

hvi = sequencer.compile()

except kthvi.CompilationFailed as ex:

compile_status = ex.compile_status

print(compile_status.to_string())

raise ex

print("HVI Compiled")

# Load HVI to HW: load sequences, configure actions/triggers/events, lock resources, etc.

hvi.load_to_hw()

print("HVI Loaded to HW")

# Execute HVI in non-blocking mode

# This mode allows SW execution to interact with HVI execution

hvi.run(hvi.no_wait)

print("HVI Running...")

print("Plotting measured data... Press enter to exit")

print("")

rawReadoutBufferI = dig.DAQread(test_channel, test_daq_points * test_daq_cycles, 200)

# Plot acquisition data

plt.clf()

plt.plot(rawReadoutBufferI, 'r-')

plt.show()

30 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

SD1 3.x Software for M310xA / M330xA Digitizers

User’s Guide

3. Using the PathWave FPGA Board Support Package (BSP)

Licensing for PathWave FPGA BSP support 32
Comparing FPGAFlow with PathWave FPGA 33
Working with PathWave FPGA software 34
Using BSP with PathWave FPGA software 37
Generating a k7z file using PathWave FPGA BSP 39
Loading k7z file into modules 48
Implementing BSP using SD1 API - Sample Programs 50

This chapter provides an introduction to the PathWave FPGA Board Support Package (BSP) and
describes its implementation in the SD1 3.x API. For detailed information about using the PathWave

FPGA 2020 Update 1.0 software along with BSP for supported modules, refer to the PathWave FPGA
Customer Documentation and the BSP guides for the respective modules.

3 Using the PathWave FPGA Board Support Package (BSP)

Section 3.1: Licensing for PathWave FPGA BSP support

All instruments that can be programmed with PathWave FPGA BSP will enable programming using
the licensing option -FP1. You are required to procure an -FP1 license option for each instrument
that must be programmed. For example, if you are purchasing ten M3102A DIG cards, each M3102A
requires an individual -FP1 license option enabled.

New Hardware - Latest Software

The new modules for M3201A AWG 1G, M3202A AWG 500 and M3102A DIG500, where you have the

-FP1 license option enabled are supported only with SD1 software version 3.x (or later) installed on
your machine. If you have SD1 version 2.x.x installed on your machine, you must upgrade the
software for hardware compatibility. For more information regarding the supported firmware and
software versions, refer to the SD1 3.x Software Startup Guide.

Latest Software - New Hardware

Keysight SD1 SFP software version 3.x or later recognize only those PXIe M3xxxA products that have
Firmware versions greater than or equal to 4.0 (for M320xA AWGs / M330xA Combos) and greater
than or equal to 2.0 (for M310xA Digitizers). You may either update the firmware on your modules or
contact Keysight Sales to upgrade your hardware. After upgrading your hardware, you must have the

-FP1 license option enabled to make it compatible with the latest version of SD1 software.

The M3201A / M3202A may be purchased as a 4 channel configuration, each of which may include
an option to specify a variable sampling clock.

The M3102A / M3100A may be purchased as a 4 channel configuration, which have fixed sampling
clock.

These modules may also be purchased to include one of two possible Xilinx FPGAs:
1 xc7k410tffg676-2
2 xc7k325tffg676-2

The xc7k410tffg676-2 part offers a substantial increase in the amount of FPGA resources available to
the user for custom logic. The following table outline the FPGA resources, which are available for
custom logic for each part.

Table 16 Available FPGA Resources for custom logic on each module

xc7k325tffg676-2 xc7k410tffg676-2

Resource Type 4 Channel 4 Channel

Slice LUTs 82800 102000

Slice Registers 165600 204000

DSP Blocks 360 660

Block Ram (RAMB18) 360 660

32 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

NOTE

Section 3.2: Comparing FPGAFlow with PathWave FPGA

Beginning with SD1 3.x software release, the M3602A Graphical FPGA
Development Environment (FPGAFlow) is replaced by the KF9000A
PathWave FPGA software for FPGA programming. The files generated by
FPGAFlow are not supported in the SD1 3.x software.

The following sections describe the differences between FPGAFlow and PathWave FPGA software
along with the new features introduced in the latter software.

3.2.1: Differences between FPGAFlow and PathWave FPGA

While most of the features are same, but there are subtle differences in the appearances and certain
aspects of both the FPGA programming environments. Tab le 1 7 highlights such differences.

Table 17 Differences between FPGAFlow and PathWave FPGA

l

FPGAFlow PathWave FPGA

Support limited to Legacy Signadyne boards Support for larger number of Keysight developed boards

Uses one or more BitGen servers to generate the output bitstream Uses Xilinx Vivado Design Suite locally on Host Machine to generate the output bitstream

Generates “sbp” file, which is loaded on the legacy module’s FPGA Generates “k7z” file, which is loaded on the FPGA of the new modules

3.2.2: New features in PathWave FPGA

Apart from the differences listed above, the PathWave FPGA software has certain new elements:

• IPs can be defined using IP-XACT file. This gives you information about the IP name, version,

interfaces, category, and so on.

• A repository of IPs that are using IP-XACT can be loaded concurrently.

• Block designs are now called sub-modules.

• Multiple boards are supported using the BSP technology.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 33

3 Using the PathWave FPGA Board Support Package (BSP)

NOTE

Section 3.3: Working with PathWave FPGA software

Beginning with Keysight SD1 3.x release, the KF9000A PathWave FPGA Programming Environment
(commonly known as PathWave FPGA), powered by Xilinx Vivado Design Suite, has been introduced
for FPGA designing on supported Keysight modules.

Some applications require the use of custom on-board real-time processing, which might not be
covered by the comprehensive off-the-shelf functionalities of standard hardware products. For these
applications, Keysight supplies Option -FP1 (Enabled FPGA Programming) that provide the capability
to program the on-board FPGA. With PathWave FPGA, development time is dramatically reduced
and you can focus exclusively on expanding the functionality of the standard instrument, instead of
developing a complete new one.

PathWave FPGA is a graphical environment that provides a complete FPGA design flow for rapid
FPGA development from design creation to simulation to Gateware deployment to
Hardware/Gateware verification on Keysight hardware with Open FPGA. This environment provides a
design flow from schematic to bitstream file generation with the click of a button.

The PathWave FPGA 2020 is a licensed software. Contact Keysight Support
for more information on procuring the respective licenses.

Once you have installed the PathWave FPGA 2020 software, you can launch its user interface from
the Start menu. Alternatively, you may use the corresponding command line or scripts to launch the
application.

Figure 11 Default window for PathWave FPGA 2020 Update 1.0 software

34 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

In Keysight PathWave, FPGA code is represented as boxes (called blocks) with IO ports. An empty
project contains the “Default Product Blocks”, and the “Design IO Blocks” that provide the outer
interface of the design. You can add/remove blocks from the Keysight Block Library, External Blocks,
or Xilinx IP cores.

To know about the required prerequisite software, system requirements and licensing information for
the PathWave FPGA 2020 Update 1.0 software, refer to the “Getting Started” section of the

PathWave FPGA Customer Documentation. To view the installation procedure, refer to the “Installing
PathWave FPGA 2020 Update 1.0 software” section and to view how to launch the software, refer to

the “Launching the PathWave FPGA BSP” section in the SD1 3.x Software Startup Guide.

3.3.1: Understanding Partial Configuration (PR)

The FPGA configurable region utilizes Xilinx FPGA partial reconfiguration technology to allow you to
design and configure a defined section of the supported M3xxxA FPGA without the need to power
down or reboot the M3xxxA module or host computer, respectively.

PathWave FPGA supports the design flow in the Partial Reconfiguration (PR) technology. In a PR
flow, a full FPGA reconfiguration is only necessary once for a given static region version. The
sandboxes can be reconfigured anytime, without a full reconfiguration, and without stopping the
current operation of the FPGA.

Partial Reconfiguration enables performing dynamic change of modules within an active design. By
implementing multiple configurations in this flow, you can achieve full bitstream for each
configuration and partial bitstream for each reconfigurable module.

While FPGA technology facilitates direct programming and re-programming of modules without
going through re-fabrication with a modified design; the partial reconfiguration technique allows the
modification of an operating FPGA design by loading a partial configuration file. The logic in the
FPGA design is divided into two different types, reconfigurable logic and static logic. The static logic
remains functional and is unaffected by the loading of a partial bitstream file, whereas the
reconfigurable logic is replaced by the contents of that bitstream file.

Figure 12 Block diagram depicting partial reconfiguration using bitstream files

Partial Reconfiguration (PR) is modifying a subset of logic in an operating FPGA design by
downloading a partial bitstream. In some cases, a complete FPGA reconfiguration might be
preferable (better routing, timing closure, and so on). This is also supported by PathWave FPGA, as
long as a reboot is not required after the reconfiguration process.

The PathWave FPGA software does not, by itself, provide access to the waveform and digitizer
controls for the supported Keysight M3xxxA PXIe modules. You must install the module-specific
Board Support Package (BSP) to leverage the features within the PathWave FPGA software for FPGA
designing and for loading your customized code onto the Keysight instrument.

The design part in Keysight FPGA consists of two regions: the static region and the sandbox region.
The static region for each supported module is defined within BSP and cannot be modified. This
region defines the implementation of the FPGA interfaces to external resources, and defines the

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 35

3 Using the PathWave FPGA Board Support Package (BSP)

interfaces to the sandbox. A static region implementation can define one or more sandbox regions in
an FPGA design. The sandbox region contains the user specific FPGA design. The interface of the
sandbox depends on the static region implementation.

Figure 13 Block diagram representing layout of Static and Sandbox regions

36 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

Section 3.4: Using BSP with PathWave FPGA software

3.4.1: Understanding BSP composition

In embedded systems, the board support package (BSP) is the layer of software containing
hardware-specific drivers and other routines that allow a particular operating system (traditionally a
real-time operating system, or RTOS) to function in a particular hardware environment (a computer
or CPU card), integrated with the RTOS itself. Third-party hardware developers, who wish to support
a particular RTOS must create a BSP that allows that RTOS to run on their platform. In most cases
the RTOS image and license, the BSP containing it, and the hardware are bundled together by the
hardware vendor. BSPs are typically customizable, allowing you to specify the drivers and routines,
which should be included in the software build based on their selection of hardware and software
options. (source: Wikipedia)

The Board Support Package (BSP), installed separately from PathWave FPGA, comprises of two
parts—an FPGA Support Package (FSP) and a Runtime Support Package (RSP). A BSP configuration
file contains all the necessary information to identify the configuration, which includes static region
implementation, an RSP implementation, build scripts, examples, project templates, and
documentation.

• The FSP is that portion of the BSP that allows you to build a bitstream file for the target FPGA. It is

consumed by PathWave FPGA to support design creation and sandbox compilation; everything
that is performed without the physical hardware. The FPGA Support Package allows you, as a
PathWave FPGA user, to create a design targeting your instrument. It includes descriptions of the
sandbox interfaces, template PathWave FPGA projects, and files required for compiling a sandbox
image from HDL sources. An FSP fulfills the ‘design-time requirements’ of PathWave FPGA, which
covers everything prior to loading a bit image onto the instrument.

• The RSP is that portion of the BSP that allows you to control your target FPGA. It provides a ‘C’

API that you can use to load design images onto hardware, verify your FPGA bitstream image and
perform simple register and streaming accesses to the sandbox. An RSP requires a hardware
driver with the following capabilities:

• Hardware discovery/enumeration

• Program the FPGA sandbox regions

• Read and write registers inside the sandbox

• Read and write to streaming interfaces inside the sandbox (if the sandbox has streaming
interfaces)

Both PathWave FPGA software and the BSP work together and cannot be used individually.

The block diagram shown in Figure 14 indicates how the bitstream file is generated using both the
PathWave FPGA software and BSP together for any specific supported PXIe module.

Figure 14 Bitstream file compilation flow using PathWave FPGA and BSP

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 37

3 Using the PathWave FPGA Board Support Package (BSP)

PathWave FPGA manages bitstream file generation using a scripted flow of the FPGA tools. The
scripts for building a specific design are provided by the FSP. The FSP build script can also add
metadata, which are delivered to the RSP. The bitstream file and metadata are packaged into a
Keysight PathWave FPGA program archive file with the filename extension *.k7z.

To load a bitstream image on the FPGA, PathWave FPGA supplies the program archive file to the
RSP. The RSP unpacks the contents of the program archive file and checks that the image is
compatible. The original bitstream file and the metadata are then passed to the instrument-specific
portion of the RSP, which eventually configures the FPGA with the bitstream file.

The output from a PathWave FPGA design compilation is saved in a Keysight PathWave FPGA
program archive file, with a k7z extension. To understand how to generate the k7z file onto a module,
see “Generating a k7z file using PathWave FPGA BSP” on page 39.

Hereafter, you may load the k7z file onto the required hardware using the Keysight SD1 3.x SFP
software’s user interface or the corresponding SD1 API functions. To understand how to load the k7z
file onto a module, see “Loading k7z file into modules” on page 48.

For information regarding the Board Support Package for M3102A Digitizer modules, refer to
M3102A Digitizer PathWave FPGA User Guide.

38 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

Section 3.5: Generating a k7z file using PathWave FPGA BSP

After you install BSP for one or more modules, you can proceed with creating a new project to design
the sandbox region for the corresponding modules.

Following steps give you a quick glance into creating a new sandbox project using PathWave FPGA
2020 software for FPGA designing followed by generating a bitstream file for one or more supported
PXIe modules. This example uses the BSP file for an M3102A module.

You can also perform most of the steps shown below using command line arguments. Refer to the
“Advanced Features” section of the PathWave FPGA Customer Documentation.

1 On the main window of the PathWave FPGA 2020 software, click the icon for new project.

A new sandbox project dialog appears.

Figure 15 Creating a new Sandbox project

2Click Next >.

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3 Using the PathWave FPGA Board Support Package (BSP)

3 For the Project Type, choose the BSP corresponding to one of the modules whose FPGA you wish

to update.

Figure 16 Selecting the module-specific BSP

4Click Next >.

40 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

5 For the Project Options, choose the BSP options and Board Configurations you wish to include in

your FPGA design logic for the selected module.

Figure 17 Selecting various options for FPGA design logic

6Click Next >.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 41

3 Using the PathWave FPGA Board Support Package (BSP)

7 For the Project Template, either choose the default template offered within the PathWave FPGA

design environment or choose blank to start a new custom design logic.

Figure 18 Selecting the PathWave FPGA project template

8Click Next >.

42 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

9 Verify all information displayed in the Project Summary. To make any amendments, click Back. If

the selected options for the corresponding BSP are satisfactory, click Finish.

Figure 19 Viewing the project summary information

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 43

3 Using the PathWave FPGA Board Support Package (BSP)

Various blocks are displayed, which are part of the default template in the PathWave FPGA
2020 software.

Figure 20 Viewing FPGA design blocks in the default template

10 Customize the configuration as per your requirements using one or more elements from the

Design Interfaces and IP Catalog panels.
For more information regarding the configurable region of the M3xxxA FPGA interfaces and BSP

IP Repository, refer to the BSP User Guide for the corresponding modules, which can be
accessed via Help > BSPs Help menu options in the PathWave FPGA 2020 software. The guides
for the supported modules are:

• M3102A PXIe Digitizers

• M3100A PXIe Digitizers

• M3201A PXIe Arbitrary Waveform Generators

• M3202A PXIe Arbitrary Waveform Generators

• M3302A PXIe AWG and Digitizer Combination

• M3300A PXIe AWG and Digitizer Combination

44 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

11 After you have finished designing your logic, you can proceed with the k7z file generation. Click

the Generate Bit File... icon as shown in Figure 21.

Figure 21 Initiating Bit File generation for the selected module

If you do not have the Xilinx Vivado Design Suite on the same machine where PathWave FPGA
2020 software and BSP are installed, the following error is prompted when you click the
Generate Bit File... icon.

Refer to PathWave FPGA Customer Documentation for more information on installing the
software and the licenses for the Xilinx Vivado Design Suite.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 45

3 Using the PathWave FPGA Board Support Package (BSP)

12 On the FPGA Hardware Build window that appears, click Run.

Figure 22 Generating FPGA Hardware Build

46 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

Depending on the configuration, the software takes some time before finishing the process of
k7z file generation.

Figure 23 Progress status for the k7z file generation

Once the Bitstream file (which is the k7z file) is generated, your custom FPGA logic is ready to be
loaded on the selected module using either the SD1 API or the Load Firmware feature (under FPGA
menu of the Module panel in the SFP software).

Other than configuring and designing your FPGA Logic using the PathWave FPGA 2020 Update 1.0
software, you can perform one or more of the following operations:

• Build your FPGA Logic

• Generate the Bit File (covered briefly in this section)

• Verify the Bit File

• Simulate your FPGA Logic

• Simulation Testbench Designing

• Test Bench Address Mapping

• Work with Advanced features

• Using Command Line Arguments

• Migrating a design to a new BSP

• Changing a Submodule Project Target Hardware

• Debugging in Hardware

For detailed instructions on performing these steps and to understand the features of the PathWave
FPGA 2020 software, refer to the PathWave FPGA Help file accessible via the Help menu of the
software. For information about the features and various elements along with understanding the
workflow associated with the PathWave FPGA 2020 Update 1.0 software, refer to the “User Guide”
section of the PathWave FPGA Customer Documentation.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 47

3 Using the PathWave FPGA Board Support Package (BSP)

Section 3.6: Loading k7z file into modules

After a bitstream file (k7z) is generated using the PathWave FPGA software, you may use either the
SD1 3.x software user interface or the SD1 API functions to load the FPGA on the corresponding
module and also, verify design compatibility on that module.

3.6.1: Using SD1 SFP user interface to load FPGA

To load the FPGA using SD1 3.x software,
1From the Start menu, launch Keysight SD1 SFP.

2 From the main menu of a specific module’s dialog, click FPGA > Load firmware....

Figure 24 Accessing FPGA firmware loader option in SD1

48 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

3 On the Firmware Loader dialog that appears, click the button to browse for the required k7z file for

that particular module.

Figure 25 Firmware Loader window for the selected module

4Click Load to initiate the process of FPGA loading.

If the progress bar displays “Loading successful” and “100%”, it indicates that the FPGA is updated
as well as the FPGA design logic is compatible on hardware.

3.6.2: Using SD1 API to load FPGA

To load the FPGA using SD1 3.x API,
1 Import system and Keysight SD1 libraries.
2 Open the module with open().
3 Load FPGA sandbox using *.k7z file with FPGAload().
4 (Optional) Read/Write into registers using functions defined in SD_SandboxRegister functions.
5 (Optional) Perform FPGA related operations using other functions defined in SD_Module

functions (specific to Pathwave FPGA).

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 49

3 Using the PathWave FPGA Board Support Package (BSP)

Section 3.7: Implementing BSP using SD1 API - Sample Programs

3.7.1: Sample program using Python for read write on sandbox region

# ----------------------------

# import required libraries

import sys

sys.path.append('C:\Program Files\Keysight\SD1\Libraries\Python')

import keysightSD1

# Set details for the connected module

product=''

chassis=1

slot=9

# open a module

module=keysightSD1.SD_Module()

moduleID=module.openWithSlot(product,chassis,slot)

if moduleID < 0:

print ("Module open error: ",moduleID)

else:

print("Module is: ",moduleID)

# Loading FPGA sandbox using the *.k7z file

error = module.FPGAload(r'..\myHardwareTest.k7z')

numRegisters = 4

# Get list of Registers from the sandbox

registers = module.FPGAgetSandBoxRegisters(numRegisters)

# Print the register properties in register list

for register in registers:

print(register.Name);

print(register.Length);

print(register.Address);

print(register.AccessType);

registerName = 'Register_Bank_A'

# Get Sandbox Register with name "Register_Bank_A"

registerA = module.FPGAgetSandBoxRegister(registerName)

50 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using the PathWave FPGA Board Support Package (BSP) 3

# Write data to Register_Bank_A

error = registerA.writeRegisterInt32(9)

registerNameB = 'Register_Bank_B'

# Get Sandbox Register with name "Register_Bank_B"

registerB = module.FPGAgetSandBoxRegister(registerNameB)

# Write data to Register_Bank_B

error = registerB.writeRegisterInt32(9)

registerNameC = 'Register_Bank_C'

# Get Sandbox Register with name "Register_Bank_C"

sandbox_register_C = module.FPGAgetSandBoxRegister(registerNameC)

# Read data from Register_Bank_B

error = sandbox_register_C.readRegisterInt32()

memoryMap = 'Host_mem_1'

# Get Sandbox memoryMap with name "Host_mem_1"

memory_Map = module.FPGAgetSandBoxRegister(memoryMap)

# Write buffer to memory map

memory_Map.writeRegisterBuffer(0, [1,2,3, 4, 5, 6],

keysightSD1.SD_AddressingMode.AUTOINCREMENT, keysightSD1.SD_AccessMode.DMA)

# Read buffer from memory map

c_value = memory_Map.readRegisterBuffer(0, 6, keysightSD1.SD_AddressingMode.AUTOINCREMENT,

keysightSD1.SD_AccessMode.NONDMA)

print(c_value)

module.close()

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 51

3 Using the PathWave FPGA Board Support Package (BSP)

3.7.2: Sample program using .NET for read write on sandbox region

class Program

{

static void Main(string[] args)

{

SD_AOU awg = new SD_AOU();

// Open awg module

awg.open("", 1, 9);

//Loading FPGA sandbox using .K7z file

int error = awg.FPGAload(@"..\myHardwareTest.k7z");

//Get Sandbox register list

List<SD_SandBoxRegister> registers = awg.FPGAGetSandBoxRegisters(4);

//Print register properties

foreach(SD_SandBoxRegister register in registers)

{

Console.WriteLine(register.Name);

Console.WriteLine(register.Address);

Console.WriteLine(register.Length);

Console.WriteLine(register.AccessType);

}

int[] buffer = { 5, 4, 3, 2 };

int[] registerBuffer = new int[4];

//Write data buffer to register with index 0

registers[0].WriteRegisterBuffer(0, buffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.DMA);

//Read buffer from register with index 0

registers[0].ReadRegisterBuffer(0, registerBuffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.DMA);

SD_SandBoxRegister registerA= awg.FPGAGetSandBoxRegisterByName("Register_Bank_A");

//Write data to register Register_Bank_A

registerA.WriteRegisterInt32(2);

int registerBValue = registerA.ReadRegisterInt32();

SD_SandBoxRegister hostMem = awg.FPGAGetSandBoxRegisterByName("Host_mem_1");

int indexOffset = 2;

//Write data buffer to Host_mem_1 with indexOffset 2

hostMem.WriteRegisterBuffer(indexOffset, buffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.NONDMA);

//Read data buffer to Host_mem_1 with indexOffset 2

hostMem.ReadRegisterBuffer(indexOffset, registerBuffer, SD_AddressingMode.AUTOINCREMENT,

SD_AccessMode.DMA);

}

}

52 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

SD1 3.x Software for M310xA / M330xA Digitizers

User’s Guide

4. Using Keysight SD1 3.x SFP Software

Installing the Keysight SD1 3.x Software Package 55

Launching the Keysight SD1 SFP software 56
Understanding the SD1 SFP features & controls 58
Understanding Digitizer SFP features & controls 64

This chapter describes how to use Keysight SD1 SFP software.

4 Using Keysight SD1 3.x SFP Software

KeysightM3201A/M3202A PXIe AWGs, M3100A/M3102A PXIe Digitizers, and M3300A/M3302A
PXIe AWG/Digitizer Combos can be operated as classical bench-top instruments using Keysight SD1
SFP software; no programming is required.

Keysight SD1 SFP Software provides a fast and intuitive way of operating KeysightM3201A/M3202A
PXIe AWGs, M3100A/M3102A PXIe Digitizers, and M3300A/M3302A PXIe AWG/Digitizer Combos.

Based on your preference, you may also perform various operations using the programming library
provided within Keysight SD1 Core API. An API function is available for almost every control within
the user interface. You can build and run custom scripts to carry out various operations / workflow,
which can be performed by the SD1 SFP user interface.

The sections in this chapter cover the functionality of each SD1 SFP feature available in its user
interface, along with describing the workflow required to perform some specific operations.
Wherever applicable, the API function corresponding to the feature/control has been specified for
reference.

To know about the programming libraries and the available API functions, see Chapter 5, “Using
Keysight SD1 API Command Reference” followed by Chapter 6, “Using SD1 API functions in sample
programs”.

54 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

Section 4.1: Installing the Keysight SD1 3.x Software Package

The Keysight SD1 3.x Software Package includes:

• Keysight SD1 3.x SFP Software

• KF9000A PathWave FPGA Programming Environment (commonly known as PathWave FPGA

software)—required for FPGA logic designing

• PathWave FPGA Board Support Package (BSP)—required for FPGA logic designing

• KS2201A PathWave Test Sync Executive Software—required for integration with HVItechnology

Prior to installing the software package components listed above, the following software must be
installed on your machine that runs a Windows 10 (64-bit) Operating System.

Prerequisites • Keysight IO Libraries Suite 2018 (version 18.0 or later)

• Microsoft .NET 3.5 or later

• Any API interface

• Python 64-bit version 3.7.x or later

• Any C#/.NET Compiler

• Any C/C++ Compiler

• Xilinx Vivado Design Suite (required with PathWave FPGA software)

• License options

• Option -FP1 (to enable FPGA programming through PathWave FPGA BSP)

• Option -HV1 (to implement HVI technology using the PathWave Test Sync Executive software)

Refer to the Keysight SD1 3.x Software Startup Guide for download links and installation
instructions.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 55

4 Using Keysight SD1 3.x SFP Software

Section 4.2: Launching the Keysight SD1 SFP software

After the Keysight SD1 3.x SFP software is installed, click Start > Keysight > Keysight SD1 SFP.

Figure 26 Launching SD1 SFP software from the Start menu

The Keysight SD1 3.x SFP software window is displayed, as shown in Figure 27 and Figure 28.

When SD1 SFP is launched, it identifies all Keysight PXIe hardware modules that are connected to
the embedded controller or desktop computer and opens a corresponding soft front panel for each
piece of hardware. As shown in Figure 27, the soft front panel for the M3201A AWG and M3302A
(AWG & Digitizer) Combo are displayed by default, which indicates these modules are connected.

Figure 27 SD1 SFP software window (online mode with M3201A and M3302A cards connected)

If one or more modules are not inserted into the chassis (or disconnected), the soft front panel for
each of such modules is displayed as “Demo module” on the Keysight SD1 3.x SFP software. See

Figure 28.

56 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

Figure 28 SD1 SFP software (offline mode without any card connected)

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 57

4 Using Keysight SD1 3.x SFP Software

Section 4.3: Understanding the SD1 SFP features & controls

As the name indicates, the Soft Front Panel (SFP) provides you controls so that you may configure
settings associated with the front panel features (namely, Channel, Clock and Trigger) on the
connected PXIe AWG, Digitizer and Combo cards. Considering the basic functionality of an AWG and
a Digitizer, the appearance and functions on each SFP window for AWG modules are different from
that for the Digitizer modules.

The SFP windows that are specific to AWG modules correspond to:

• M3202A AWG 1G

• M3201A AWG 500

• AWG front panel of the M3302A AWG 500 DIG 500 Combo

• AWG front panel of the M3300A AWG 500 DIG 100 Combo

The SFP windows that are specific to Digitizer modules correspond to:

• M3102A DIG 500

• M3100A DIG 100

• DIG front panel of the M3302A AWG 500 DIG 500 Combo

• DIG front panel of the M3300A AWG 500 DIG 100 Combo

The SD1 SFP user interface, primarily, consists of three types of windows:
1 Main window—includes controls for displaying each module window and hardware configuration.
2 AWG Module SFP window—includes front panel controls for performing operations pertaining to

AWGs.

3 Digitizer Module SFP window—includes front panel controls for performing operations pertaining

to Digitizers.

In the offline (Demo) mode, even though the front panel controls appear to be available and even
configurable, they are meant for demonstrative purposes only. On the other hand, when connected,
each module has its respective SFP window and all controls and functions are available. The
following sections describe the controls that appear on each window.

4.3.1: Understanding main window features and controls

Figure shows the SD1 SFP main window without any overlapping SFP window.

Figure 29 SD1 SFP main window

The controls under each menu item are further described in the order displayed above.

58 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

1. File

Figure 30 Controls in the File menu

• Exit—Click File > Exit to close the SD1 SFP main window along with any SFP windows that may be

displayed.

2. Window

Figure 31 Controls in the Window menu

• The menu under Window lists the names assigned to the connected modules. By default, a tick

mark appears against each entry, indicating that the corresponding SFP window is active. Any
name that does not appear indicates that the module is not connected. An offline instance for
each module is available in the Demo Modules sub-menu.

1 To close any SFP window that is open, clear the tick from the corresponding entry.
2 To open an SFP window for a module that is connected, click the corresponding entry.

• Demo Modules—The drop-down sub-menu under Window > Demo Modules lists the names of each

module. You may perform the steps described above, but the corresponding SFP windows that
appear are meant for demonstration purpose only.

3. Help

Figure 32 Controls in the Help menu

• Hardware Manager...—Click Help > Hardware Manager... to launch the Hardware Manager window.

See “Understanding features in Hardware Manager” on page 60 for more information on features
available in the Hardware Manager window.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 59

4 Using Keysight SD1 3.x SFP Software

•About—Click Help > About to view the About Keysight SD1 SFP window. This window conveys the

SD1 SFP software’s version installed on your machine.

Figure 33 About Keysight SD1 SFP window

4.3.2: Understanding features in Hardware Manager

The features in this window are described below in the order shown in Figure 34.

Figure 34 Hardware Manager window

60 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

1 File—The File menu has two items, which are:

Figure 35 Controls in the File menu for Hardware Manager

• Refresh HW list—This feature requires an active network connection to fetch information

from the database. Click File > Refresh HW list so that the SD1 SFP software checks the
Firmware database for any new Firmware version for each M3xxxA module that is
displayed in the Modules area below. If an updated firmware version is found
corresponding to one or more modules, the firmware version is updated/refreshed in the
Available FW Version list. Performing the Refresh HW list is recommended prior to
proceeding with Firmware update using the SD1 SFP software on one or more connected
modules.

• Load update package...—In case your machine is offline, that is, does not have an active

network connection, this feature is useful to load an updated and pre-saved firmware
package so that you can still proceed with firmware updates on one or more connected
M3xxxA modules. Click File > Load update package... to access the Load SDM package...
window, as shown in Figure 36. Navigate to the folder where the firmware update file is
saved. Open the required SDM package file with extension *.sdpkg. You may proceed with
firmware update on the module which the SDM package file corresponds to.

Figure 36 Accessing firmware update file from Load SDM package window

2 Help—The Help > Database Version to view the version of the Firmware update file Database

server.

Figure 37 Control in the Help menu for Hardware Manager

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 61

4 Using Keysight SD1 3.x SFP Software

NOTE

Figure 38 Database Version window

3 Software—This area displays the installed version of the Keysight SD1 SFP software and

programming libraries along with that of the compatible driver.

4 Module—This area consists of the following information:

• Chassis—the Chassis number where the M3xxxA cards are inserted into. Related API

• <M3xxxA>—the model number for one or more modules that are inserted into the specific

Keysight SD1 SFP 3.x software does not recognize cards that have
Firmware version less than 4.0 (for M32xxA/M33xxA modules) or less than

2.0 (for M31xxA modules).

function: “getChassis()”.

Chassis number. The following information is displayed for each module. Related API
function: “getType()”.

Figure 39 Information pertaining to each module in the Hardware Manager window

• Instance name—Product Name assigned to the software instance when the SD1 SFP

detects the connected module. Format is <M3xxxA>#<serial-number>. Related API
function: “getProductName()”.

• Serial Number—Serial number of the connected module. Related API function:

“getSerialNumber()”.

• Options—Hardware license options that are enabled on this module. Related API

function: “getOptions()”.

• HW Version—Hardware version of the module. Related API function:

“getHardwareVersion()”.

• Status—Indicates the current status of the module. ‘ok’ indicates devices is working

properly.

• HW PID—The Product ID number of the Hardware. Indicates which physical options

are available on the product.

• FW PID—The Product ID number of the Firmware. Indicates which firmware elements

are available on the product.

62 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

• Slot—the slot number in the Chassis where the M3xxxA module is inserted into. Related

API function: “getSlot()”.

• Firmware Version—the firmware version currently installed on each M3xxxA module.

Related API function: “getFirmwareVersion()”.

• Available FW Version—’None’ if only the modules are connected but the machine does not

have an active network connection; else, the latest firmware version number that is
available on the Database server.

• Update—By default, the option is ‘No’ for each module. Change to ‘Yes’ for one or more

modules where you wish to perform a firmware update.

5 Update Selected HW—Click the Update Selected HW button to proceed with firmware update on

your selected module, where you have set the Update flag to Yes . The SD1 SFP software then
displays a confirmation prompt asking you to verify if you wish to proceed with the firmware
update using the version listed in the Available FW Version list for the selected module on the
respective Chassis & Slot numbers. For firmware update instructions, refer to SD1 3.x Software
Startup Guide.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 63

4 Using Keysight SD1 3.x SFP Software

NOTE

Section 4.4: Understanding Digitizer SFP features & controls

For all those modules that are connected to the Chassis, the respective soft front panel for the
M3100A/M3102A PXIe Digitizer and that for the Digitizer part of the M3300A/M3302A Combo
appear automatically when SD1SFP is launched. By default, the SFP window for the Digitizer
appears, as shown for M3302A module in Figure 40.

The controls are common across all Digitizer SFP windows. However, the
number of DAQs / Channels that appear depends on the module type.
M31xxA modules and the M3300A Combos support 4 DAQs/Channels
whereas the M3302A Combos support 2 DAQs/Channels.

On this window,

• the default name, which is assigned by the SD1 SFP user interface, is displayed on the bar at the
top.

• the hardware options enabled on the module followed by the serial number, Chassis number and
Slot number are displayed on the bar at the bottom.

• the Channel controls are displayed on the main window whereas the Data Acquisition (DAQ)
controls are included within the main menu items, which are explained in the following section.

• The SFP is divided into Time domain and Frequency domain. The main menu is common to both
domains.

Figure 40 SFP (Time domain) for the connected M3302A after SD1 SFP software is launched

64 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

4.4.1: Understanding DIG SFP main menu features & controls

The controls under each menu item are further described in the order displayed in Figure 40. Images
in this section pertain mainly to M3302A DIG module’s SFP only, but are applicable across all DIG
module SFP windows.

1. File

Note that the functionality of this feature is same as that for AWGSFP. The images shown here are
specific to M3201A SFP; however, the functionality is the same across all SFP windows in the SD1 3.x
software.

Figure 41 Controls in the File menu of the SFP

• Change Name...—Click File > Change Name... to open the Change name module dialog box.

Figure 42 Change name module dialog box

•In the Name: text field, enter an alternate name of your choice.

•Click OK.

The new name appears on the bar at the top of the corresponding module’s SFP window.

• Hide—Click File > Hide to close the module’s SFP window instance.

• To show/open the same window again, click Window > <module name> from the main menu of
the Keysight SD1 SFP software. See description for “Window” in “Understanding main window

features and controls” on page 58.

2. Settings

Here, the controls for DAQ are available in the upper part.

Figure 43 Controls in the Settings menu of the DIG SFP

• DAQ External Triggers...—Click Settings > DAQ External Triggers... to open the Configure DAQ Triggers
dialog box. See “Setting the Configure DAQ Triggers dialog” on page 70 for more description.

• Related API function: “DAQtriggerExternalConfig()”

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 65

4 Using Keysight SD1 3.x SFP Software

• DAQ Settings—Click Settings > DAQ Settings > DAQ n to open the DAQ n Settings dialog box. See
“Setting the DAQ Settings dialog” on page 71 for more description.

• DAQ Trigger—Click Settings > DAQ Trigger > Send Trigger to send a trigger to the selected DAQs in
the same sub-menu. By default, all DAQs are selected.

• Related API functions: “DAQtrigger()”, “DAQtriggerMultiple()”, “DAQtriggerConfig()”

Figure 44 Controls in DAQ Trigger sub-menu

•Click one or more DAQ n (where, n = DAQ number) entries to clear the tick mark; thereby,
refraining them from receiving the trigger when you click Send Trigger.

• Alternatively, you may use the shortcut controls to send trigger to DAQs.

Figure 45 Shortcut controls for sending trigger to DAQs

• Trigger/Clock...—Click Settings > Trigger/Clock... to open the Trigger / Clock Settings dialog box.
While the DAQ receives the data on trigger, the functionality of the user interface is the same as
that for Trigger / Clock Settings dialog in AWG SFP modules. See Setting the Trigger / Clock

Settings dialog for more information.

• Related API functions: “triggerIOconfig()”, “clockIOconfig()”

3. FPGA

This feature functions in the same manner across all SFPs.

Figure 46 Control in the FPGA menu of the SFP

• Load firmware...—Click FPGA > Load firmware... to open the Firmware Loader dialog box, where you
can load the bitstream file (*.k7z) onto the FPGA sandbox region of the corresponding module. For
more information on how to load the bitstream file onto the FPGA sandbox region, see “Using SD1

SFP user interface to load FPGA” on page 48.

• Related API function: “FPGAload()”

66 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

4. Help

This feature functions in the same manner across all SFPs.

Figure 47 Control in the Help menu of the SFP

• Module User Guide...—Click Help > Module User Guide... to view the documentation corresponding
to Digitizer/Combo modules in Online Help format. For more information, see “Accessing Online

Help for SD1 3.x software” on page 200.

4.4.2: Other DIG SFP features & controls

5. Time

The Time domain, whose functionality is like that of Oscilloscope, is displayed by default. The controls
in this tab are explained further.

Using Keysight SD1 3.x SFP Software 4

6. Display

The display is similar to that of the Oscilloscope and plots the input waveform on the time scale. You
can alter the way the waveform is plotted by using the Channel controls.

7. Points

Indicates the number of sample points to be acquired in a Data Acquisition. Make sure that the input
integer is an even number.

8. Trigger

i Channel—Enter the number for the corresponding Channel n (where, n = Channel number)

where the trigger is checked. Note that each Channel is color-coded, so that the applied
trigger inherit the same color as shown on the selected Channel for easy identification,
when triggers on multiple Channels are applied.

• Positive Edge—(default) indicates that the Trigger is generated when the input signal is

rising and crosses the configured threshold value.

• Negative Edge—indicates that the Trigger is generated when the input signal is falling

and crosses the configured threshold value.

• Both Edges—indicates that the Trigger is generated when the input signal crosses the

configured threshold value, irrespective of whether it is rising or falling.

ii Threshold—indicates the threshold voltage level (in units of Volts), which the input signal

must attain for the Trigger to be generated.

iii Delay—indicates the time delay (in units of sampling points) on the input signal, after

which the Trigger is generated.

iv Mode—select one of the following drop-down options:

• Normal—(default) Triggering is generated when the conditions defined for Edge,

Threshold and Delay levels are met.

• Auto—Triggering is generated irrespective of the conditions defined for Edge,

Threshold and Delay levels.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 67

4 Using Keysight SD1 3.x SFP Software

9. Channel

Select the check box for the corresponding Channel n (where, n = Channel number) where the input
sampling points can be plotted as a waveform. Note that each Channel is color-coded, so that the
waveforms inherit the same color as shown on the selected Channel for easy identification, when
multiple waveforms are displayed.

i Full Scale—configures scalability of the input waveform on the Digitizer SFP display.

ii Position—configures positioning of the input waveform on the Digitizer SFP display.

iii Prescaler—configures the value by which the effective sampling rate must be reduced.

iv Impedance—configures the impedance value for AC coupling and DC coupling on the input

10. Single

•Click the Single button to capture a single acquisition of the waveform.

11. Run

•Click the Run button to capture a continuous acquisition of the waveform.

• Secondary—Trigger is generated through a secondary triggering mode.

waveform.

12. Frequency

The Frequency domain, whose functionality is like that of a spectrum analyzer, has common Channel
controls described so far, but for the additional Window feature, which is available in this domain
only, as shown in Figure 48.

68 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

Using Keysight SD1 3.x SFP Software 4

Figure 48 SFP (Frequency domain) for the connected M3302A

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 69

4 Using Keysight SD1 3.x SFP Software

13. Window

Window is a mathematical function that is zero-valued outside of some chosen interval and it is used
in applications including spectral analysis.

• Select one of the following window functions from the drop-down options to apply on the Digitizer
signals:

• Rectangular—Simplest B-spine window

• Bartlett—Hybrid window

• Hanning—Side-lobes roll off about 18 dB per octave

• Hamming—Optimized to minimize the maximum nearest side lobe

• Blackman—(default) Higher-order generalized cosine windows for applications that require
windowing by the convolution in the frequency-domain

14. Channel n

(n represents the Channel number)

• Select the check box for the corresponding Channel number on the module, where the selected
Window function must be applied.

15. Display

The display is similar to that of a Spectrum Analyzer and plots the input waveform on the time scale.
You can alter the way the waveform is plotted by using the Channel controls, described earlier in this
section.

4.4.3: Configuring DAQ and Trigger/Clock Setting dialogs

1. Setting the Configure DAQ Triggers dialog

If you are using an external trigger source to send trigger to one or more DAQs, you must configure
the Configure DAQ Triggers dialog box.

Figure 49 Configure DAQ Triggers dialog box

1 Select one or more rows to enable external triggering for DAQ n, where n = DAQ number.
2 Trigger Mode indicates the mode when the trigger signal must be sent. From the Trigger Mode

drop-down options, select one of the following options:

• Disabled—(default) indicates that external triggering is disabled for the selected DAQ.

• Active High—indicates that the trigger signal must be sent when active high voltage on the
signal is attained.

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• Active Low—indicates that the trigger signal must be sent when active low voltage on the signal
is attained.

• Rising Edge—indicates that the trigger signal must be sent when the rising edge on the signal is
attained.

• Falling Edge—indicates that the trigger signal must be sent when the falling edge on the signal
is attained.

3 Trigger Line indicates the line medium to be used for the trigger signal to be sent. This field is

enabled for all Trigger Mode options except for Disabled. From the Trigger Line drop-down options,
select one of the following options:

• Extern 1 / Extern 2—indicates that line 1 / line 2 from the external triggering source is used to
send the trigger signal.

• PXI n (where, n = 0 to 7)—indicates that lines 0 to 7 from the PXI backplane trigger source can
be used to send the trigger signal. PXI0 is the default option.

4 Sync—By default, the setting to synchronize the DAQ with the trigger source is disabled. You may

select the check box to enable synchronization.

5Click OK to save any changes and return to the DIG module window.

2. Setting the DAQ Settings dialog

To indicate the triggering mode on each DAQ, you must configure the DAQ n settings dialog box
(where, n = DAQ number). Also, see “DAQ Trigger” on page 17 for more information.

Figure 50 Configure DAQ Setting dialog box

• Trigger Mode—Select one of the following drop-down options:

• Auto—The acquisition is triggered immediately after the DAQ has started, irrespective of the
triggering source.

• Analog—(default) The acquisition is triggered using an analog triggering source. The DAQ waits
for an external analog trigger (applicable only for products with analog inputs).

• SW/HVI—The acquisition is triggered using any triggering software or using an HVI function. In
either case, the Digitizer must be connected and operational.

• External—The acquisition is triggered using an external digital triggering source.

•Click OK to save any changes and return to the Digitizer module window.

3. Setting the Trigger / Clock Settings dialog

• While the DAQ acquires data on trigger, the functionality of the user interface is the same as that
for Trigger / Clock Settings dialog in AWG SFP modules. If you are using an External Trigger / Clock
source, you can control the point when the trigger must be applied. Use the Trigger / Clock Settings
dialog to perform this action.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 71

4 Using Keysight SD1 3.x SFP Software

Figure 51 Trigger / Clock Settings dialog box

1 Select the check box for either External Clock, External Trigger, or both to indicate which external

source is being used.

2 External Clock—From the Value drop-down options, select:

• Output Disabled—indicates that the signal from the external clock source is not included in the
AWG output.

• Output Enabled—(default) indicates that the signal from the external clock source is included in
the AWG output.

3 External Trigger—From the Value drop-down options, select:

• Input—Indicates that the signal from the external trigger source is used only to trigger the input
waveform at the selected DIG Channels.

• Output + Input—(default) Indicates that the signal from the external trigger source is used to
trigger both the DIG input and DAQ waveforms.

4Click OK to save any changes and return to the DIG module window.

72 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

SD1 3.x Software for M310xA / M330xA Digitizers

User’s Guide

5. Using Keysight SD1 API Command Reference

Keysight Supplied Native Programming Libraries 74
Support for Other Programming Languages 75
Functions in SD1 Programming Libraries 76
SD_Module functions 88
SD_AIN functions 108
SD_Module functions (specific to Pathwave FPGA) 166
SD_SandboxRegister functions 176

Programs can run on an embedded controller or desktop computer and be controlled with Keysight
SD1 Programming Libraries. Keysight supplies a comprehensive set of highly optimized software
instructions that controls off-the-shelf functionalities of Keysight hardware. These software
instructions are compiled into the Keysight SD1 Programming Libraries. The use of customizable
software to create user-defined control, test and measurement systems is commonly referred as
Virtual Instrumentation. In Keysight documentation, the concept of a Virtual Instrument (or VI)
describes user software that uses programming libraries and is executed by a computer.

5 Using Keysight SD1 API Command Reference

Section 5.1: Keysight Supplied Native Programming Libraries

Keysight provides ready-to-use native programming libraries for a comprehensive set of
programming languages, such as C, Visual Studio (C#, VB), Python, etc., ensuring full software
compatibility and seamless multi-vendor integration. Ready-to-use native libraries are supplied for
the following programming languages and compilers:

Table 18 List of programming languages and compilers

Language Compiler Library Files

Microsoft Visual Studio .NET .NET Library *.dll

C

C++ Any C++ compiler Header only *.h

C# Microsoft Visual Studio .NET .NET Library *.dll

Python Any Python compiler Python Library *.py

Basic Microsoft Visual Studio .NET .NET Library *.dll

MinGW (Qt) C Library *.h, *.lib

Any C compiler C Library *.h, *.lib

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Section 5.2: Support for Other Programming Languages

Keysight provides dynamic libraries, such as DLLs, that can be used in virtually any programming
language. Dynamic-link libraries are compatible with any programming language that has a compiler
capable of performing dynamic linking. Here are some case examples:

• Compilers not listed above.

• Other programming languages: Java, PHP, Perl, Fortran, Pascal.

• Computer Algebra Systems (CAS): Wolfram Mathematica, Maplesoft Maple.

• DLL function prototypes—The exported functions of the dynamic libraries have the same

prototype as their counterparts of the static libraries.

• Function Parameters—Some of the parameters of the library functions are language dependent.

The table of input and output parameters for each function is a conceptual description, therefore,
the user must check the specific language function to see how to use it. One example are the ID
parameters (moduleID, etc.), which identify objects in non object-oriented languages. In
object-oriented languages, the objects are identified by their instances and therefore the IDs are
not present.

• Function Names—Some programming languages like C# have a feature called function

overloading or polymorphism, that allows creating several functions with the same name, but with
different input/output parameters. In languages without this feature, functions with different
parameters must have different names.

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 75

5 Using Keysight SD1 API Command Reference

Section 5.3: Functions in SD1 Programming Libraries

The functions available in Keysight SD1 Programming Libraries are listed below.

• SD_Module functions

• SD_AIN functions

• SD_Module functions (specific to Pathwave FPGA)

• SD_SandboxRegister functions

Note that there are a few API functions that are specific to M3300A/M3302A PXIe Combo Cards. The
syntax for these API functions use the “SD_AIO” class, which represents Combo modules and use the
“port” parameter to distinguish between the AWG and the Digitizer within. These API functions have
been developed with the flexibility to exclusively use the “SD_AOU” or “SD_AIN” class specifically for
AWG or Digitizer cards, respectively.

Table 19 List of SD_Module Functions

Function name Short description

open Initializes a hardware module and must be called before using any other

close Releases all resources that were allocated for a module with open and must

moduleCount Returns the number of Keysight SD1 modules in the system.

getProductName Returns the product name of the specified module.

getSerialNumber Returns the serial number of the specified module.

getChassis Returns the chassis number of where a module is located.

getSlot Returns the slot number of where a module is located.

PXItriggerWrite Sets the digital value of a PXI trigger in the PXI backplane. Only available in

PXItriggerRead Reads the digital value of a PXI trigger in the PXI backplane. Only available in

getFirmwareVersion Returns the firmware version of the module.

getHardwareVersion Returns the hardware version of the module.

getOptions Returns all the available option for selected card.

getTemperature Returns the temperature of the module.

getType Returns the type of module.

isOpen Returns true if module is opened successfully.

module-related function.

always be called before exiting the application.

PXI/PXI Express form factors.

PXI/PXI Express form factors.

translateTriggerIOtoExternalTriggerLine Returns the translated external trigger value.

translateTriggerPXItoExternalTriggerLine Returns the translated PXI trigger value.

runSelfTest Performs a self test on the open module.

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Table 20 List of SD_AIN Functions

Function name Short description

channelCoupling Returns the coupling of the specified channel.

channelFullScale Returns fullScale value for the specified channel.

channelImpedance Returns the impedance of the specified channel.

channelInputConfig Configures the input full scale, impedance and coupling.

channelMaxFullScale Returns maximum fullScale value for the specified input coupling and impedance.

channelMinFullScale Returns minimum fullScale value for the specified input coupling and impedance.

channelPrescaler Returns the prescaler value for the specified channel.

channelPrescalerConfig Configures the input prescaler.

channelPrescalerConfigMultiple Configures prescaler on the selected Digitizer channels.

channelTriggerConfig Configures the analog trigger block for each channel Analog Trigger.

DAQanalogTriggerConfig Configures the analog hardware trigger for the selected DAQ Trigger.

DAQconfig Configures the acquisition of words Data Acquisition (DAQs) in two possible reading

DAQdigitalTriggerConfig Configures the digital hardware triggers for the selected DAQ Trigger.

DAQread Reads the words acquired with the selected DAQ Data Acquisition (DAQs).

DAQstart Starts an acquisition on the selected DAQ Data Acquisition (DAQ).

DAQstartMultiple Starts an acquisition on the selected DAQs Data Acquisition (DAQs).

DAQstop Stops the Data Acquisition (DAQ).

DAQstopMultiple Stops multiple channels of Data Acquisition (DAQs).

DAQpause Pauses the Data Acquisition (DAQ).

DAQpauseMultiple Pauses multiple channels of Data Acquisition (DAQs).

DAQresume Resumes acquisition on the selected DAQ.

DAQresumeMultiple Resumes multiple channels of acquisition on the selected DAQs.

DAQflush Flushes the acquisition buffers and resets the acquisition counter included in a data

DAQflushMultiple Flushes the acquisition buffers and resets the acquisition counter included in a Data

DAQnPoints Returns the counter of DAQ.

DAQtrigger Triggers the acquisition of words in the selected DAQs provided that they are configured for

modes.

acquisition block.

Acquisition block.

VI/HVI Trigger.

DAQtriggerMultiple Triggers the acquisition of words in the selected DAQ provided that they are configured for

DAQtriggerConfig Configures DAQ for the selected DAQ Trigger.

DAQcounterRead Reads the number of words acquired by the selected DAQ (Data Acquisition (DAQs))

triggerIOconfig Configures the trigger connector/line direction (I/O Triggers).

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 77

VI/HVI Trigger.

since the last call to DAQflush or DAQ.

5 Using Keysight SD1 API Command Reference

Function name Short description

triggerIOwrite Sets the trigger output and synchronization mode.

triggerIOread Reads the trigger input (I/O Triggers).

clockSetFrequency Sets the module clock frequency.

clockGetFrequency Returns the frequency of Clock System.

clockGetSyncFrequency Returns the frequency of the synchronization clock.

clockIOconfig Configures the operation of the clock output connector.

clockResetPhase Sets the module in a synchronized state, waiting for the first trigger to reset the phase of the

DAQbufferPoolConfig Configures buffer pool that will be filled with the data of the channel to be transferred to PC.

DAQbufferAdd Adds an additional buffer to the channel’s previously configured pool.

DAQbufferGet Retrieves a filled buffer from the channel buffer pool. You have to call DAQbufferAdd with this

DAQbufferPoolRelease Releases the channel buffer pool and its resources. After this function is called, you need to

DAQbufferRemove Requests that a buffer be removed from the channel buffer pool. If a NULL pointer is returned,

DAQtriggerExternalConfig Configures DAQ for the external trigger source.

FFT Calculates the FFT of data captured by DAQread for the selected channel. FFT frequency

voltsToInt Converts threshold in ChannelTriggerConfig() from ‘double’ to ‘integer’.

Table 21 List of SD_Module Functions (specific to PathWave FPGA)

Function name Short description

FPGAgetSandBoxRegister Get sandbox register from name if programmable FPGA is loaded from.k7z file.

FPGAgetSandBoxRegisters Get sandbox registers list if programmable FPGA is loaded from.k7z file.

internal clocks CLKsync and CLKsys.

buffer so the buffer can be used again.

call DAQbufferRemove consecutively to get all buffers back and release them.

no more buffers remain in the buffer pool. Returned buffer is a previously added buffer from
the user and the user has to release/delete it.

range goes from 0 to fs/2.

FPGAload Loads the bit file (*.k7z), which is generated using PathWave FPGA, onto the respective

FPGAreset Sends a reset signal to the Sandbox region.

FPGATriggerConfig Configures PXI or FrontPanel triggers coming in or going out from sandbox region.

FPGAconfigureFromK7z Configures the FPGA Sandbox region using the K7z bitstream file, without loading it onto the

FPGAGetKernelUUID Gets the KernelUUID string from the FPGA Sandbox region.

User FPGA HVI Actions/Events Defines the HVI Actions & Events, which are available for sending information to and

78 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

module’s FPGA.

module.

receiving information from the FPGA sandbox.

Using Keysight SD1 API Command Reference 5

Table 22 List of SD_Module HVI Functions

Function name Short description

Module HVI Engine Enables HVI Engines located in the M3xxxA module’s FPGA.

Module HVI Triggers Activates PXI or Front Panel triggers for HVI sequences.

Table 23 List of SD_SandboxRegister Functions

Function name Short description

readRegisterBuffer Reads data buffer from a sandbox register bank or memory map.

readRegisterInt32 Reads int32 data from a sandbox register bank or memory map.

writeRegisterBuffer Writes data buffer to a sandbox register bank or memory map.

writeRegisterInt32 Writes int32 data to a sandbox register bank or memory map.

Properties Displays properties associated with registers.

5.3.1: Common References to parameter values

Following certain parameters and their respective values, which are required for one or more API
functions.

Table 24 Clock Output options and corresponding values

Options Description Value

Disable The CLK connector is disabled. 0

CLKrefOutput The reference clock is available at the CLK connector. 1

Table 25 Analog Trigger Mode options

Option Description Name Value

Positive Edge Trigger is generated when the input signal is rising and crosses the

threshold

Negative Edge Trigger is generated when the input signal is falling and crosses the

threshold

Both Edges Trigger is generated when the input signal crosses the threshold, no

matter if it is rising or falling

AIN_RISING_EDGE 1

AIN_FALLING_EDGE 2

AIN_BOTH_EDGES 3

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Table 26 DAQ Trigger Mode options

Option Description Name Value

Auto (Immediate) The acquisition starts automatically after a call to function DAQstart AUTOTRIG 0

Software / HVI Software trigger. The acquisition is triggered by the function DAQtrigger,

Hardware Digital
Tri gger

Hardware Analog
Tri gger

Table 27 External Hardware Digital Trigger Source for the DAQ

Option Description Name Value

External I/O
Tri gger

PXI Trigger PXI form factor only. The DAQ trigger is a PXI trigger line and it is

Table 28 Trigger behavior for the DAQ

Option Description Name Value

None No trigger has been activated TRIGGER_NONE 0

Active High Trigger is active when it is at level high TRIGGER_HIGH 1

Active Low Trigger is active when it is at level Low TRIGGER_LOW 2

DAQtrigger provided that the DAQ is running. DAQtrigger can be
executed from the user application (VI) or from an HVI.

Hardware trigger. The DAQ waits for an external digital trigger (see

Table 27 External Hardware Digital Trigger Source for the DAQ).

Hardware trigger. The DAQ waits for an external analog trigger (only
products with analog inputs).

The DAQ trigger is a TRG connector/line of the product (I/O Triggers).
PXI form factor only: this trigger can be synchronized to CLK10.

synchronized to CLK10.

SWHVITRIG 1

HWDIGTRIG 2

HWANATRIG 3

TRIG_EXTERNAL 0

TRIG_PXI 0-7

Rising Edge Trigger is active on the rising edge TRIGGER_RISE 3

Falling Edge Trigger is active on the falling edge TRIGGER_FALL 4

Table 29 Trigger Direction options and corresponding values

Options Description Name Value

Trigger Output
(readable)

Trigger Input TRG operates as a trigger input, or as a general purpose digital input

80 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

TRG operates as a general purpose digital output signal, that can be
written by the user software.

signal, that can be read by the user software.

AIN_TRG_OUT 0

AIN_TRG_IN 1

Using Keysight SD1 API Command Reference 5

Table 30 Sync mode options and corresponding values

Options Description Name Value

Non-synchronized mode The trigger is sampled with an internal 100 MHz clock. SYNC_NONE 0

Synchronized mode (PXI form factor only) The trigger is sampled using CLK10*. SYNC_CLK10 1

* In synchronized mode, the trigger is synchronized to the nearest clock edge of the 10 MHz clock from the PXI chassis backplane. If us­ing an external trigger, it should also be synchronized to the same 10 MHz reference. The trigger is sampled using CLKsync. If it is a multi­ple of 10 MHz, the maximum processing time would be less than 100 ns, varying depending on trigger arrival. If CLKsync is less than 10
MHz, the processing time will be greater than 100 ns.

Table 31 Variable clock system operation mode options and corresponding values

Options Description Name Value

Low JitterMode The clock system is set to achieve the lowest jitter, sacrificing tuning

speed.

Fast Tuning Mode The clock system is set to achieve the fastest tuning time, sacrificing jitter

performance.

Table 32 SD_ResetMode attribute values

Attribute Value

LOW 0 (to exit reset mode / “HIGH” state of the sandbox region)

HIGH 1 (to initiate reset mode and keep the sandbox region in the same mode until a “LOW” state is used to exit reset mode)

PULSE 2 (to reset the sandbox region by sending a “pulse”)

Table 33 FPGATriggerDirection attribute values

Attribute Value

IN 0

INOUT 1

Table 34 TriggerPolarity attribute values

Attribute Value

CLK_LOW_JITTER 0

CLK_FAST_TUNE 1

ACTIVE_LOW 0

ACTIVE_HIGH 1

Table 35 Window Types Used in FFT Functions

Option Description Name Value

Rectangular Simplest B-spine window WINDOW_RECTANGULAR 0

Bartlett Hybrid window WINDOW_BARTLETT 1

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Option Description Name Value

Hanning Side-lobes roll off about 18 dB per octave WINDOW_HANNING 2

Hamming Optimized to minimize the maximum nearest side lobe WINDOW_HAMMING 3

Blackman Higher-order generalized cosine windows for applications that require

windowing by the convolution in the frequency-domain

WINDOW_BLACKMAN 4

82 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

5.3.2: Data transfer rates

Tabl e 37 shows the data transfer rate (download speed) to both M3102A DIG 500 and M3100A DIG

100 modules, calculated for specific number of points per cycle for 1 cycle. The average values of
time and data rate have been calculated over five iterations using the following configuration:

• Operation System — Windows 10 (64-bit)

• RAM — 16 GB

• Processor Speed — 2.40 GHz

Table 36 Data upload speed to DIG modules

Points per Cycle

1000 205.9 9.79 156.4 13.2

10,000 326.31 61.52 266.0 77.27

1,00,000 1612.79 124.06 1547.4 129.61

Average Time (µs) Average Data Transfer

Using Keysight SD1 API Command Reference 5

Python C++

Average Time (µs) Average Data Transfer

Rate (MBps)

Rate (MBps)

5,00,000 7754.98 128.97 7478.6 133.787

10,00,000 15667.91 127.70 14844.2 134.835

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NOTE

5.3.3: Latency in Digitizers for various HVI Actions & Instructions

Tabl e 37 displays the HVI actions and instructions along with the corresponding latency measured

for Digitizers. The latency value for each instruction or action is determined and measured based on
the GateWare design. You must use the measured values for the instructions as shown in the
following table.

Table 37 Latency (in nanoseconds) for HVI Actions & Instructions

HVI Actions / Instructions Latency in M3102A (DIG 500) Comments

ChannelPrescalerConfig 30 Notes 2, 3

ChannelTriggerConfig 30 Notes 2, 3

DAQConfig 80 Notes 1, 3

DAQFlush 170 Notes 2, 3

DAQTrigger 330 Notes 2, 3

DAQStart 120 Notes 2, 3

Notes:

1. “DAQConfig” is a multi-step instruction, which takes 20ns to run.

2. This HVI action / instruction takes 10ns to run.

3. The HVI actions / instructions in Digitizers are mutually exclusive, that is, cannot be run simultaneously.

To calculate latency, certain timing parameters in the HVI statements include the
“Instrument_SyncResources_Latency” value, which is specific for each instrument/module
being used. For all SD1 modules, the “Instrument_SyncResources_Latency” value is set to
‘0’ cycles. For more information, refer to Chapter 7: HVI Time Management and Latency in the
KS2201A PathWave Test Sync Executive User Manual.

HVI related latency in FPGA User Sandbox

The FPGA registers and Memory map access latency from HVI for both AWG and Digitizers is
measured as: HVI_FPGA_ProductDelay = 1 cycles (10ns). Refer to the SD1 3.x Software for M320xA
/ M330xA AWG User’s Guide for latency information in AWGs. Tab le 3 8 summarizes the latency for
all FPGA read/write instructions. For more information regarding latencies related to HVI, refer to
Chapter 7: HVI Time Management and Latency in the PathWave Test Sync Executive User Manual.

Table 38 Minimum delay required (in nanoseconds) for FPGA User Sandbox instructions

Instructions Minimum Delay required

fpga_array_read 60

fpga_array_read (Address from HviRegister) 80

fpga_array_write 30

fpga_array_write (Address or data from HviRegister) 50

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Instructions Minimum Delay required

fpga_register_read 60

fpga_register_write 30

fpga_register_write (Address or data from HviRegister) 50

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5 Using Keysight SD1 API Command Reference

TriggerIO and Action Groups

When writing HVI Native local instructions, any number of TriggerIOs can be written at the same
time. TriggerIOs are organized in groups of 16. The Fetch time of the instruction depends on the
number of different TriggerIO groups included in the instruction (#TriggerIOGroups).

Tabl e 39 shows the elements in the TriggerIO Group.

Table 39 Elements in TriggerIO Group

Group Elements

Tri gger IOGr oup_ 0

* The group TriggerIOGroup_0 applies to all AWG, DIG and Combo modules. However, the element ‘FrontPanel2’ trigger applies to the
Combo cards only.

FrontPanel1

FrontPanel2*

The action-execute HVI instruction synchronously runs a list of HVI actions that you have defined.
HVI actions are organized in groups that can contain up to 16 actions. Each M3XXXA defines its own
groups of actions, which are shown below.

Any number of HVI actions can be run synchronously, regardless of the group to which each action,
which you have specified, belongs. However, the number of action groups included in the
action-execute instruction (#ActionGroups) will affect both the Fetch time and the Execution time of
the instruction.

Tabl e 40 shows the action names in the AWG Action Group.

Table 40 Action names in AWG Action Group

Group Action names

CH1ResetPhase - CH4ResetPhase

ActionGroup_0

AWG1Start - AWG4Start

AWG1Stop - AWG4Stop

AWG1Pause - AWG4Pause

AWG1Resume - AWG4Resume

ActionGroup_1

ActionGroup_2 UserFpga0 - UserFpga7

86 SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide

AWG 1Trigger - A WG4Trigger

AWG1JumpNextWaveform - AWG4JumpNextWaveform

AWG1QueueFlush - AWG4QueueFlush

Tabl e 41 shows the action names in the DIG Action Group.

Table 41 Action names in DIG Action Group

Group Action names

DAQ1Start - DAQ4Start

Using Keysight SD1 API Command Reference 5

ActionGroup_0

ActionGroup_1

DAQ1Stop - DAQ4Stop

DAQ1Resume - DAQ4Resume

DAQ1Trigger - DAQ4Trigger

DAQ1Flush- DAQ4Flush

UserFpga0 - UserFpga7

Tabl e 42 shows the action names in the Combo Action Group.

Table 42 Action names in Combo Action Group

Group Action names

CH1ResetPhase - CH4ResetPhase

ActionGroup_0

ActionGroup_1

AWG1Start - AWG4Start

AWG1Stop - AWG4Stop

AWG1Pause - AWG4Pause

AWG1Resume - AWG4Resume

AWG 1Trigger - A WG4Trigger

AWG1JumpNextWaveform - AWG4JumpNextWaveform

AWG1QueueFlush - AWG4QueueFlush

DAQ1Start - DAQ4Start

ActionGroup_2

ActionGroup_3 DAQ1Flush - DAQ4Flush

SD1 3.x Software for M310xA / M330xA Digitizers User’s Guide 87

DAQ1Stop - DAQ4Stop

DAQ1Resume - DAQ4Resume

DAQ1Trigger - DAQ4Trigger

UserFpga0 - UserFpga7

5 Using Keysight SD1 API Command Reference

Section 5.4: SD_Module functions

5.4.1: open

Description Initializes a hardware module and must be called before using any other module-related function. A

module can be opened using the serial number or the chassis and slot number. Using the serial
number ensures the same module is always opened regardless of its chassis or slot location.

Parameters Table 43 Input parameters for open

Input Parameter name Description

productName Module’s product name (for example, “M3102A” or “M3202A”). The product name can be found on the product or can be retrieved

serialNumber Module’s serial number (for example, “ES5641”). The serial number can be found on the product or can be retrieved with

chassis

nChassis

nSlot Slot number in the chassis where the module is located. The slot number can be found on the chassis or can be retrieved with getSlot.

compatibility Forces the channel numbers to be compatible with legacy models. Channel numbering (channel enumeration) can start as CH0 or

partNumber Name of the module such as “M3102A” or “M3202A”.

options The format of the <options> string is “optionName1=value1, optionName2=value2, and so on.”

Output Parameter name Description

moduleID (Non-object-oriented languages only) Module identifier or a negative number that indicates an error, see Description of SD1 Error IDs.

errorOut See Description of SD1 Error IDs.

with getProductName.

getSerialNumber.

Chassis number where the module is located. The chassis number can be found in Keysight SD1 software or can be retrieved with

getChassis.

CH1. See Channel Numbering and Compatibility Mode.

Valid Values are:
simulate=true|false.
If ‘true’, the module is open as a simulated (demo) card.
channelNumbering=Signadyne|Keysight, HVI2=true|false and Factory=XX.
Signadyne modules label their channel numbers starting from 0, Keysight modules start from 1.

Table 44 Output parameters for open

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Syntax Table 45 API syntax for open

Language Syntax

C int SD_Module_openWithSerialNumber(const char* productName, const char* serialNumber);

int SD_Module_openWithSlot(const char* productName, int chassis, int nSlot);

int SD_Module_openWithSerialNumberCompatibility(const char* productName, const char* serialNumber,

int compatibility);

int SD_Module_openWithSlotCompatibility(const char* productName, int chassis, int nSlot, int

compatibility);

int SD_Module_openWithOptions(const char *partNumber, int chassis, int nSlot, const char *options);

C++ int SD_Module::open(std::string partNumber, int nChassis, int nSlot, int compatibility);

int SD_Module::open(std::string partNumber, std::string serialNumber, int compatibility);

int SD_Module::open(std::string partNumber, int nChassis, int nSlot);

int SD_Module::open(std::string partNumber, std::string serialNumber);

int SD_Module::open(std::string partNumber, int nChassis, int nSlot, std::string options);

.NET, MATLAB int SD_Module::open(string productName, string serialNumber);

int SD_Module::open(string productName, int chassis, int nSlot);

int SD_Module::open(string productName, string serialNumber, int compatibility);

int SD_Module::open(string productName, int chassis, int nSlot, int compatibility);

int SD_Module::open(string partNumber, int nChassis, int nSlot, string options);

Python SD_Module.openWithSerialNumber(partNumber, serialNumber)

SD_Module.openWithSlot(partNumber, nChassis, nSlot)

SD_Module.openWithSerialNumberCompatibility(partNumber, serialNumber, compatibility)

SD_Module.openWithSlotCompatibility(partNumber, nChassis, nSlot, compatibility)

SD_Module.openWithOptions(partNumber, nChassis, nSlot, options)

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5.4.2: close

Description Releases all resources that were allocated for a module with open and must always be called before

exiting the application.

Parameters Table 46 Input parameters for close

Input Parameter name Description

moduleID (Non-object-oriented languages only) Module identifier, returned by open.

Table 47 Output parameters for close

Output Parameter name Description

errorOut See Description of SD1 Error IDs.

Syntax Table 48 API syntax for close

Language Syntax

C int SD_Module_close(int moduleID);

C++ int SD_Module::close();

.NET, MATLAB int SD_Module::close();

Python SD_Module.close()

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NOTE

5.4.3: moduleCount

Description Returns the number of Keysight SD1 modules (M31xxA/M32xxA/M33xxA) installed in the system.

(Specific to object-oriented programming languages only) moduleCount is a
static function.

Parameters Table 49 Output parameters for moduleCount

Output Parameter name Description

nModules Number of Keysight SD1 modules installed in the system. Negative numbers indicate an error. See Description of SD1 Error IDs.

errorOut See Description of SD1 Error IDs.

Syntax Table 50 API syntax for moduleCount

Language Syntax

C int SD_Module_count();

C++ int SD_Module::moduleCount();

.NET, MATLAB int SD_Module::moduleCount();

Python SD_Module.moduleCount()

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NOTE

5.4.4: getProductName

Description Returns the product name of the specified module.

(Specific to object-oriented programming languages only) getProductName
is a static function. Object-oriented languages also have a non-static
function without arguments.

Parameters Table 51 Input parameters for getProductName

Input Parameter name Description

index Module index. It must be in the range (0 to nModules-1), where nModules is returned by moduleCount.

chassis Chassis number where the module is located. The chassis number can be found in Keysight SD1 software or can be retrieved with

slot Slot number in the chassis where the module is located. The slot number can be found on the chassis or can be retrieved with

moduleId Module identifier returned by open function.

Output Parameter name Description

productName Product name of the specified module. This product name can be used in open.

errorOut See Description of SD1 Error IDs.

getChassis.

getSlot.

Table 52 Output parameters for getProductName

Syntax Table 53 API syntax for getProductName

Language Syntax

C int SD_Module_getProductNameByIndex(int index, char *productName);

int SD_Module_getProductNameBySlot(int chassis, int slot, char* productName);

char* SD_Module_getProductName(int moduleId, char * productName);

C++ std::string SD_Module::getProductName();

std::string SD_Module::getProductName(int index);

std::string SD_Module::getProductName(int chassis, int slot);

.NET, MATLAB string SD_Module::getProductName(int index);

string SD_Module::getProductName(int chassis, int slot);

string SD_Module::getProductName();

Python SD_Module.getProductNameByIndex(index)

SD_Module.getProductNameBySlot(chassis, slot)

SD_Module.getProductName()

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NOTE

5.4.5: getSerialNumber

Description Returns the serial number of the specified module.

(Specific to object-oriented programming languages only) getSerialNumber
is a static function. Object-oriented languages also have a non-static
function without arguments.

Parameters Table 54 Input parameters for getSerialNumber

Input Parameter name Description

index Module index. It must be in the range (0 to nModules-1), where nModules is returned by moduleCount.

chassis Chassis number where the module is located. The chassis number can be found in Keysight SD1 software or can be retrieved with

slot Slot number in the chassis where the module is located. The slot number can be found on the chassis or can be retrieved with

moduleId Module identifier returned by open function.

Output Parameter name Description

serialNumber Serial number of the specified module. This serial number can be used in open.

errorOut See Description of SD1 Error IDs.

getChassis.

getSlot.

Table 55 Output parameters for getSerialNumber

Syntax Table 56 API syntax for getSerialNumber

Language Syntax

C int SD_Module_getSerialNumberByIndex(int index, char *serialNumber);

int SD_Module_getSerialNumberBySlot(int chassis, int slot, char *serialNumber);

char* SD_Module_getSerialNumber(int moduleId, char* serialNumber);

C++ std::string SD_Module::getSerialNumber(int index);

std::string SD_Module::getSerialNumber();

std::string SD_Module::getSerialNumber(int chassis, int slot);

.NET, MATLAB string SD_Module::getSerialNumber(int index);

string SD_Module::getSerialNumber(int chassis, int slot);

string SD_Module::getSerialNumber();

Python SD_Module.getSerialNumberByIndex(index)

SD_Module.getSerialNumberBySlot(chassis, slot)

SD_Module.getSerialNumber()

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NOTE

5.4.6: getChassis

Description Returns the chassis number of where a module is located.

(Specific to object-oriented programming languages only) getChassis is a
static function. Object-oriented languages also have a non-static function
without arguments.

Parameters Table 57 Input parameters for getChassis

Input Parameter name Description

moduleID Module identifier, returned by open.

index Module index. It must be in the range (0 to nModules-1), where nModules is returned by moduleCount.

Table 58 Output parameters for getChassis

Output Parameter name Description

chassis Chassis number of where a module is located. Negative numbers indicate an error. See Description of SD1 Error IDs.

errorOut See Description of SD1 Error IDs.

Syntax Table 59 API syntax for getChassis

Language Syntax

C int SD_Module_getChassisByIndex(int index);

int SD_Module_getChassis(int moduleID);

C++ int SD_Module::getChassis(int index);

int SD_Module::getChassis();

.NET, MATLAB int SD_Module::getChassis(int index);

int SD_Module::getChassis();

Python SD_Module.getChassis()

SD_Module.getChassisByIndex(index)

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NOTE

5.4.7: getSlot

Description Returns the slot number of where a module is located in the chassis.

(Specific to object-oriented programming languages only) getSlot is a static
function.

Parameters Table 60 Input parameters for getSlot

Input Parameter name Description

moduleID Module identifier, returned by open.

index Module index. It must be in the range (0 to nModules-1), where nModules is returned by moduleCount.

Table 61 Output parameters for getSlot

Output Parameter name Description

slot Slot number of where the module is located in the chassis. Negative numbers indicate an error. See Description of SD1 Error IDs.

errorOut See Description of SD1 Error IDs.

Syntax Table 62 API syntax for getSlot

Language Syntax

C int SD_Module_getSlotByIndex(int index);

int SD_Module_getSlot(int moduleID);

C++ static int SD_Module::getSlot(int index);

int SD_Module::getSlot();

.NET, MATLAB static int SD_Module::getSlot(int index);

int SD_Module::getSlot();

Python SD_Module.getSlot()

SD_Module.getSlotByIndex(index)

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NOTE

5.4.8: PXItriggerWrite

Description Sets the digital value of a PXI trigger in the PXI backplane.

This function is only available in PXI/PXI Express form factors.

Parameters Table 63 Input parameters for PXItriggerWrite

Input Parameter name Description

moduleID (Non-object-oriented languages only) Module identifier, returned by open.

nPXItrigger

trigger

value Digital value with negated logic: 0 (ON) or 1 (OFF)

Output Parameter name Description

errorOut See Description of SD1 Error IDs.

PXI trigger line number. Input Values 0 to 7.

Table 64 Output parameters for PXItriggerWrite

Syntax Table 65 API syntax for PXItriggerWrite

Language Syntax

C int SD_Module_PXItriggerWrite(int moduleID, int nPXItrigger, int value);

C++ int SD_Module::PXItriggerWrite(int nPXItrigger, int value);

.NET, MATLAB int SD_Module::PXItriggerWrite(int nPXItrigger, int value);

Python SD_Module.PXItriggerWrite(trigger, value)

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5.4.9: PXItriggerRead

NOTE

Description Reads the digital value of a PXI trigger in the PXI backplane.

This function is only available in PXI/PXI Express form factors.

Parameters Table 66 Input parameters for PXItriggerRead

Input Parameter name Description

moduleID (Non-object-oriented languages only) Module identifier, returned by open.

Using Keysight SD1 API Command Reference 5

nPXItrigger

trigger

Output Parameter name Description

value Digital value with negated logic: 0 (ON) or 1 (OFF). Negative numbers indicate an error. See Description of SD1 Error IDs.

errorOut See Description of SD1 Error IDs.

PXI trigger line number. Input Values 0 to 7.

Table 67 Output parameters for PXItriggerRead

Syntax Table 68 API syntax for PXItriggerRead

Language Syntax

C int SD_Module_PXItriggerRead(int moduleID, int nPXItrigger);

C++ int SD_Module::PXItriggerRead(int nPXItrigger);

.NET, MATLAB int SD_Module::PXItriggerRead(int nPXItrigger);

Python SD_Module.PXItriggerRead(trigger)

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5.4.10: getFirmwareVersion

Description Returns the Firmware Version of the module.

Parameters Table 69 Input parameters for getFirmwareVersion

Input Parameter name Description

moduleID Module identifier, returned by open.

Table 70 Output parameters for getFirmwareVersion

Output Parameter name Description

firmwareVersion Firmware Version of the specified module.

errorOut See Description of SD1 Error IDs.

Syntax Table 71 API syntax for getFirmwareVersion

Language Syntax

C int SD_Module_getFirmwareVersion(int moduleID, char *firmwareVersion);

C++ std::string SD_Module::getFirmwareVersion();

.NET, MATLAB String SD_Module::getFirmwareVersion();

Python SD_Module.getFirmwareVersion()

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5.4.11: getHardwareVersion

Description Returns the hardware version of the module.

Parameters Table 72 Input parameters for getHardwareVersion

Input Parameter name Description

moduleID Module identifier, returned by open.

Table 73 Output parameters for getHardwareVersion

Output Parameter name Description

hardwareVersion Hardware Version of the specified module.

errorOut See Description of SD1 Error IDs.

Syntax Table 74 API syntax for getHardwareVersion

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Language Syntax

C int SD_Module_getHardwareVersion(int moduleID, char *hardwareVersion);

C++ std::string SD_Module::getHardwareVersion();

.NET, MATLAB String SD_Module::getHardwareVersion();

Python SD_Module.getHardwareVersion()

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5.4.12: getOptions

Description Returns all the available option for selected card. It has two uses:

1 normal—the user calls getOptions(“<OptionKey>”). This would return the values listed below:

• the value of desired option (if it exists).

• “NONE”, if the value doesn’t exist.

• NULL pointer, if there is not enough space to write all the data or you are trying to access an

unopened module.

2 help - the user calls getOptions(“?”). This would return the values listed below:

• list of all the possible keys (available or not) the function can be queried.

• NULL pointer, if there is not enough space to write all the data.

Parameters Table 75 Input parameters for getOptions

Input Parameter name Description

moduleID Module identifier, returned by open.

optionKey Possible values are:

varToFill empty char array of options.

vartoFillSize size of the char array.

objectType type of module. Refer to getType.

Output Parameter name Description

options The options available for the selected card.

errorOut See Description of SD1 Error IDs.

• “model”

• “channels”

• “clock”

• “memory”

• “modulation”

• “dual_modulation”

• “up_modulation”

• “down_modulation”

• “onboard_dc”

• “streaming”

• “fpga”

• “fpga_programmable”

• “hvi”

Table 76 Output parameters for getOptions

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