The HMMC-5025 was designed as a generic wide band distributed amplier, covering the
frequency span 2-50 GHz. It consists of seven stages. Each stage is made up of two
cascaded FETs with gate peripheries of 48 μm per FET. Both input and output ports were
designed to provide 50 Ohm terminations. Bonding pads are provided in the layout to allow
amplier operation at frequencies lower than 2 GHz by means of external circuit components.
The amplier is biased with a single positive drain supply (VDD) and a single negative gate
supply (VG1). A second gate connection is provided for external gain control applications.
Chip Size:
1720 × 920 μm (67.7 × 36.2 mils)
Chip Size Tolerance:
±10 μm (±0.4 mils)
Chip Thickness:
127 ± 15 μm (5 ±0.6 mils)
Pad Dimensions:
80 × 80 μm (3.2 × 3.2 mils)
Absolute Maximum Ratings
1
SymbolParameters/conditionsMin.Max.Units
V
DD
I
DD
V
G1
V
G2
Positive drain voltage7.0volts
Total drain current170mA
First gate voltage–3.50volts
Second gate voltage–3.0+3.0volts
PDC powerDC power dissipation1.2watts
P
T
T
T
T
in
ch
case
stg
max
CW input power20dBm
Operating channel temperature150°C
Operating case temperature–55°C
Storage temperature–65165°C
Maximum assembly temperature (for 60 seconds maximum)300°C
1. Operation in excess of any one of these conditions may result in permanent damage to this
device. TA = 25 °C except for Tch, T
The HMMC-5025 traveling wave amplier is designed for use as a general purpose
wideband power stage in communication systems, and microwave instrumentation,
and optical systems. It is ideally suited for broadband applications requiring a at gain
response and excellent port matches over a 2 to 50 GHz frequency range. Dynamic gain
control and lowfrequency ex tension capabilities are designed into these devices.
It is characteristic of traveling wave ampliers that S22 tends to 0 dB and greater out
of band. This is the design trade-off for the broadband performance of TWAs. As a
consequence, TWAs are not necessarily uncondtionally stable out of band. This means
that if a TWA is followed by a reective low-pass lter, oscillations can occur. This
phenomenon is exacerbated by low temperature where the gain is higher. More data will
follow on individual devices.
Biasing and Operation
The recommended bias conditions for best performance for the HMMC- 5025 are VDD =
5.0 V, IDD = 75 mA. To achieve these drain current levels, VG1 is typically biased between
–0.2 V and –0.6 V. No other bias supplies or connections to the device are required
for 2 to 50 GHz operation. The gate voltage (VG1) should be applied prior to the drain
voltage (VDD) during power up and removed after the drain voltage during power down.
The HMMC-5025 is a DC coupled amplier. External coupling capacitors are needed on
RFIN and RF
the lowest operating frequency.
The auxiliary gate and drain contacts are provided when performance below 1 GHz is
required. Connect external capacitors to ground to maintain input and output VSWR at
low frequencies (see Additional References). Do not apply bias to these pads.
The second gate (VG2) can be used to obtain 30 dB (typical) dynamic gain control. For
normal operation, no external bias is required on this contact.
ports. The drain bias pad is connected to RF and must be decoupled to
OUT
Assembly Techniques
GaAs MMICs are ESD sensitive. ESD preventive measures must be employed in all
aspects of storage, handling, and assembly.
MMIC ESD precautions, handling considerations, die attach and bonding methods are
critical factors in successful GaAs MMIC performance and reliability.
Keysite Technologies application note, GaAs MMIC ESD, Die Attach and Bonding
Guidelines (literature number 5991- 3484EN) provides basic information on these
subjects.
Additional References:
Keysite Technologies application note, GaAs MMIC TWA Users Guide
(literature number 5991-3545EN).
Figure 6. Typical Small-signal gain vs. TemperatureFigure 7. Typical Gain vs. Second gate control voltage
(VDD = 5.0 V, V
G1
-0.66 V)
=
20
10
21
0
-10
-20
-30
2 6 10 14 18 22 26 30 34 38 42 46 50
Frequency (GHz
VG2
(V)
+2.0
-1.0
-1.5
-2.0
-2.5
-3.0
IDD
(mA)
75
59
47
34
24
16
(VDD = 5.0 V, I
18
(Q) = 75 mA)
DD
16
14
12
10
Output power (dBm)
8
6
4
2 6 10 14 18 22 26 30 34 38 42 46 50
Frequency (GHz)
Figure 8. Typical 1 dB Gain compression and Saturated
output power vs. Frequency
6
5
4
3
Noise figure (dB)
2
1
2 4 6 8 10 12 14 16 18 20 22 24 26.5
Nominal Bias:
(V
= 5.0 V, IDD = 75 mA)
DD
Optimal NF Bias:
(V
= 2.25 V, IDD = 26 mA)
DD
Frequency (GHz)
Figure 10. Typical Noise gure performance vs. Frequency
P(sat)
P(-1 dB)
13
11
9
7
5
Associated gain (dB)
(VDD = 5.0 V, I
-10
-15
-20
-25
-30
-35
-40
Harmonics (dBc)
-45
-50
-55
-60
2 3 4 5 6 7 8 9 10 11 12 13 14
DD
2nd Harm.
3rd Harm.
(Q) = 75 mA)
Fundamental frequency, ƒo (GHz)
Figure 9. Typical Second and Third harmonics vs.
Fundamental frequency at P
= 10 dBm
out
Notes
All data measured on individual devices mounted in a 50 GHz test
package TA = 25 °C (except where noted).
This data sheet contains a variety of typical and guaranteed
performance data. The information supplied should not be
interpreted as a complete list of circuit specications. Customers
considering the use of this, or other TCA GaAs ICs, for their
design should obtain the current production specications
from Keysight Technologies, Inc.. In this data sheet the term
typical refers to the 50th percentile performance. For additional
information and support email: [email protected].
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