75000 Series C
User & SCPI Programming Manual
Keysight E1459A / Z2404A 64-Channel Isolated Input Interrupt Module
Notices
© Keysight Technologies, Inc. 1991-2019
No part of this manual may be reproduced in any form or by any means
(including electronic storage and retrieval
or translation into a foreign language)
without prior agreement and written consent from Keysight Technologies, Inc. as
governed by United States and international copyright laws.
Manual Part Number
E1459-90001
Edition
Fourth Edition, October 2019
Published by
Keysight Technologies, Inc.
900 S. Taft Ave.
Loveland, CO 80537 USA
Sales and Technical Support
To contact Keysight for sales and technical support, refer to the support links on
the following Keysight websites:
www.keysight.com/find/E1459A
(product-specific information and support, software and documentation
updates)
www.keysight.com/find/assist (world-
wide contact information for repair and
service)
Declaration of Conformity
Declarations of Conformity for this product and for other Keysight products may
be downloaded from the Web. Go to
http://keysight.com/go/conformity and
click on “Declarations of Conformity.” You
can then search by product number to
find the latest Declaration of Conformity.
Technology Licenses
The hardware and/or software described
in this document are furnished under a
license and may be used or copied only in
accordance with the terms of such
license.
Warranty
THE MATERIAL CONTAINED IN THIS
DOCUMENT IS PROVIDED “AS IS,” AND
IS SUBJECT TO BEING CHANGED,
WITHOUT NOTICE, IN FUTURE EDITIONS. FURTHER, TO THE MAXIMUM
EXTENT PERMITTED BY APPLICABLE
LAW, KEYSIGHT DISCLAIMS ALL WARRANTIES, EITHER EXPRESS OR IMPLIED,
WITH REGARD TO THIS MANUAL AND
ANY INFORMATION CONTAINED
HEREIN, INCLUDING BUT NOT LIMITED
TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. KEYSIGHT
SHALL NOT BE LIABLE FOR ERRORS OR
FOR INCIDENTAL OR CONSEQUENTIAL
DAMAGES IN CONNECTION WITH THE
FURNISHING, USE, OR PERFORMANCE
OF THIS DOCUMENT OR OF ANY INFORMATION CONTAINED HEREIN. SHOULD
KEYSIGHT AND THE USER HAVE A SEPARATE WRITTEN AGREEMENT WITH
WARRANTY TERMS COVERING THE
MATERIAL IN THIS DOCUMENT THAT
CONFLICT WITH THESE TERMS, THE
WARRANTY TERMS IN THE SEPARATE
AGREEMENT SHALL CONTROL.
Keysight Technologies does not warrant
third-party system-level (combination of
chassis, controllers, modules, etc.) performance, safety, or regulatory compliance unless specifically stated.
DFARS/Restricted Rights
Notices
If software is for use in the performance
of a U.S. Government prime contract or
subcontract, Software is delivered and
licensed as “Commercial computer software” as defined in DFAR 252.227-7014
(June 1995), or as a “commercial item” as
defined in FAR 2.101(a) or as “Restricted
computer software” as defined in FAR
52.227-19 (June 1987) or any equivalent
agency regulation or contract clause.
Use, duplication or disclosure of Software
is subject to Keysight Technologies’ standard commercial license terms, and nonDOD Departments and Agencies of the
U.S. Government will receive no greater
than Restricted Rights as defined in FAR
52.227-19(c)(1-2) (June 1987). U.S. Government users will receive no greater
than Limited Rights as defined in FAR
52.227-14 (June 1987) or DFAR 252.2277015 (b)(2) (November 1995), as applicable in any technical data.
Safety Information
The following general safety precautions must be observed during all
phases of operation of this instrument.
Failure to comply with these precautions or with specific warnings or operating instructions in the product
manuals violates safety standards of
design, manufacture, and intended use
of the instrument. Keysight Technologies assumes no liability for the customer's failure to comply with these
requirements.
General
Do not use this product in any manner not
specified by the manufacturer. The protective features of this product must not be
impaired if it is used in a manner specified in
the operation instructions.
Before Applying Power
Verify that all safety precautions are taken.
Make all connections to the unit before
applying power. Note the external markings
described under “Safety Symbols”.
Ground the Instrument
Keysight chassis’ are provided with a
grounding-type power plug. The
instrument chassis and cover must be
connected to an electrical ground to
minimize shock hazard. The ground pin
must be firmly connected to an electrical ground (safety ground) terminal at
the power outlet. Any interruption of
the protective (grounding) conductor
or disconnection of the protective
earth terminal will cause a potential
shock hazard that could result in personal injury.
Do Not Operate in an Explosive
Atmosphere
Do not operate the module/chassis in
the presence of flammable gases or
fumes.
Do Not Operate Near Flammable
Liquids
Do not operate the module/chassis in
the presence of flammable liquids or
near containers of such liquids.
Cleaning
Clean the outside of the Keysight module/chassis with a soft, lint-free,
slightly dampened cloth. Do not use
detergent or chemical solvents.
Do Not Remove Instrument Cover
Only qualified, service-trained personnel who are aware of the hazards
involved should remove instrument
covers. Always disconnect the power
cable and any external circuits before
removing the instrument cover.
Keep away from live circuits
Operating personnel must not remove
equipment covers or shields. Procedures involving the removal of covers
and shields are for use by servicetrained personnel only. Under certain
conditions, dangerous voltages may
exist even with the equipment
switched off. To avoid dangerous electrical shock, DO NOT perform procedures involving cover or shield removal
unless you are qualified to do so.
DO NOT operate damaged
equipment
Whenever it is possible that the safety
protection features built into this product have been impaired, either through
physical damage, excessive moisture,
or any other reason, REMOVE POWER
and do not use the product until safe
operation can be verified by servicetrained personnel. If necessary, return
the product to a Keysight Technologies
Sales and Service Office for service and
repair to ensure the safety features are
maintained.
DO NOT block the primary
disconnect
The primary disconnect device is the
appliance connector/power cord when
a chassis used by itself, but when
installed into a rack or system the disconnect may be impaired and must be
considered part of the installation.
Do Not Modify the Instrument
Do not install substitute parts or perform any unauthorized modification to
the product. Return the product to a
Keysight Sales and Service Office to
ensure that safety features are maintained.
In Case of Damage
Instruments that appear damaged or
defective should be made inoperative
and secured against unintended operation until they can be repaired by
qualified service personnel
Do NOT block vents and fan exhaust:
To ensure adequate cooling and ventilation, leave a gap of at least 50mm
(2") around vent holes on both sides of
the chassis.
Do NOT operate with empty slots: To
ensure proper cooling and avoid damaging equipment, fill each empty slot
with an AXIe filler panel module.
Do NOT stack free-standing chassis:
Stacked chassis should be rackmounted.
All modules are grounded through the
chassis: During installation, tighten
each module's retaining screws to
secure the module to the chassis and
to make the ground connection.
Operator is responsible to maintain
safe operating conditions. To ensure
safe operating conditions, modules
should not be operated beyond the full
temperature range specified in the
Environmental and physical specification. Exceeding safe operating conditions can result in shorter lifespan,
improper module performance and
user safety issues. When the modules
are in use and operation within the
specified full temperature range is not
maintained, module surface temperatures may exceed safe handling conditions which can cause discomfort or
burns if touched. In the event of a
module exceeding the full temperature
range, always allow the module to cool
before touching or removing modules
from the chassis.
iv
Safety Symbols
A CAUTION denotes a hazard. It
calls attention to an operating procedure or practice, that, if not correctly performed or adhered to
could result in damage to the
product or loss of important data.
Do not proceed beyond a CAUTION
notice until the indicated conditions are fully understood and met.
A WARNING denotes a hazard. It
calls attention to an operating procedure or practice, that, if not correctly performed or adhered to,
could result in personal injury or
death. Do not proceed beyond a
WARNING notice until the indicated conditions are fully understood and met.
Products display the following symbols:
Warning, risk of electric
shock
Refer to manual for additional safety information.
Earth Ground.
Chassis Ground.
Alternating Current (AC).
Direct Current (DC)
v
vi
Contents
1 Installing and Configuring the E1459A
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Level Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Debounce Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Programmable Debounce Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Edge Detection Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Front Panel Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt Driven or Polled Mode Operations . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt Parsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configuring for Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting the Logical Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting the Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting Input Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Setting the Reset Time on the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . 22
Connecting User Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Installing the Keysight E1459A in a VXIbus Mainframe . . . . . . . . . . . . . . . . 25
Terminal Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Wiring Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Wiring a Terminal Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 Using the Keysight E1459A Module
Power-on / Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Example 1: Reset, Self Test, and Module ID. . . . . . . . . . . . . . . . . . . . . . . . . 30
Digital Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Example 2: Digital Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Edge Detected Event Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Polling the Port Summary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Polling the Status Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SRQ Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Example 3: Edge Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3 Keysight E1459A SCPI Command Reference
Common Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SCPI Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Command Separator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Keysight E1459/Z2404B User and SCPI Programming Guide vii
Abbreviated Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Implied Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Linking Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DIAGnostic:SYSReset Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DIAGnostic:SYSReset[:STATe]? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DIAGnostic:SYSReset:ENABle <state> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DIAGnostic:SYSReset:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DISPlay:MONitor Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DISPlay:MONitor:PORT <port> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DISPlay:MONitor:PORT? [MINimum | MAXimum | DEFault]. . . . . . . . . . . . . 47
DISPlay:MONitor:PORT:AUTO <state> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DISPlay:MONitor:PORT:AUTO? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DISPlay:MONitor[:STATe] <state> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
INPutn:CLOCk[:SOURce] <source>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
INPutn:CLOCk[:SOURce]?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
INPutn:DEBounce:TIME <time> | MINimum | MAXimum | DEFault . . . . . . . 51
INPutn:DEBounce:TIME? [MINimum | MAXimum | DEFault] . . . . . . . . . . . . 52
MEASure Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MEASure:DIGital:DATAn[:type] [:VALue]? . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MEASure:DIGital:DATAn[:type]:BITm?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
MEMory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MEMory:DELete:MACRo <name> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SENSe Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
[SENSe:]EVENt:PORTn:DAVailable? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
[SENSe:]EVENt:PORTn:DAVailable:ENABle <state>. . . . . . . . . . . . . . . . . . . 57
[SENSe:]EVENt:PORTn:DAVailable:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . 58
[SENSe:]EVENt:PORTn:EDGE? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
[SENSe:]EVENt:PORTn:EDGE:ENABle <state>. . . . . . . . . . . . . . . . . . . . . . . 59
[SENSe:]EVENt:PORTn:EDGE:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
[SENSe:]EVENt:PORTn:NEDGe? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
[SENSe:]EVENt:PORTn:NEDGe:ENABle <mask> . . . . . . . . . . . . . . . . . . . . . 60
[SENSe:]EVENt:PORTn:NEDGe:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
[SENSe:]EVENt:PORTn:PEDGe? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
[SENSe:]EVENt:PORTn:PEDGe:ENABle <mask> . . . . . . . . . . . . . . . . . . . . . 62
[SENSe:]EVENt:PORTn:PEDGe:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
[SENSe:]EVENt:PSUMmary:DAVailable? . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
viii Keysight E1459/Z2404B User and SCPI Programming Guide
[SENSe:]EVENt:PSUMmary:EDGE? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
STATus Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STATus:OPERation:CONDition? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
STATus:OPERation:ENABle <mask> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
STATus:OPERation:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
STATus:OPERation[:EVENt]?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
STATus:OPERation:PSUMmary:CONDition?. . . . . . . . . . . . . . . . . . . . . . . . . 68
STATus:OPERation:PSUMmary:ENABle <mask> . . . . . . . . . . . . . . . . . . . . . 69
STATus:OPERation:PSUMmary:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
STATus:OPERation:PSUMmary[:EVENt]? . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
STATus:PRESet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
STATus:QUEStionable:CONDition?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
STATus:QUEStionable:ENABle <mask> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
STATus:QUEStionable:ENABle? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
STATus:QUEStionable[:EVENt]? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SYSTem Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SYSTem:CDEScription? <number>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SYSTem:CTYPe? <number> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SYSTem:ERRor? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SYSTem:VERSion? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IEEE 488.2 Common Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Command Quick Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A Keysight E1459A Specifications
B Keysight E1459A Register Definitions
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Addressing the Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Register Access with Logical Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Register Access with Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Device Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Edge Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Data Available Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Watchdog Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Command Register Port 0/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Channel Data Register Port 0/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Keysight E1459/Z2404B User and SCPI Programming Guide ix
Positive Edge Detect Register Port 0/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Negative Edge Detect Register Port 0/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Positive Mask Register Port 0/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Debounce Clock Register Port 0 and Port1/ Port 2 and Port 3 . . . . . . . . . . 96
Command Register Port 1/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Channel Data Register Port 1/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Positive Edge Detect Register Port 1/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Negative Edge Detect Register Port 1/3 . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Positive Mask Register Port 1/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Negative Mask Register Port 1/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Debounce Clock Register Port 0 and Port 1/ Port 2 and Port 3 . . . . . . . . 101
Power On/Reset Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Output and Edge Detection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
C Error Messages
x Keysight E1459/Z2404B User and SCPI Programming Guide
E1459A/Z2404B User and SCPI Programming Guide
1 Installing and Configuring the
E1459A
The Keysight E1459A 64-Channel Isolated Digital Input/Interrupt module
(formerly known as the Z2404B
configured as four 16-bit ports. The module is used for sensing signals and
detecting edge changes on digital inputs. The module is a C-Size VXIbus
register-based product that operates in a C-Size VXIbus mainframe.
Each isolated channel can withstand up to 115 Vac RMS or 115 Vdc difference in
ground potential between channels. The input threshold for each channel is
selectable with a jumper to allow for inputs with high logic levels from 5 to 48
volts. Each channel can be individually masked to generate an interrupt on a
positive and/or negative edge transition. Channel inputs are also "debounced" to
help prevent erroneous transition detection on noisy signals. Two programmable
clock sources control the debounce circuitry (one for ports 0 and 1, one for ports
2 and 3).
Functional Description
The Keysight E1459A simultaneously monitors each channel for the occurrence
of transitions, (i.e., edge events), or for level sensing signals which meet
preprogrammed parameters for magnitude and duty. Each channel is electrically
isolated from all other channels, power, ground, and other current paths within
the limits of specification. Each channel may be independently programmed to
sense only positive transitions, only negative transitions, or transitions of either
polarity.
1
) provides 64 isolated digital input channels
Figure 1 shows the functional block diagram for the module.
1 The Keysight E1459A and Z2404B are functionally identical. The Keysight E1459A is provided with a
downloadable SCPI driver and a VXIplug&play driver; the Z2404B was not provided with a language driver.
11
Installing and Configuring the E1459A Functional Description
To VXIbu s
Transceivers
Figure 1-1 Keysight E1459A 64-Channel Isolated Digital Input/Interrupt Block Diagram
12 Keysight E1459A/Z2404B User and SCPI Programming Guide
Functional Description Installing and Configuring the E1459A
The Keysight E1459A can be programmed to monitor channel occurrences either
internally with a 1.0 MHz sample clock, or externally, with a sourced capture
clock. Using either clocking technique, data channels may function as edge
detect inputs and/or data capture inputs.
Events at any channel may occur simultaneously or in overlap with events on any
other channel. Figure 2 is a block diagram of the hardware interrupt resolver
circuit. User software algorithms are also necessary to resolve issues of overlap
and to determine the occurring sequence of events.
Figure 1-2 Resolver Block Diagram
Watchdog Timer
The Keysight E1459A provides a programmable timer facility which, in the event
of time-out, will generate a "system wide" reset to all other card-cage modules.
This timer may be disabled by the SCPI command DIAG:SYSR:ENAB OFF.
Input Level Selection
Each channel is capable of operation over an input range from 2.0 through 60.0
Vdc. Input voltages are grouped into voltage ranges which are selected via a
series of jumpers on the module. These jumpers are described in more detail
later.
Input Isolation
Each channel is optically coupled and electrically isolated from all other
channels and current paths. Isolated channel inputs are polarized and require
that the user observe input signal polarity when connections are made.
Keysight E1459A/Z2404B User and SCPI Programming Guide 13
Installing and Configuring the E1459A Functional Description
Input Debounce Processing
Each channel is debounced by a digital circuit specific to this function. Two
programmable clock sources establish reference parameters which determine
the debounce criteria for validating inputs. Channels are not independently
programmed for debounce period, but are instead grouped together in blocks of
32 channels per clock source. Channels 00-31 (Ports 0 and 1) are collectively
programmed via one clock source and channels 32-63 (Ports 2 and 3) are
programmed via a second clock source.
Programmable Debounce Parameters
Debounce circuits require that a channel input remain in a stable state for 4 to
4.5 periods of the programmable clock before a channel transition is declared.
The debounce clocks may be programmed for frequencies ranging from 250 KHz
down to 466 Hz. The 4 to 4.5 clock period requirements of the debouncers
translate into debounce periods which range from 16 S minimum to 9600
seconds (2.67 hours) maximum.
The debounce circuits can add considerable latency in the signal path and an
additional delay occurs within the Register FPGA. Normally the signals pass
though without significant delay. However, during a VXIbus transaction to this
port, the input signals are momentarily captured by a latch and are held for the
duration of the bus transaction plus 500 nS. This prevents data events from being
lost due to potential timing conflicts with VXIbus transactions. The data signals
are then synchronized with the system clock and synchronously captured in
either the data register, the positive edge event register, or the negative edge
event register. This can potentially add another 500 nS depending upon timing
circumstances.
Thus the input data is delayed by the debounce circuits, possibly by the input
latches (equal to bus transaction time plus 500 nS), and a synchronizing delay of
500 nS. The external clocks (front panel external trigger inputs) are also delayed
but by no more than 500 nS. Therefore, an external capture clock concurrent with
a data event will not capture the event unless consideration is given for data
latency.
The user MUST ensure, based upon the programmed debounce
period and internal delays, that data to be captured has
propagated the debouncers and is fully setup prior to the
assertion of the externally generated capture clock.
The module has two primary modes of operation: the module can interrupt your
software when an event occurs or your software can periodically poll the module
to determine if an event has occurred. If the channel data registers are serviced
via a "polled mode" method (which is not keyed to the posting of the "marker
14 Keysight E1459A/Z2404B User and SCPI Programming Guide
Functional Description Installing and Configuring the E1459A
bits" or the occurrence of an interrupt), no timing relationship will necessarily
exist with the debounced event. As a result, a small window of uncertainty exists
between input latch timing and debounce circuit timing.
Input Edge Detection
Each channel may be programmed to sense the occurrence of a qualified edge
transition of either polarity, or both concurrently. All channels are preprocessed
via the debounce circuits before presentation to the edge detect logic. Edge
detection is performed (by sampling methods) within each of the four ports, in
groups of 16 channels per port. If enabled, each port will post an "Edge Interrupt
Marker" to the control logic circuitry on the occurrence of a qualified edge event
for any active channel within its channel group. (The static state of these markers
may be tested via the "Edge Interrupt Status Register" These markers are also
accessible at the front panel.)
Edge Detect Markers are cleared by a read of the register causing
the marker to be posted. Since there is no high-level method of
determining whether a positive or negative edge event is
generating the marker, both edge detect registers (positive and
negative) within a channel group, MUST be read during the
service interval to identify ALL edge events which may have
potentially occurred.
Each marker bit is forced inactive for a two clock (16 MHz) periods each time
either edge detect register is read. (The edge detect register is then cleared at
the end of the cycle.) If the register that is not being read is inactive and remains
inactive, the marker will continue to remain inactive. If the register that is not
read is active or becomes active, the marker is again posted to the "control"
logic. The control logic detects this event and stores this occurrence in a flip-flop
which marks the pending need for service. If this marking register, (now active),
is then read and ultimately cleared, the marker will become inactive and will
remain inactive until the subsequent occurrence of another qualified edge event.
The control logic detects this "cleared marker condition" and consequently clears
the pending service request flip-flop.
External edge events which occur concurrently with a register read/clear cycle
are queued and post-processed on completion of the cycle.
Edge Detection Examples
Figure 3 demonstrates a typical example. A channel that has been programmed
to detect both positive and negative edge transitions posts a marker at the
occurrence of a positive edge. Before user software can service this interrupt, a
Keysight E1459A/Z2404B User and SCPI Programming Guide 15
Installing and Configuring the E1459A Functional Description
negative transition occurs and is detected. Because both are detected and the
events are marked, user software first reads the positive edge detect register and
then the negative edge detect register.
Figure 1-3 Positive and Negative Edge Transitions
In Figure 4, a channel that has been programmed for data capture posts a
marker on the occurrence of an external capture clock. During the subsequent
data register read cycle, another data capture clock occurs to create a pending
DAV (Data AVailable) situation. The second DAV is retained (and valid) until a
subsequent read of the corresponding data register.
Figure 1-4 DAV Timing
16 Keysight E1459A/Z2404B User and SCPI Programming Guide
Functional Description Installing and Configuring the E1459A
Input Data Capture
The state of any channel, within any channel group, may be captured for
subsequent processing (as data) by an externally sourced capture clock
(XTRIG0N - XTRIG3N, the external trigger inputs for each port). Data channels
may be interspersed among all 64 channel inputs, but the user is cautioned to
ensure that all setup criteria and clock sources coincide with requirements for
synchronization. (Each channel group shares a common capture clock which may
not necessarily be synchronous with an external capture clock of some other
channel group.)
If enabled, each register FPGA will post a "Data Available Marker" to the control
FPGA on the occurrence of a corresponding capture clock. Data Available
Markers are cleared by a read of the corresponding "Channel Data Register."
(The static state of these markers may be tested via the "Data Available
Register.") Capture clocks which occur concurrently with a "register read/marker
clear" cycle, are queued and post- processed on completion of the present cycle.
In that event, the marker bit is forced inactive for a two clock (16 MHz) period
before again being posted to the control FPGA.
In the "Data Capture Mode", the Keysight E1459A may be programmed to
generate an interrupt on the occurrence of an external capture clock, or an
internal 1.0 MHz sample clock may be selected to allow the state of the data
channels to be tested in the absence of a capture clock. Capture clock selection
(internal/external) is controlled by bit 1 of the Command Register Word.
A potential hazard exists if software were to improperly program
the Keysight E1459A to post data-capture IRQ's with the
internally selected 1.0 MHz clock source. In this situation, a DAV
interrupt would be posted each microsecond (if software were
able to service at that rate), and would cause software to
continuously vector to interrupt service upon each "return from
service." Therefore, the Keysight E1459A should never be
programmed to generate DAV interrupts with the internal clock
source selected.
In the Keysight E1459A the Data Ready Marker is guaranteed to
be cleared when the clock source is switched from internal to
external. Therefore, any capture clock which occurs within the
internal/external clock selection interval will not post a marker to
the control FPGA and will be lost.
Keysight E1459A/Z2404B User and SCPI Programming Guide 17
Installing and Configuring the E1459A Functional Description
Front Panel Markers
All "Data Available" and "Edge Detect" marker bits are physically available via the
Keysight E1459A front panel. These outputs are TTL/HC compatible and may be
used to trigger other system-wide events or to provide logging information for
statistical tracking or other performance analysis purposes.
Interrupt Driven or Polled Mode Operations
Interrupts may be programmatically disabled for both edge-detect and
data-capture events. All registers remain active and valid and may be serviced on
a polled mode basis.
Interrupt Parsing
Since the command module interrupt handler must service multiple,
concurrently-occurring interrupts, (including those which may be sharing the
same IRQ line), some method is necessary to ensure that only a single IRQ is
posted by the Keysight E1459A during each service interval.
Individual interrupts must be serviced by a commander on a one-for-one basis.
The Keysight E1459A accomplishes this by inhibiting the generation of a second
IRQ each time an IRQ is posted. THE INHIBIT CONDITION IS CLEARED BY THE
REMOVAL AND REASSERTION OF EITHER INTERRUPT ENABLE BIT, "DAV" OR
"EDGE DETECT." (Refer to Figure 2.)
For this one-for-one interrupt parsing, the Keysight E1459A REQUIRES that a
global interrupt enable, either DAV or Edge Detect, be disabled and reasserted
within the context of the interrupt service procedure. Normally, you would simply
shut off interrupts at the top of the service procedure, and would then re-enable
them before returning from service. This is the suggested usage, although this
specific sequence is not necessary for proper Keysight E1459A hardware
function.
18 Keysight E1459A/Z2404B User and SCPI Programming Guide
Configuring for Installation Installing and Configuring the E1459A
Configuring for Installation
Before installing the module you should verify that the following jumpers and
switches are set correctly.
– Logical Address dip switch
– Interrupt priority jumper positions
– Input threshold levels
– Reset time of the Watchdog Timer
SHOCK HAZARD. Only qualified, service-trained personnel
who are aware of the hazards involved should install,
configure, or remove the module. Disconnect all power
sources from the mainframe, the terminal module and
installed modules before installing or removing a module.
SHOCK HAZARD. When handling user wiring connected to
the terminal module, consider the highest voltage present
accessible on any terminal.
SHOCK HAZARD. Use wire with an insulation rating greater
than the highest voltage which will be present on the
terminal module. Do not touch any circuit element
connected to the terminal module if any other connector to
the terminal module is energized to more than 30 Vac RMS
or 60 Vdc.
MAXIMUM VOLTAGE. Maximum allowable voltage per channel for
this module is 60 Vdc. Up to 115 Vdc or 115 Vac RMS can be
applied from one channel to another or from any channel to
chassis.
STATIC-SENSITIVE DEVICE. Use anti-static procedures when
removing, configuring, and installing a module. The module is
susceptible to static discharges. Do not install the module
without its metal shield attached.
Keysight E1459A/Z2404B User and SCPI Programming Guide 19
Installing and Configuring the E1459A Configuring for Installation
Setting the Logical Address
Each module within the VXIbus mainframe must be set to a unique logical
address. The setting is controlled by an 8 pin dip switch. This allows for values
from 0 to 255. The factory setting of this switch is decimal 144. No two modules
in the same mainframe can have the same logical address. The location is shown
in Figure 5.
Setting the Interrupt Priority
At power on, after a SYSRESET, or after resetting the module via the control
register, all masks will be cleared, interrupts will be disabled, and internal
triggering will be enabled. With interrupts enabled, an interrupt will be
generated whenever an edge occurs on a channel that has been enabled
properly.
The interrupt priority jumper selects which priority level will be asserted. As
shipped from the factory, the interrupt priority jumper should be in position 1. In
most applications this should not be changed. When set to level X interrupts are
disabled. The interrupt priority jumpers are identified on the sheet metal shield. A
hole has been cut into the shield for access to the jumpers. Interrupts can also be
disabled using the Control Register.
The jumper locations are shown in Figure 5. To change the setting, move the
jumper or jumpers to the desired setting. If the card uses two 2-pin jumpers
versus a single 4 pin jumper, the jumpers must all be placed in the same row for
proper operation.
Consult your mainframe manual to be sure that backplane
jumpers are configured correctly. If you are using the Keysight
E1401B Mainframe these jumpers are automatically set when the
card is installed.
20 Keysight E1459A/Z2404B User and SCPI Programming Guide
Configuring for Installation Installing and Configuring the E1459A
Figure 1-5 Keysight E1459A Logical Address Switch and IRQ Jumper Locations
Setting Input Threshold Levels
The threshold levels for each channel can be set independently. A six pin plug
with a two pin shorting jack is provided for each channel. The channel can be
identified from the silk-screen on the board. Each jumper is labeled JXCC, where
Keysight E1459A/Z2404B User and SCPI Programming Guide 21
Installing and Configuring the E1459A Configuring for Installation
12 Volt
24 Volt
48 Volt
5 Volt Settings
(Factory Default)
Ch 0 Ch 2
Ch 3
Ch 5
Ch 6
Ch 8
Ch 63
Ch 60
Ch 57 Ch 59
Ch 62
JM203
JM202
PET Time
Jumpers
.
Ch
1
Ch 61
.
J indicates jumper, X is a number that can be ignored and CC indicates channel
number. The default factory setting is for 5 volts. Pin 1 can be identified by the
square pad on the bottom of the board.
Figure 1-6 Input Threshold Level Jumpers and Watchdog Reset Time Jumpers
Setting the Reset Time on the Watchdog Timer
There are 2 jumpers located on the PC board used to control the reset time of the
Watchdog Timer (see Figure 6). The reset time is the maximum allowed time
between accesses to keep the Watchdog from asserting SYSRESET. The
Watchdog timer is reset by reading the Watchdog Control/Status register; use
22 Keysight E1459A/Z2404B User and SCPI Programming Guide
the DIAG:SYSR:STAT? command (see Chapter 3).
The following table shows the effect of the jumpers on the reset time. An X
means that the jumper is in place and O indicates the jumper is removed. The
factory default setting is 1.2 second.
Jumper Reset Time
600 ms 150 ms 1.2 sec Not Allowed
JM202 O X O X
JM203 O O X X
Configuring for Installation Installing and Configuring the E1459A
Connecting User Inputs
The Keysight E1459A Isolated Digital Input/Interrupt module consists of a
component module and a terminal block. User inputs for each channel consists
of a low and a high connection for each channel. The inputs will only detect
signals of a positive polarity. A logical "1" will only be detected if the high
terminal is at a higher potential than the low terminal. It must also meet the drive
requirements for the voltage threshold selected.
For each block of 16 channels an additional active low input and two active low
outputs are available. The table below lists the signal names and the associated
channels.
Port Channels External Trigger Data Available Interrupt
0 0 through 15 XTRIG0N DAV0N INTR0N
1 16 through 31 XTRIG1N DAV1N INTR1N
2 32 through 47 XTRIG2N DAV2N INTR2N
3 48 through 63 XTRIG3N DAV3N INTR3N
Figure 7 shows the front panel terminals and pinouts for the module. The cover
to the terminal module is silk-screened to indicate the function of each screw
terminal.
Keysight E1459A/Z2404B User and SCPI Programming Guide 23
Installing and Configuring the E1459A Configuring for Installation
A B C
32 CH 00 HI CH 00 LO
31 CH 01 HI CH 02 LO CH 01 LO
30 CH 02 HI CH 03 LO
29 CH 04 HI CH 03 HI CH 04 LO
28 CH 05 HI CH 05 LO
27 CH 06 HI CH 06 LO
26 CH 07 HI CH 07 LO
25 CH 08 HI CH 08 LO
24 CH 09 HI CH 09 LO
23 CH 10 HI CH 11 LO CH 10 LO
22 CH 11 HI CH 12 LO
21 CH 13 HI CH 12 HI CH 13 LO
20 CH 14 HI CH 14 LO
19 CH 15 HI CH 15 LO
18 CH 16 HI CH 16 LO
17 CH 17 HI CH 17 LO
16 CH 18 HI CH 18 LO
15 CH 19 HI CH 19 LO
14 CH 20 HI CH 20 LO
13 CH 21 HI CH 21 LO
12 CH 22 HI CH 23 LO CH 22 LO
11 CH 23 HI CH 24 LO
10 CH 25 HI CH 24 HI CH 25 LO
9 CH 26 HI CH 26 LO
8 CH 27 HI CH 27 LO
7 CH 28 HI CH 28 LO
6 CH 29 HI CH 29 LO
5 CH 30 HI CH 30 LO
4 CH 31 HI CH 31 LO
3 CH 32 HI CH 32 LO
2 CH 33 HI CH 33 LO
1 CH 34 HI CH 34 LO
A B C
32 CH 35 HI CH 35 LO
31 CH 36 HI CH 37 LO CH 36 LO
30 CH 37 HI CH 38 LO
29 CH 38 HI CH 39 HI CH 39 LO
28 CH 40 HI CH 40 LO
27 CH 41 HI CH 42 LO CH 41 LO
26 CH 42 HI CH 43 LO
25 CH 43 HI CH 44 HI CH 44 LO
24 CH 45 HI CH 45 LO
23 CH 46 HI CH 46 LO
22 CH 47 HI CH 47 LO
21 CH 48 HI CH 48 LO
20 CH 49 HI CH 49 LO
19 CH 50 HI CH 50 LO
18 CH 51 HI CH 51 LO
17 CH 52 HI CH 52 LO
16 CH 53 HI CH 53 LO
15 CH 54 HI CH 55 LO CH 54 LO
14 CH 55 HI CH 56 LO
13 CH 56 HI CH 57 HI CH 57 LO
12 CH 58 HI CH 58 LO
11 CH 59 HI CH 59 LO
10 CH 60 HI CH 61 LO CH 60 LO
9 CH 61 HI CH 62 LO
8 CH 62 HI CH 63 HI CH 63 LO
7
6
5 GND +5VTC GND
4 DAV3N INTR3N XTRIG3N
3 DAV2N INTR2N XTRIG2N
2 DAV1N INTR1N XTRIG1N
1 DAV0N INTR0N XTRIG0N
Figure 1-7 Front Panel Connections
24 Keysight E1459A/Z2404B User and SCPI Programming Guide
Configuring for Installation Installing and Configuring the E1459A
1
Set the extraction levers out.
2
Slide the into any slot
(except slot 0) until the backplane
connectors touch.
3
Seat the into the
mainframe by pushing in the
extraction levers
Extraction
Levers
4
Tighten the top and bottom screws to
secure the module to the mainframe.
To remove the from the mainframe
,
reverse the procedure.
NOTE: The extraction levers will not
seat the backplane connectors on older
VXIbus mainframes. You must manually
seat the connectors by pushing in the
module until the module's fron t panel is
flush with the front of the mainframe.
The extraction levers may be used to
guide or remove the .
module
module
module
module
Installing the Keysight E1459A in a VXIbus Mainframe
The Keysight E1459A may be installed in any C-size VXIbus mainframe
slot (except slot 0). Refer to Figure 8 to install the module in a
mainframe.
Figure 1-8 Installing the Keysight E1459A in a VXIbus Mainframe
To prevent electric shock, tighten faceplate screws when
installing module into mainframe.
Keysight E1459A/Z2404B User and SCPI Programming Guide 25
Installing and Configuring the E1459A Configuring for Installation
CH0 CH5
CH1
CH2
CH3
CH4
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
+5 GND
CH29
CH30
CH31
CH32
CH33
CH34
+5 GND
+5 GND
+5 GND
CH35
CH36
CH37
CH38
CH39
CH40
CH41
CH42
CH43
CH44
CH45
CH46
CH47
CH48
CH49
CH50
CH51
CH52
CH53
CH54
CH55
CH56
CH57
CH58
CH59
CH60
CH61
CH62
CH63
+5 GND
+5 GND
GNDDAVINTREXT
GNDDAVINTREXT
GNDDAVINTREXT
Not Used
Terminal Block
The Keysight E1459A includes both the input / interrupt module and a
screw-type standard terminal block. User inputs to the terminal block are to the
High and Low for each channel, +5Volt, Ground, Data Valid (DAV0 - DAV3),
External Trigger (XTRIG0 - XTRIG3), and Interrupt (INTR0 - INTR3) .
Figure 9 shows the Keysight E1459A’s standard screw-type terminal block
connectors and associated channel numbers. Use the guidelines below to wire
connections.
Figure 1-9 Keysight E1459A Standard Screw-type Terminal Block
Wiring Guidelines
– Be sure the wires make solid connections in the screw terminals.
– Maximum terminal wire size is No. 16 AWG. When wiring all channels, a
smaller gauge wire (No. 20 or 22 AWG) is recommended. Wire ends should
be stripped 5 to 6 mm (0.2 to 0.25 in.) and tinned to prevent single strands
from shorting to adjacent terminals.
26 Keysight E1459A/Z2404B User and SCPI Programming Guide
To prevent the spread of fire in the case of a fault, use
flame-rated field wiring whenever the input voltage will
exceed 30Vrms, 42Vpeak, or 60Vdc.
Configuring for Installation Installing and Configuring the E1459A
.
Wiring a Terminal Block
The following illustrations show how to connect field wiring to the terminal block.
Continued on Next Page
Keysight E1459A/Z2404B User and SCPI Programming Guide 27
Installing and Configuring the E1459A Configuring for Installation
5
Replace Wiring Exit Panel
Cut required
holes in panels
for wire exit
Keep wiring exit panel
hole as small as
possible
6
Replace Clear Cover
A. Hook in the top cover tabs
onto the fixture
B. Press down and
tighten screws
7
Install the Terminal
Module
HP E1459A
Module
8
Push in the Extraction Levers to Lock the
Terminal Module onto the HP E1459A
Extraction
Levers
.
28 Keysight E1459A/Z2404B User and SCPI Programming Guide
E1459A/Z2404B User and SCPI Programming Guide
2 Using the Keysight E1459A
Module
This chapter provides examples of using and programming the Keysight E1459A
using the Standard Commands for Programmable Instrumentation (SCPI). For
detailed information on all the SCPI commands for this module, refer to Chapter
3. Appendix B in this manual provides information on registers and
register-based programming.
If you are controlling the module by a high level language, such as
the downloaded SCPI driver or the VXIplug&play driver, do not do
register writes. This is because the high level driver will not know
the instrument state and an interrupt may occur causing the
driver and/or command module to fail.
The example programs in this chapter were developed with the ANSI C language
using the Keysight VISA extensions. For additional information, refer to the
Keysight VISA User’s Guide. These programs were written and tested in Microsoft
Visual C++ but should compile under any standard ANSI C compiler.
To run the programs you must have the Keysight SICL Library, the Keysight VISA
extensions, and an Keysight 82340 or 82341 GPIB module installed and properly
configured in your PC. An Keysight E1406 Command Module provides direct
access to the VXI backplane.
29
Using the Keysight E1459A Module Power-on / Reset States
Power-on / Reset States
At power-on or reset (*RST) the Keysight E1459A is set to the following
conditions:
– Watchdog timer is off (disabled).
– Clock Source is Internal
– Input Debounce Time is 18.0 S.
– DAV (Data Available) Event interrupts are disabled for all ports.
– Edge Event interrupts are disabled for all ports.
Also, refer to the
STATus:PRESet command in Chapter 3.
Example 1: Reset, Self Test, and Module ID
This first example resets the Keysight E1459A, performs the module self test, and
reads the module ID and description.
/* Self Test
This program resets the Keysight E1459A, performs a Self Test,
and reads the ID string
Created in Microsoft Visual C++ */
#include <visa.h>
#include <stdio.h>
#include <stdlib.h>
#define INSTR_ADDR "GPIB0::9::3::INSTR"
/* E1459A logical address */
int main()
{
ViStatus errStatus;
/* status from VISA call */
ViSession viRM;
/* Resource Mgr. session */
ViSession E1459;
/* session for Keysight E1459A */
char id_string [256] = {0};
/* ID string buffer */
char selftst_string[256] = {0};
/* Open a default Resource Manager */
30 Keysight E1459A/Z2404B User and SCPI Programming Guide
Power-on / Reset States Using the Keysight E1459A Module
errStatus = viOpenDefaultRM (&viRM);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
/* Open the Instrument Session */
errStatus = viOpen (viRM, INSTR_ADDR,VI_NULL,VI_NULL, &E1459);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
/* Reset the E1459A */
errStatus = viPrintf (E1459, "*RST;*CLS\n");
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
/* Send the Self Test Command */
errStatus = viQueryf (E1459, "*TST?\n","%t",selftst_string);
if (VI_SUCCESS > errStatus){
printf("ERROR: viQueryf() returned 0x%x\n",errStatus);
return errStatus;}
printf("Self Test Result is %s\n",selftst_string);
/* Query the ID string */
errStatus = viQueryf (E1459, "*IDN?\n","%t",id_string);
if (VI_SUCCESS > errStatus){
printf("ERROR: viQueryf() returned 0x%x\n",errStatus);
return errStatus;}
printf("IDN? returned %s\n",id_string);
/* Close Sessions */
errStatus = viClose (E1459);
if (VI_SUCCESS > errStatus){
printf("ERROR: viClose() returned 0x%x\n",errStatus);
return 0;}
errStatusviClose (viRM);
if (VI_SUCCESS > errStatus){
printf("ERROR: viClose() returned 0x%x\n",errStatus);
return 0;}
}
/* End of main program */
Keysight E1459A/Z2404B User and SCPI Programming Guide 31
Using the Keysight E1459A Module Power-on / Reset States
Digital Input
The Keysight E1459A is capable of simple digital inputs on any of the individual
four ports or combined Ports 0 and 1 or Ports 2 and 3. The
MEASure command
subsystem (see Chapter 3 for details) provides two commands for reading the
current value of the input ports:
MEASure:DIGital:DATAn:type:VALue? — reads the current port value
MEASure:DIGital:DATAn:type:BITm? — reads an individual bit value
Example 2: Digital Input
This program reads Port 0 as an individual 16-bit port and then it reads the
combined Ports 2 and 3 as a 32-bit port. The values returned are a signed 16-bit
integer for Port 0 and a signed 32-bit integer for combined Ports 2 and 3.
Although this program does not decode the returned value to determine
individual bit/channel values, a "0" in any bit position indicates the input to the
corresponding channel is low; a "1" in any bit position indicates the input to the
corresponding channel is high.
/* Digital Input Example
This program reads the current value of Port 0 (16-bit word)
and combined value of Ports 2 and 3 (32-bit word)
Created in Microsoft Visual C++ */
#include <visa.h>
#include <stdio.h>
#include <stdlib.h>
#define INSTR_ADDR "GPIB0::9::3::INSTR"
/* E1459A logical address */
int main()
{
ViStatus errStatus;
/* status from VISA call */
ViSession viRM;
/* Resource Mgr. session */
ViSession E1459;
/* session for E1459A */
int val;
/* value of Port 0 */
long val1;
/*Value of Ports 2 & 3 */
/* Open a default Resource Manager */
errStatus = viOpenDefaultRM (&viRM);
if (VI_SUCCESS > errStatus){
32 Keysight E1459A/Z2404B User and SCPI Programming Guide
Power-on / Reset States Using the Keysight E1459A Module
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
/* Open the Instrument Session */
errStatus = viOpen (viRM, INSTR_ADDR,VI_NULL,VI_NULL, &E1459);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
/* Query Port 0 as a 16-bit word */
errStatus = viQueryf(E1459, "MEAS:DIG:DATA0:WORD:VAL?\n","%t", val);
if (VI_SUCCESS > errStatus){
printf("ERROR: viQueryf() returned 0x%x\n",errStatus);
return errStatus;}
printf("Value returned %i\n",val);
/* Query Ports 2 and 3 as a 32-bit word */
errStatus = viQueryf(E1459, "MEAS:DIG:DATA2:LWORD:VAL?\n","%t", val1);
if (VI_SUCCESS > errStatus){
printf("ERROR: viQueryf() returned 0x%x\n",errStatus);
return errStatus;}
printf("Value returned %i\n",val1);
/* Close Sessions */
errStatus = viClose (E1459);
if (VI_SUCCESS > errStatus){
printf("ERROR: viClose() returned 0x%x\n",errStatus);
return 0;}
errStatus = viClose (viRM);
if (VI_SUCCESS > errStatus){
printf("ERROR: viClose() returned 0x%x\n",errStatus);
return 0;}
}
/* End of main program */
Keysight E1459A/Z2404B User and SCPI Programming Guide 33
Using the Keysight E1459A Module Edge Detected Event Detection
Edge Detected Event Detection
The Keysight E1459A can respond to two types of events: Edge Events (either
negative edge, positive edge, or both) and Data Available. Figures 2-1 and 2-2
show the general flow of commands necessary to program the Keysight E1459A
to detect events. Figure 2-1 shows the flow for Edge Event Detection, Figure 2-2
shows the flow for Data Available Event Detection.
Three general methods of identifying and servicing an Keysight E1459A detected
event are:
– Polling the Port Summary Register
– Polling the VXI Status Subsystem
– SRQ Interrupt
When an Edge Event occurs, read the value of the port(s) with the
[SENSe:]EVENt:PORTn:NEDGe? or [SENSe:]EVENt:PORTn:PEDGe? command.
When a Data Available Event occurs, read the value of the port(s) with the
MEASure:DIGital:DATAn command.
Polling the Port Summary Register
The first, and easiest method, is to repeatedly poll the Port Summary Register
using either the
SENSe:EVENt:PSUMmary:DAVailable? command (for Data Available Events)
the
until an event occurs. Example 3 in this chapter demonstrates this procedure.
SENSe:EVENt:PSUMmary:EDGE? command (for Edge Events) or
Polling the Status Subsystem
The second method is to set-up and repeatedly poll the Status Subsystem. You
can poll the port summary condition register with the
STATus:OPERation:PSUMmary:CONDition? command to determine when an event
has occurred.
Alternately, set-up the port summary enable register to specify the type of
event(s) and port(s) to monitor; use the
STATus:OPERation:PSUMmary:ENABle<mask> command. Then enable bit 9 in the
Status Operation Enable register; use the
Repeatedly poll the module with the *
becomes set.
SRQ Interrupt
STATus:OPERation:ENABle command.
STB? command to determine when bit 7
The third method is to set-up the Status Subsystem and have the Keysight
E1459A Module interrupt (via SRQ) the system computer when an event occurs.
In general, you must set-up the port summary enable register to specify the type
of event(s) and port(s) to monitor; use the
34 Keysight E1459A/Z2404B User and SCPI Programming Guide
Edge Detected Event Detection Using the Keysight E1459A Module
Unmask all 16 bits of Port.
(Either Positive, Negative,
or both.)
Optionally, set the
Debounce Time
Enable the Edge Detection
Wait for the Event to Occur.
Do one of the following:
1. Poll the Port Summary Register
2. Poll the Status Subsystem
3. Use SRQ to interrupt
Read the data and clear the
event detector register
[SENSe:]EVENt:PORTn:NEDGE:ENABle <mask>
[SENSe:]EVENt:PORTn:PEDGE:ENABle <mask>
INPutn:DEBounce:TIMe <time>
[SENSe:]EVENt:PORTn:EDGE:ENABle <state>
[SENSe:]EVENt:PSUMmary:EDGe?
STATus:OPERation:PSUMmary:CONDition?
STATus:OPERation:PSUMmary:ENABle <mask>
STATus:OPERation:ENABle 512
*SRE128
[SENSe:]EVENt:PORTn:NEDGe?
[SENSe:]EVENt:PORTn:PEDGe?
HP E1459A Edge Event Detection Flowchart
STATus:OPERation:PSUMmary:ENABle<mask> command. Then, enable bit 9 in
the Status Operation Enable register; use the
STATus:OPERation:ENABle
command. Enable the OPR bit (bit 7) in the Status Register with the
command; this allows the Operation Status register to generate the SRQ.
*SRE 128
Keysight E1459A/Z2404B User and SCPI Programming Guide 35
Figure 2-1 Keysight E1459A Edge Event Detection Flowchart
Using the Keysight E1459A Module Edge Detected Event Detection
Optionally, set the
Debounce Time
Enable the DAV Detection
Wait for the Event to Occur.
Do one of the following:
1. Poll the Port Summary Register
2. Poll the Status Subsystem
3. Use SRQ to interrupt
INPutn:DEBounce:TIMe <time>
[SENSe:]EVENt:PORTn:DAVailable:ENABle <state>
Set External Clock Source
INPutn:CLOCk[:SOURce]EXT
[SENSe:]EVENt:PSUMmary:DAV?
STATus:OPERation:PSUMmary:CONDition?
STATus:OPERation:PSUMmary:ENABle <mask>
STATus:OPERation:ENABle 512
*SRE128
HP E1459A Data Available Event Detection Flowchart
Read the data and clear the
event detector register
MEASure:DIGital:DATAn:type:VALue?
MEASure:DIGital:DATAn:type:BITm?
36 Keysight E1459A/Z2404B User and SCPI Programming Guide
Figure 2-2 Keysight E1459A Data Available Event Detection Flowchart
Edge Detected Event Detection Using the Keysight E1459A Module
Example 3: Edge Interrupt
This example repeatedly polls the Port 0 Port Summary Edge Detection Register
to determine when an edge event occurs. When an event occurs, the program
reads the values of the Positive and Negative Edge Registers and returns the
values. The values returned are in the range of -32768 to +32767. Although this
program does not decode this returned value to determine individual bit/channel
values, a "0" in any bit position indicates an edge event was not
corresponding channel; a "1" in any bit position indicates an edge event was
detected for the corresponding channel.
/* Edge Interrupt Example
This program sets both positive and negative edge detection,
queries the Port Summary Edge Detection Register in a loop
until an event occurs. The program then read the PEDGE and NEDGE
registers and returns the current value.
Created in Microsoft Visual C++ */
#include <visa.h>
#include <stdio.h>
#include <stdlib.h>
#define INSTR_ADDR "GPIB0::9::3::INSTR"
/* E1459A logical address */
int main()
{
ViStatus errStatus;
/* status from VISA call */
ViSession viRM;
/* Resource Mgr. session */
ViSession E1459;
/* session for Keysight E1459A */
int val, event;
/* Open a default Resource Manager */
errStatus = viOpenDefaultRM (&viRM);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
/* Open the Instrument Session */
errStatus = viOpen (viRM, INSTR_ADDR,VI_NULL,VI_NULL, &E1459);
if (VI_SUCCESS > errStatus){
printf("ERROR: viOpen() returned 0x%x\n",errStatus);
return errStatus;}
/* Unmask the negative edge events for Port 0 */
errStatus = viPrintf (E1459, "EVEN:PORT0:NEDG:ENAB 0xFFFF\n");
detected for the
Keysight E1459A/Z2404B User and SCPI Programming Guide 37
Using the Keysight E1459A Module Edge Detected Event Detection
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
/* Unmask the positive edge events for Port 0 */
errStatus = viPrintf (E1459, "EVEN:PORT0:PEDG:ENAB 0xFFFF\n");
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
/* Set Port 0 debounce time to 1.13 mS */
errStatus = viPrintf (E1459, "INP0:DEB:TIM 1E-3\n");
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
/* Enable Port 0 Edge Detection */
errStatus = viPrintf (E1459, "EVEN:PORT0:EDGE:ENAB ON\n");
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
/* Loop and poll Port Summary Register until event occurs */
while (event = 0)
{
errStatus = viQueryf (E1459, "EVEN:PSUM:EDGE?\n","%t",event);
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
}
/* Read NEDGE register and clear event detector register */
errStatus = viQueryf (E1459, "EVEN:PORT0:NEDGE?\n","%t",val);
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
printf ("Negative Edge Event value = %s\n",val);
/* Read PEDGE register and clear event detector register */
errStatus = viQueryf (E1459, "EVEN:PORT0:PEDGE?\n","%t",val);
if (VI_SUCCESS > errStatus){
printf("ERROR: viPrintf() returned 0x%x\n",errStatus);
return errStatus;}
printf ("Positive Edge Event value = %s\n",val);
/* Close Sessions */
errStatus = viClose (E1459);
if (VI_SUCCESS > errStatus){
printf("ERROR: viClose() returned 0x%x\n",errStatus);
38 Keysight E1459A/Z2404B User and SCPI Programming Guide
Edge Detected Event Detection Using the Keysight E1459A Module
return 0;}
errStatus = viClose (viRM);
if (VI_SUCCESS > errStatus){
printf("ERROR: viClose() returned 0x%x\n",errStatus);
return 0;}
}
/* End of main program */
Keysight E1459A/Z2404B User and SCPI Programming Guide 39
Using the Keysight E1459A Module Edge Detected Event Detection
40 Keysight E1459A/Z2404B User and SCPI Programming Guide
E1459A/Z2404B User and SCPI Programming Guide
3 Keysight E1459A SCPI Command
Reference
The Standard Commands for Programmable Instruments (SCPI) commands
described in this chapter are only available in the downloadable SCPI driver for
the Keysight Command Modules such as the Keysight E1406. If you are not using
a command module, you should use the Keysight VXIplug&play driver. This driver
is available on the Keysight Instrument Drivers CD and available on the World
Wide Web.
Common Command Format
The IEEE 488.2 standard defines the Common commands that perform functions
like reset, self-test, status byte query, etc. Common commands are four or five
characters in length, always begin with the asterisk character (*), and may
include one or more parameters. The command keyword is separated from the
first parameter by a space character. Some examples of common commands are
shown below:
*RST *ESR 32*STB?
SCPI Command Format
The SCPI commands perform functions such as making measurements, querying
instrument states, or retrieving data. A command subsystem structure is a
hierarchical structure that usually consists of a top level (or root) command, one
or more low-level commands, and their parameters. The following example
shows the root command DISPlay and some of its lower-level subsystem
commands:
:DISPlay
:MONitor
:PORT <port>
:PORT? [MINimum | MAXimum | DEFault]
[:STATe] <state>
[:STATe]?
:DISPlay is the root command, :MONitor is a second level commands, and
:PORT, PORT?, [:STATe], and [:STATe]? are third level commands.
41
Keysight E1459A SCPI Command Reference SCPI Command Format
Command Separator
A colon (:) always separates one command from the next lower level command:
DISPlay:MONitor:PORT <port>
Colons separate the root command from the second level command
(
DISPlay:MONitor) and the second level from the third level (MONitor:CHANnel).
Abbreviated Commands
The command syntax shows most commands as a mixture of upper and lower
case letters. The upper case letters indicate the abbreviated spelling for the
command. For shorter program lines, send the abbreviated form. For better
program readability, you may send the entire command. The instrument will
accept either the abbreviated form or the entire command.
For example, if the command syntax shows
both acceptable forms. Other forms of
generate an error. You may use upper or lower case letters. Therefore,
display, and DiSpLaY are all acceptable.
Implied Commands
Implied commands are those which appear in square brackets ([ ]) in the
command syntax. (Note that the brackets are not part of the command and are
not sent to the instrument.) Suppose you send a command but do not send the
associated implied command. In this case, the instrument assumes you intend to
use the implied command and it responds as if you had sent it. For example:
DISPlay:MONitor[:STATe] <state>
The third level command [:STATe] is an implied command. For example, to set the
display monitor state, you can send either of the following command statements:
DISPlay:MONitor <state> or DISPlay:MONitor:STATe <state>
DISPlay, then DISP and DISPLAY are
DISPlay, such as DISPL or DISPl will
DISPLAY,
42 Keysight E1459A/Z2404B User and SCPI Programming Guide
SCPI Command Format Keysight E1459A SCPI Command Reference
Command Parameters
Parameter Types. The following table contains explanations and examples of
parameter types you might see later in this chapter.
Parameter Type Explanations and Example
Numeric Accepts all commonly used decimal representations of number including
optional signs, decimal points, and scientific notation.
123, 123E2, -123, -1.23E2, 0.123, 1.23E-2, 1.23000E-01.
Special cases include MINimum, MAXimum, and DEFault.
Boolean Represents a single binary condition that is either true or false.
ON, OFF, 1, 0
Discrete Selects from a finite number of values. These parameters use mnemonics
to represent each valid setting.
Optional Parameters. Parameters shown within square brackets ([ ]) are optional
parameters. (Note that the brackets are not part of the command and are not
sent to the instrument.) If you do not specify a value for an optional parameter,
the instrument chooses a default value. For example, consider the
command. If you send the command without specifying a MINimum or
MAX]
MAXimum parameter, the present
parameter, the command returns the minimum current display channel. If you
send the
MAX parameter, the command returns the maximum display channel.
Be sure to place a space between the command and the parameter.
Linking Commands
Linking IEEE 488.2 Common Commands with SCPI Commands. Use a semicolon
between the commands. For example:
*RST;DISP:MON ON or DISP:MON ON;*TRG
Linking Multiple SCPI Commands. Use both a semicolon and a colon between
the commands. For example:
An example is the TRIGger:SOURce <source>
command where source can be BUS, EXT, or IMM.
:PORT? [MIN |
PORT? value is returned. If you send the MIN
DISP:MON:PORT 0;:MEAS:DIG:DATA0:WORD::VAL?
Keysight E1459A/Z2404B User and SCPI Programming Guide 43
Keysight E1459A SCPI Command Reference DIAGnostic:SYSReset Subsystem
DIAGnostic:SYSReset Subsystem
The DIAGnostic:SYSReset Subsystem controls and monitors the Watchdog
Timer. Refer to Chapter 1 for detailed information on the Watchdog Timer.
Syntax
DIAGnostic:SYSReset
[:STATe]?
:ENABle <state>
:ENABle?
DIAGnostic:SYSReset[:STATe]?
Returns the value of the Watchdog Timer state from the Watchdog Timer Control
/ Status Register.
Parameters
None
Comments
– Returns a 1 if the Watchdog Timer is asserted; returns a 0 if the Timer is
not asserted.
– Reading this register resets the Watchdog Timer.
– If the Watchdog timer is enabled, the state of the timer MUST be read
before the Watchdog time elapses. If the state is not read before the time
elapses, the Watchdog Timer asserts the VXIbus SYSRESET line.
44 Keysight E1459A/Z2404B User and SCPI Programming Guide
DIAGnostic:SYSReset:ENABle <state> Keysight E1459A SCPI Command Reference
DIAGnostic:SYSReset:ENABle <state>
Turns the Watchdog Timer ON or OFF.
Parameters
Parameter Name Parameter Type Range of Values Default
<state> numeric or discrete 0, 1, OFF, ON 0, OFF
Comments
– A 0 or OFF turns the Watchdog Timer off; a 1 or ON turns the Timer on.
– CAUTION: When the Watchdog Timer is enabled (ON), the VXIbus
backplane SYSRESET line is asserted if the Watchdog Timer is allowed to
elapse. The Watchdog Timer is reset each time the state of the Timer is
read by the DIAG:SYSR:STAT? command.
Example
DIAG:SYSR:ENAB ON Turns Watchdog Timer on
DIAGnostic:SYSReset:ENABle?
Returns the state of the Watchdog Timer as either a (unsigned) 1, or 0.
Parameters
None
Comments
Returns a 1 if the Watchdog Timer is enabled. Returns a 0 if the Timer is not
enabled.
Keysight E1459A/Z2404B User and SCPI Programming Guide 45
Keysight E1459A SCPI Command Reference DISPlay:MONitor Subsystem
DISPlay:MONitor Subsystem
The DISPlay:MONitor subsystem turns on the monitor mode. Parameters related
to the state of the data and control lines are shown on an external terminal
Refer to the Command Module’s Users’s Guide for supported terminal types. The
DISPlay:MONitor commands do not apply to any C-SCPI or VXIplug&play driver
implementation. The parameters displayed are:
Syntax
DISPlay:MONitor
:PORT <port>
:PORT? [MINimum | MAXimum | DEFault]
PORT:AUTO <state>
:PORT:AUTO?
[:STATe] <state>
[:STATe]?
DISPlay:MONitor:PORT <port>
Sets the value of the DISPlay:MONitor:PORT or sets the automatic display mode.
Parameters
Parameter Name Parameter Type Range of Values Default
1
.
<port> numeric or discrete 0, 1, 2, 3, AUTO, MINimum,
MAXimum, DEFault
AUTO
Comments
– Sets the value of the Display Monitor to Port 0, 1, 2, or 3. AUTO
automatically displays the results of a MEAS:DIG:DATAn? command
whenever that command is executed for the monitored Port if the display
monitor is active for the Port. MINimum or DEFault sets the value for the
monitored Port to 0. MAXimum sets the value for the monitored Port to 3.
– Specifying either 0, 1, 2, 3, MIN, MAX, or DEF turns the AUTO mode off.
– *RST Condition: sets the display Port to 0 and the automatic display mode
ON.
Example
DISP:MON:PORT2 Display data from port 2
DISP:MON:PORT AUTO Set automatic display mode
1 The display monitor is an RS-232 Terminal attached to an Keysight E1405B, E1406, or E1306 Command
Module and provides an interactive user interface to the Keysight E1459A.
46 Keysight E1459A/Z2404B User and SCPI Programming Guide
DISPlay:MONitor Subsystem Keysight E1459A SCPI Command Reference
DISPlay:MONitor:PORT? [MINimum | MAXimum | DEFault]
Returns the number of the current display Port as +0, +1, +2, or +3.
Parameters
None
Comments
– When sent with no parameter, this query returns a decimal number
indicating the Port being monitored. If AUTO was selected as the Port
parameter in the DISP:MON:PORT <port> command, the query returns the
number of the most recently-viewed Port. If either MINimum or DEFault
was specified, this query returns a +0. If MAXimum was specified, this
query returns a +3.
DISPlay:MONitor:PORT:AUTO <state>
Sets the automatic mode for the Display Monitor on or off. When AUTO mode is
ON, the port being monitored is automatically set to the last last port measured.
Parameters
Parameter
Name
<state> numeric or discrete 0, 1, OFF, ON OFF
Parameter Type Range of Values Default
Comments
– a 0 or OFF turns the display monitor automatic mode off; a 1 or ON turns
the display monitor automatic mode on.
– *RST Condition: sets the automatic mode on.
Example
DISP:MON:PORT:AUTO ON Turns automatic display mode on
Keysight E1459A/Z2404B User and SCPI Programming Guide 47
Keysight E1459A SCPI Command Reference DISPlay:MONitor Subsystem
DISPlay:MONitor:PORT:AUTO?
Returns the state of the automatic display mode as either +0 or +1.
Parameters
None.
Comments
– A 0 indicates the automatic display mode is OFF; a 1 indicates the
automatic display mode is ON.
– *RST Condition: sets the automatic mode on.
DISPlay:MONitor[:STATe] <state>
Turns the Display Mode on or off.
Parameters
Parameter Name Parameter Type Range of Values Default
<state> Numeric or discrete 0 | 1 | OFF | ON OFF
Comments
– DISP:MON ON enables the terminal display of Port parameters. The
parameters are updated to the terminal following each new command
accessing a Port.
– The displayed data is in the format:
-- Displayed port number: 0, 1, 2, or 3
-- Size of the data: 16-bit word or 32-bit word
-- Actual data: signed decimal and hexadecimal
– A keyboard entry at the terminal sets DISP:MON OFF.
– *RST Condition: OFF.
Example
DISP:MON ON turns the display mode on.
48 Keysight E1459A/Z2404B User and SCPI Programming Guide
DISPlay:MONitor Subsystem Keysight E1459A SCPI Command Reference
DISPlay:MONitor[:STATe]?
Returns the value of the Display Monitor State as either 0 (for OFF) or 1 (for ON).
Parameters
None
Comments
– DISP:MON[:STAT]? returns a 1 if the monitor mode is on; or returns a 0 if
the monitor mode is off.
Example
DISP:MON?
Keysight E1459A/Z2404B User and SCPI Programming Guide 49
Keysight E1459A SCPI Command Reference DISPlay:MONitor Subsystem
INPut Subsystem
The INPut Subsystem configures the input de-bounce circuitry and specifies the input
clock source.
Syntax
INPutn
:CLOCk[:SOURce] <source>
:CLOCk[:SOURce]?
:DEBounce:TIME <time> | MINimum | MAXimum | DEFault
:DEBounce:TIME? [MINimum | MAXimum | DEFault]
INPutn:CLOCk[:SOURce] <source>
Specifies the input circuitry clock source for Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
INPutn
<source>
numeric
discrete
0, 1, 2, 3
INTernal, EXTernal
0
INT
Comments
– When the clock source is set to INTernal, the input data is sampled by the
internal clock. When the clock is set to EXTernal, the input data is sampled
on negative-edge transitions of the input clock.
– This is the clock source for clocking new data from the optical isolators into
the input circuitry. New data is automatically clocked into the input
debounce circuitry for each clock pulse of the internal clock when the
clock source is INTernal. Refer to the INPut:DEBounce:TIME command to
set the Debounce time.
– For a clock source of EXTernal, new data is clocked into the input circuitry
when the external clock receives a clock pulse. Data is clocked into the
input circuitry on the positive edge of the external clock.
– Note that the debounce circuitry, current value registers, and event
detectors are always clocked by the internal clock.
– Note: if a Data Available Event is enabled for the port, attempting to set
the clock source to INTernal will result in an error -221, "Settings Conflict".
– *RST Condition: sets the input clock source to INTernal.
Example
INP1:CLOC:SOUR EXT Sets the input clock source for Port 1 to External
50 Keysight E1459A/Z2404B User and SCPI Programming Guide
DISPlay:MONitor Subsystem Keysight E1459A SCPI Command Reference
INPutn:CLOCk[:SOURce]?
Returns the programmed value of the input clock source for Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
INPutn numeric 0, 1, 2, 3 0
Comments
– The value returned is an unquoted string of EXT or INT.
Example
INPut2:CLOCk[:SOURce]? queries the input clock source for Port
INPutn:DEBounce:TIME <time> | MINimum | MAXimum | DEFault
Programs the input debounce time for Port n. Ports 0 and 1 share the same
debounce circuitry; Ports 2 and 3 share the same debounce circuitry.
Parameters
Parameter Name Parameter Type Range of Values Default
INPutn
<time>
DEFault
MINimum
MAXimum
numeric
numeric (floating pt)
0, 1, 2, 3
18.0 Sec through 9600 Sec
Default 18.0 Sec
Minimum 18.0 Sec
Maximum 9600 Sec
0
18.0S
ec
Comments
– The available debounce times are:
18.0 S, 36 S, 72 S, 144 S, 288 S, 576 S, 1.13 mS, 2.26 mS, 4.6 mS,
9.2 mS, 18.4 mS, 36.9 mS, 73.8 mS, 148.0 mS, 294.0 mS, 590.0 mS, 1.18
S, 2.36 S, 4.72 S, 9.43 S, 18.9 S, 37.8 S, 75.0 S, 150.0 S, 300 S, 600 S,
1200 S, 2400 S, 4800 S, 9600 S. Any value sent other than those listed is
rounded to the nearest discrete value.
– Debounce time is rounded to the nearest discrete value. For example 16.0
S to 18.4 S is rounded to 18 S, 18.5 S to 36.4 S is rounded to 36 S,
36.5 S to 72.4 S is rounded to 72 S, etc.
– Ports 0 and 1 use the same debounce time, Ports 2 and 3 use the same
debounce time. For n = 0 or n = 1, both Ports 0 and 1 are set; for n = 2 or n
= 3, both Ports 2 and 3 are set.
Keysight E1459A/Z2404B User and SCPI Programming Guide 51
Keysight E1459A SCPI Command Reference DISPlay:MONitor Subsystem
– *RST Condition: sets the value for the debounce time to 18.0Sec for all
four Ports.
INPutn:DEBounce:TIME? [MINimum | MAXimum | DEFault]
Returns the current debounce time for Port n as a floating point number
formatted as +d.ddddddE±ddd
Parameters
Parameter Name Parameter Type Range of Values Default
INPutn
<time>
DEFault
MINimum
MAXimum
numeric
numeric (floating pt)
0, 1, 2, 3
18.0 sec through 9600 sec
Default 18.0 sec
Minimum 18.0 sec
Maximum 9600 sec
Comments
– Ports 0 and 1 use the same debounce time, Ports 2 and 3 use the same
debounce time. For n = 0 or n = 1, this command returns the debounce
time for both Ports 0 and 1; for n = 2 or n = 3, this command returns the
debounce time for both Ports both Ports 2 and 3.
Example
INP2:DEB:TIME? Queries input circuit debounce time of Port 2
0
18.0
sec
52 Keysight E1459A/Z2404B User and SCPI Programming Guide
MEASure Subsystem Keysight E1459A SCPI Command Reference
MEASure Subsystem
The MEASure commands are used for the Isolated Digital Input part of the
Keysight E1459A. These commands return data corresponding to the current
value of the input signals. Refer to Chapter 2 for more examples of using the
MEASure Subsystem.
Syntax
MEASure:DIGital:DATAn[:type][:VALue]?
:DIGital:DATAn[:type]:BITm?
MEASure:DIGital:DATAn[:type] [:VALue]?
Returns the current data for the specified Port n as a signed integer.
Parameters
Parameter Name Parameter Type Range of Values Default
DATAn
TYPE
Numeric
discrete
0,1, 2, 3 for type WORD; 0, 2 for LWORd
WORD (Ports 0, 1, 2, or 3)
LWORd (for Ports 0 or 2)
0
WORD
Comments
– For TYPE WORD, the data is returned as a signed 16 bit integer. Example
values returned include: +0, +1, +32767, -32768. Specify port as either
DATA0, DATA1, DATA2, or DATA3.
– For TYPE LWORd, the data is returned as a signed 32 bit integer with Port
0 or Port 2 in the least significant bytes. Specify port as DATA0 or DATA2.
– Default is Port 0. :DATA is equivalent to :DATA0.
Example
MEAS:DIG:DATA 1:WORD:VAL? Queries 16-bit data from Port 1
MEAS:DIG:DATA 0:LWORD:VAL? Queries 32-bit word from Ports 0 and 1
Keysight E1459A/Z2404B User and SCPI Programming Guide 53
Keysight E1459A SCPI Command Reference MEASure Subsystem
MEASure:DIGital:DATAn[:type]:BITm?
Returns the value of BIT m of the data for the specified Port n as a signed integer
of either +0 or +1.
Parameters
Parameter Name Parameter Type Range of Values Default
DATAn
TYPE
BITm
Numeric
discrete
Numeric
0, 1, 2, or 3 for WORD; 0 or 2 for LWORd
WORD (Ports 0, 1, 2, 3)
LWORd (for Ports 0 or 2)
0 - 15 for WORD, 0 - 31 for LWORd
Comments
– For TYPE LWORd, the data from the Channel Data registers for Ports 0 and
1 OR Ports 2 and 3 are combined as a single 32 bit integer. Port 0 is the
least significant bits such that bit 0 of Port 0 becomes bit 0 and bit 15 of
Port 1 becomes bit 31 of the 32 bit integer. Likewise, Port 2 is the least
significant bits such that bit 0 of Port 2 becomes bit 0 and bit 15 of Port 3
becomes bit 31 of the 32 bit integer. The specified Port must be DATA0 or
DATA2. Refer to Chapter 2 for more details.
– *RST Condition: sets the input clock source to INTernal and the debounce
time to 18.0 S.
Example
MEAS:DIG:DATA3:WORD:BIT 12? Queries value of Bit 12 in 16-bit word from
Port 3
Word
none
MEAS:DIG:DATA 2:LWORD:BIT23? Queries value of Bit 23 in 32-bit word
from Ports 2 and 3 (Bit 7 in Port 3)
54 Keysight E1459A/Z2404B User and SCPI Programming Guide
MEMory Subsystem Keysight E1459A SCPI Command Reference
MEMory Subsystem
This command accesses the SCPI memory subsystem.
MEMory:DELete:MACRo <name>
Deletes the MACRO command defined by the name <name>.
Parameters
Parameter Name Parameter Type Range of Values Default
<name> discrete up to 12 alphanumeric characters None
Comments
– The macro was previously defined using the *DMC Common Command.
– The maximum length for <name> is 12 characters.
– This command deletes the single, named macro; the *PMC Common
command purges all macros.
Example
MEM:DEL:MACR test_macro Deletes the macro named test_macro which was
previously defined using the *DMC Common command.
Keysight E1459A/Z2404B User and SCPI Programming Guide 55
Keysight E1459A SCPI Command Reference SENSe Subsystem
SENSe Subsystem
The SENSe Subsystem configures Event Detection in the Keysight E1459A
Module. The Keysight E1459A has an event detector for each 16 bit Port to
detect positive or negative edge transitions and whether new data is available:
DAV New data is available on the specified digital input port(s).
NEDGe Negative Edge transition occurred on a specified digital input
channel(s).
PEDGe Positive Edge transition occurred on a specified digital input
channel(s).
For details on using the SENSe Subsystem, refer to Chapter 2.
Syntax
[SENSe:]EVENt
:PORTn:DAVailable?
:PORTn:DAVailable:ENABle <state>
:PORTn:DAVailable:ENABle?
:PORTn:EDGE?
:PORTn:EDGE:ENABle <state>
:PORT:EDGE:ENABle?
:PORTn:NEDG?
:PORTn:NEDG:ENABle <mask>
:PORTn:NEDG:ENABle?
:PORTn:PEDG?
:PORTn:PEDG:ENABle <mask>
:PORTn:PEDG:ENABle?
:PSUMmary:DAVailable?
:PSUMmary:EDGE?
56 Keysight E1459A/Z2404B User and SCPI Programming Guide
SENSe Subsystem Keysight E1459A SCPI Command Reference
[SENSe:]EVENt:PORTn:DAVailable?
Returns the status of the DAVailable Event for Port n as either a (unsigned) 0 or a
1.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– 1 indicates the event did occur; 0 indicates the event did not occur.
– The event must be enabled using the [SENS:]EVEN:PORTn:DAV:ENAB
command.
– The event is cleared by reading the data on Port n with the
MEAS:DIG:DATAn? command.
Example
SENS:EVEN:PORT 2:DAV? Returns status of DAV Event for Port 2
EVEN:PORT 1:DAV? Returns statusof DAV Event for Port 1
[SENSe:]EVENt:PORTn:DAVailable:ENABle <state>
Enables a Data Available interrupt to occur when new data is latched into Port n
by an external clock source.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn
<state>
Comments
– The clock source for Port n must be set to EXTernal and the event must be
enabled. Otherwise, error -221, "Settings conflict" occurs.
numeric
numeric or discrete
0, 1, 2, 3 (PORT = PORT0)
0, 1, OFF, ON
PORT0
OFF
– The external clock source is selected with the
INPutn:CLOCk[:SOURce]EXT
command.
– *RST Condition: disables the interrupt.
Keysight E1459A/Z2404B User and SCPI Programming Guide 57
Keysight E1459A SCPI Command Reference SENSe Subsystem
Example
EVEN:PORT 1:DAV:ENAB ON Enables DAV on Port 1
[SENSe:]EVENt:PORTn:DAVailable:ENABle?
Returns the state of the DAVailable Event Enable for Port n as either a (unsigned)
0 or a 1.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– A 0 means the DAVailable Event is disabled, 1 means it is enabled.
– *RST Condition: disables the interrupt.
[SENSe:]EVENt:PORTn:EDGE?
Returns the status of the Edge Detect Event for Port n as either a a (unsigned) 0
or a 1.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– A 0 means an edge event was not detected; a 1 means an edge event was
detected.
– An edge event must have been enabled by the
[SENSe:]EVENt:PORTn:EDGE<state> command and a Positive edge mask
and/or Negative edge mask must be enabled and set to a non-zero value.
– The Edge Event Status is cleared by reading PEDGE and/or NEDGE status
registers for that port.
58 Keysight E1459A/Z2404B User and SCPI Programming Guide
SENSe Subsystem Keysight E1459A SCPI Command Reference
[SENSe:]EVENt:PORTn:EDGE:ENABle <state>
Enables / disables an edge event interrupt for Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn
<state>
numeric
numeric or discrete
Comments
– Refer to the [SENSe:]EVENt:PORTn:PEDGe:ENAB or
[SENSe:]EVENt:PORTn:NEDGe:ENAB commands to configure the edge
detect registers.
– The Edge Event Status is cleared by reading PEDGE and/or NEDGE status
registers for that port.
– *RST Condition: not enabled.
Example
EVEN:PORT 2:EDGE:ENAB ON Enables Edge Detection on Port 2
[SENSe:]EVENt:PORTn:EDGE:ENABle?
Returns the state of the Edge Event Enable for Port n as a (unsigned) 0 or a 1.
Parameters
0, 1, 2, 3 (PORT = PORT0)
0, 1, OFF, ON
PORT0
OFF
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– A 0 means the Edge Event is not enabled; a 1 means it is enabled.
Keysight E1459A/Z2404B User and SCPI Programming Guide 59
Keysight E1459A SCPI Command Reference SENSe Subsystem
[SENSe:]EVENt:PORTn:NEDGe?
Returns the value of the Negative Edge Detect Register for all 16 bits of Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– The value returned is in the range of -32768 to +32767. A 0 in any bit
position indicates a negative edge event was not
corresponding bit of that port; a 1 in any bit position indicates a negative
edge event was detected for the corresponding bit of that port.
– When an edge event is detected, the Edge Detect Status is set true. Refer
to the [SENSe:]EVENt:PSUM:EDGE? and [SENSe:]EVENt:PORTn:EDGE?
commands.
detected for the
– Reading this register for all events that have occurred will clear the event
detector register.
– *RST Condition: disables the Edge Event.
[SENSe:]EVENt:PORTn:NEDGe:ENABle <mask>
Sets the Negative Edge Detection Mask for Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn
<mask>
Comments
– Each bit enables the corresponding channel negative edge detect for Port
n. A 1 means the mask is enabled for that bit, a 0 means the mask is
disabled for that bit.
– *RST Condition: clears the mask (no enabled bits).
numeric
numeric
0, 1, 2, 3 (PORT = PORT0)
-32768 to +32767 (0000
to FFFFh)
h
PORT0
0
Example
EVEN:PORT 1:NEDG:ENAB 32767 Enables Negative Edge Event Detection
60 Keysight E1459A/Z2404B User and SCPI Programming Guide
on all bits of Port 1
SENSe Subsystem Keysight E1459A SCPI Command Reference
[SENSe:]EVENt:PORTn:NEDGe:ENABle?
Returns the decimal value of the Negative Edge Detection Mask as a 16 bit
integer.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– Returns a number in the range of -32768 to +32767.
– Each bit enables the corresponding channel negative edge detect mask for
Port n. A 1 means the mask is enabled for that bit, a 0 means the mask is
disabled for that bit.
– *RST Condition: clears the mask (no masked bits).
[SENSe:]EVENt:PORTn:PEDGe?
Returns the value of the Positive Edge Detect Register for all 16 bits of Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– The value returned is in the range of -32768 to +32767. A 0 in any bit
position indicates a positive edge event was not
corresponding bit of that port; a 1 in any bit position indicates a positive
edge event was detected for the corresponding bit of that port.
– When an edge event is detected, the Edge Detect Status is set true. Refer
to the [SENSe:]EVENt:PSUM:EDGE? and [SENSe:]EVENt:PORTn:EDGE?
commands.
– Reading this register for all events that have occurred will clear the event
detector register.
– *RST Condition: disables the Edge Event.
detected for the
Keysight E1459A/Z2404B User and SCPI Programming Guide 61
Keysight E1459A SCPI Command Reference SENSe Subsystem
[SENSe:]EVENt:PORTn:PEDGe:ENABle <mask>
Sets the Positive Edge Detection Mask for Port n.
Parameters
Parameter Name Parameter Type Range of Values Default
PORTn
<mask>
numeric
numeric
Comments
– Each bit enables the corresponding channel positive edge detect mask for
Port n. A 1 means the mask is enabled for that bit, a 0 means the mask is
disabled for that bit.
– *RST Condition: clears the mask (no enabled bits).
Example
EVEN:PORT 1:PEDG:ENAB 32767 Enables Positive Edge Event Detection
[SENSe:]EVENt:PORTn:PEDGe:ENABle?
Returns the decimal value of the Positive Edge Detection Mask as a 16 bit
integer.
Parameters
0, 1, 2, 3 (PORT = PORT0)
-32768 to +32767 (0000
on all bits of Port 1
to FFFFh)
h
PORT0
0
Parameter Name Parameter Type Range of Values Default
PORTn numeric 0, 1, 2, 3 (PORT = PORT0) PORT0
Comments
– Returns a number in the range of -32768 to +32767.
– Each bit enables the corresponding channel positive edge detect mask for
Port n. A 1 means the mask is enabled for that bit, a 0 means the mask is
disabled for that bit.
– *RST Condition: clears the mask (no enabled bits).
62 Keysight E1459A/Z2404B User and SCPI Programming Guide
SENSe Subsystem Keysight E1459A SCPI Command Reference
[SENSe:]EVENt:PSUMmary:DAVailable?
Returns the status of the DAVailable Event for ALL ports as a 16 bit integer.
Parameters
None
Comments
– The value returned is in the range of +0 to +15 and is the sum of the
following values:
Value Returned Meaning
0 No Event occurred in any port
1 A DAV event occurred in Port 0
2 A DAV event occurred in Port 1
4 A DAV event occurred in Port 2
8 A DAV event occurred in Port 3
– This command is similar to the
except that this command returns the status for all ports.
Example
If the EVEN:PSUM:DAV? command returns a value of 5 it indicates a DAV event
occurred on Ports 0 and 2 (values 1 and 4 respectively, see table).
[SENSe:]EVENt:PSUMmary:EDGE?
Returns the status of the edge events for ALL ports.
Parameters
None
Comments
– The value returned is in the range of +0 to +15 and is the sum of the
following values:
Value Returned Meaning
0 No Edge Event occurred in any port
1 An Edge event occurred in Port 0
2 An Edge vent occurred in Port 1
4 An Edge vent occurred in Port 2
8 An Edge vent occurred in Port 3
[SENSe:]EVENt:PORTn:DAV? command
Keysight E1459A/Z2404B User and SCPI Programming Guide 63
Keysight E1459A SCPI Command Reference SENSe Subsystem
– This command is similar to the [SENSe:]EVENt:PORTn:EDGe? command
except that this command returns the status for all ports.
Example
If the EVEN:PSUM:EDGE? command returns a value of 10 it indicates an edge
event occurred on Ports 1 and 3 (values 2 and 8 respectively, see table).
64 Keysight E1459A/Z2404B User and SCPI Programming Guide
STATus Subsystem Keysight E1459A SCPI Command Reference
STATus Subsystem
The STATus subsystem controls the SCPI-defined Operation and Questionable
Status registers, Standard Event register, and the Status Byte register. Each is
comprised of a condition register, an event register, an enable mask, and
transition filters.
Transition filters are always set for positive edge transitions.
When an event occurs, the condition is set and the event register
bit is set true. If the event condition is cleared, the event status
register remains set. The event status register is cleared upon
reading that register.
Each status register works as follows: when a condition occurs, the appropriate
bit in the condition register is set or cleared. The contents of the events register
and the enable mask are logically ANDed bit-for-bit; if any bit of the result is set,
the summary bit for that register is set in the status byte. The status byte
summary bit for the Operation status register is bit 7; for the Questionable Signal
status register, bit 3; and for the Standard Event registers is bit 5.
Syntax
STATus
:OPERation
:CONDition?
:ENABle <mask>
:ENABle?
[:EVENt]?
:PSUMmary:CONDition?
:PSUMmary:ENABle <mask>
:PSUMmary:ENABle?
:PSUMmary[:EVENt]?
:PRESet
:QUEStionable
:CONDition?
:ENABle <mask>
:ENABle?
[:EVENt]?
The STATus system contains five registers, two of which are under IEEE 488.2
control: the Event Status Register (*ESE?) and the Status Byte Register (*STB?).
The Operational Status bit (OPR), Service Request bit (RQS), Event Summary bit
(ESB), Message Available bit (MAV) and Questionable Data bit (QUE) in the
Status Byte Register (bits 7, 6, 5, 4 and 3 respectively) can be queried with the
*STB? command. Use the *ESE? command to query the unmask value for the
Keysight E1459A/Z2404B User and SCPI Programming Guide 65
Keysight E1459A SCPI Command Reference STATus Subsystem
Event Status Register (the bits you want logically "OR'd" into the Summary bit).
The registers are queried using decimal weighted bit values. The decimal
equivalents for bits 0 through 15 are included in Figure 3-1.
The Questionable Status Condition, Event, and Enable registers
exist for SCPI compliance only. No status bits are defined or
reported in these registers.
Figure 3-1 Keysight E1459A Status System Register Diagram
66 Keysight E1459A/Z2404B User and SCPI Programming Guide
STATus Subsystem Keysight E1459A SCPI Command Reference
STATus:OPERation:CONDition?
Returns the value of the Operation Status Condition Register as a signed 16 bit
integer.
Parameters
None
Comments
– The only bit in this register used by the Keysight E1459A is bit 9 (decimal
weight 512) which contains the summary of the Operation Status Port
register.
– The Status Operation Condition register is not
is cleared only by executing the PSUMmary:EVENt command.
– *RST clears all Status Operation Conditions.
– *CLS does not affect the contents of the of the Status Operation
Conditions.
– The STATus:PRESet command does not affect the Status Operation
Conditions.
STATus:OPERation:ENABle <mask>
Sets the value of the OPERation Status Enable Register.
Parameters
Parameter Name Parameter Type Range of Values Default
<mask> numeric -32768 to 32767 (0000h to FFFFh) 0
Comments
– <mask> determines which OPERation Status conditions are summed. See
Figure 3-1. The events detected in the Port Summary Status Register are
reported in bit 9 of the Operation Status Register which in turn is reported
in bit 7 of the Status Byte Register.
cleared by this command. It
– *RST and *CLS do not affect the value of the enable mask.
– STATus:PRESet sets the value of the enable mask to 0.
Example
STAT:OPER:ENAB 0xFFFF Enable all bits of the Operation Status
Keysight E1459A/Z2404B User and SCPI Programming Guide 67
Enable Register
Keysight E1459A SCPI Command Reference STATus Subsystem
STATus:OPERation:ENABle?
Returns the value of the OPERation Status Enable Register as a signed 16 bit
integer.
Parameters
None
Comments
– The only defined bit is bit 9 which is the summary of the Data Available and
Edge Status for Ports 0, 1, 2, and 3. See Figure 3-1.
STATus:OPERation[:EVENt]?
Returns the value of the OPERation Status Event Register as a signed 16 bit
integer and then clears the register to 0.
Parameters
None
Comments
– The only bit in the OPERation Status Register used by the Keysight E1459A
is bit 9 (decimal weight 512) which contains the summary of the Operation
Status Port Register. This is a destructive read so that all register bits are
cleared after the read is executed.
– *RST does not affect the contents of the Status Operation Event Register.
– *CLS clears the contents of the Status Operation Event Register.
– STAT:PRESet does not affect the contents of the Status Operation Event
Register but does disable reporting the summary of this register in the
Status Byte Register (STB?).
STATus:OPERation:PSUMmary:CONDition?
Returns the value of the OPERation Status Port Summary Condition Register as a
signed 16 bit integer.
Parameters
None
68 Keysight E1459A/Z2404B User and SCPI Programming Guide
STATus Subsystem Keysight E1459A SCPI Command Reference
Comments
– Bits 0 through 3 reflect Data Available on Ports 0 through 3 respectively;
bits 4 through 7 reflect edge events on Ports 0 through 3 respectively. See
Figure 3-1.
– Note: This command does not clear the Port summary Condition Register.
The register is cleared only by removing the the condition itself. For
example, MEAS:DIG:DATA0 will clear Bit 0 if it was set.
– *RST clears all Status Operation Port Conditions.
– *CLS does not affect the contents of the Status Operation Port Register
Conditions.
– The STAT:PRESet command does not affect the Status Operation Port
Register contents.
STATus:OPERation:PSUMmary:ENABle <mask>
Sets the value of the OPERation Status Port Summary Enable Register.
Parameters
Parameter Name Parameter Type Range of Values Default
<mask> numeric -32768 to 32767 (0000h to FFFFh) 0
Comments
– This mask determines which Operation Status Port Summary Events are
summed and reported in bit 9 of the Operation Status Register. Bits 0
through 3 reflect Data Available on Ports 0 through 3 respectively; bits 4
through 7 reflect edge events on Ports 0 through 3 respectively. See Figure
3-1.
– *RST and *CLS do not affect the value of the enable mask.
– STATus:PRESet sets the value of the enable mask to 0.
Example
STAT:OPER:PSUM:ENAB 0xFFFF Enables all bits of the Operation
Status Port Summary Enable Register
Keysight E1459A/Z2404B User and SCPI Programming Guide 69
Keysight E1459A SCPI Command Reference STATus Subsystem
STATus:OPERation:PSUMmary:ENABle?
Returns the value of the Operation Status Port Summary Enable Register as a
signed 16 bit integer.
Parameters
None
STATus:OPERation:PSUMmary[:EVENt]?
Returns the value of the Operation Status Port Summary Event Register as a
signed 16 bit integer and then clears the register to 0.
Parameters
None
Comments
– This is a destructive read so that all register bits are cleared after the read
– *RST does not affect the contents of the Status Operation Port Summary
– *CLS clears the contents of the Status Operation Event Port Register.
– STAT:PRESet does not affect the contents of the Status Operation Event
STATus:PRESet
Presets the Status system registers and conditions.
Parameters
None
Comments
– Resets the following registers and conditions:
is executed.
Event Register.
Port Summary register but does disable the reporting of the summary of
this register in bit 9 of the Status Operation Register.
Register Action Register Action
Status Byte none OPER Status condition none
Standard Event event none OPER Status event none
70 Keysight E1459A/Z2404B User and SCPI Programming Guide
STATus Subsystem Keysight E1459A SCPI Command Reference
Register Action Register Action
Standard Event enable presets to 0 OPER Status enable presets to 0
QUES Status Condition none OPER PSUM condition none
QUES Status Event none OPER PSUM event none
QUES Status enable presets to 0 OPER PSUM enable presets to 0
all transition filters none
STATus:QUEStionable:CONDition?
Always returns a 0.
The Questionable Status Condition, Event, and Enable registers
exist for SCPI compliance only. No status bits are defined or
reported in these registers.
Parameters
None
Comments
– No bits are defined.
– *RST clears all Status Questionable Conditions.
– *CLS does not affect the contents of the Status Questionable Conditions.
– The STAT:PRESet command does not affect the Status Questionable
Conditions.
STATus:QUEStionable:ENABle <mask>
Sets the value of the QUEStionable Status Enable Register.
The Questionable Status Condition, Event, and Enable registers
exist for SCPI compliance only. No status bits are defined or
reported in these registers.
Parameters
None
Comments
– No bits are defined.
Keysight E1459A/Z2404B User and SCPI Programming Guide 71
Keysight E1459A SCPI Command Reference STATus Subsystem
– *RST and *CLS do not affect the value of the enable mask.
– The STAT:PRESet command sets the value of the enable mask to 0.
STATus:QUEStionable:ENABle?
Returns the value of the QUEStionable Status Enable Register as a signed 16 bit
integer.
The Questionable Status Condition, Event, and Enable registers exist for
SCPI compliance only. No status bits are defined or reported in these
registers.
Parameters
None
Comments
– No bits are defined.
STATus:QUEStionable[:EVENt]?
Returns the value of the QUEStionable Status Event Register as a signed 16 bit
integer and then clears the register to 0.
The Questionable Status Condition, Event, and Enable registers exist for
SCPI compliance only. No status bits are defined or reported in these
registers.
Parameters
None
Comments
– No bits are defined.
– This is a destructive read so that all register bits are cleared after the read
is executed.
– *RST does not affect the contents of the Status Questionable Event
Register.
– *CLS clears the contents of the Status Questionable Event Register.
– STAT:PRESet does not affect the contents of the Status Questionable Event
Register but does disable reporting the summary of this register in the
Status Byte register (STB?)
72 Keysight E1459A/Z2404B User and SCPI Programming Guide
SYSTem Subsystem Keysight E1459A SCPI Command Reference
SYSTem Subsystem
The SYSTem Subsystem returns module-specific information. This information
includes module type and description, and error messages.
Syntax
SYSTem
:CDEScription? <number>
:CTYPe? <number>
:ERRor?
:VERsion?
SYSTem:CDEScription? <number>
Returns the module description.
Parameters
Parameter Name Parameter Type Range of Values Default
<number> Numeric 1 None
Comments
– <number> must be equal to 1 since only one Keysight E1459A module is
allowed in a single instrument (logical address).
– The command returns the following string:
"64-Channel Isolated Digital Input / Interrupt"
Example
SYSTem:CDEScription? 1 Requests the module description.
Keysight E1459A/Z2404B User and SCPI Programming Guide 73
Keysight E1459A SCPI Command Reference SYSTem Subsystem
SYSTem:CTYPe? <number>
Returns the module card type.
Parameters
Parameter Name Parameter Type Range of Values Default
<number> Numeric 1 None
Comments
– <number> must be equal to 1 since only one Keysight E1459A module is
allowed in a single instrument (logical address).
– The command returns the following string:
"HEWLETT-PACKARD,E1459A/Z2404B,0,revision"
(revision is the revision of the driver, for example A.01.00).
Example
SYSTem:CTYPe? Requests the module card type.
SYSTem:ERRor?
Queries the error register for the error value and string to identify the error. The
errors are held in an error buffer and read on a First-In-First-Out basis.
Parameters
None
Comments
– Returns the error number and string. If no errors are in the error buffer, the
command returns:
+0,"No error"
– *CLS clears the error buffer.
– *RST does not affect the error buffer
– Refer to Appendix C for possible error messages.
Example
SYST:ERR? Requests the error messages.
74 Keysight E1459A/Z2404B User and SCPI Programming Guide
SYSTem Subsystem Keysight E1459A SCPI Command Reference
SYSTem:VERSion?
Returns the SCPI version to which this module complies.
Parameters
None
Comments
– Returns a decimal value in the form:YYY.R where YYY is the year and R is
the revision number within that year. Since there is no SCPI subsystem
defined for Digital I/O or Event Interrupts, the version returned will be:
1990.0
Keysight E1459A/Z2404B User and SCPI Programming Guide 75
Keysight E1459A SCPI Command Reference IEEE 488.2 Common Commands
IEEE 488.2 Common Commands
The following table lists the IEEE 488.2 Common Commands listed by functional
group that can be executed by the Keysight E1459A Digital Input / Interrupt
Module. However, commands are listed alphabetically in the reference. Example
are shown in the reference when the command has parameters or returns a
non-trivial response; otherwise, the command string is as shown in the table. For
additional information, refer to IEEE Standard 488.2-1987.
Command Title Description
*CLS Clear Status Registers Clears all STATus event registers and clears the error queue.
*ESE
<mask>
*ESE? Event Status Enable Query Returns the current programmed value of the Event Status Enable Register.
*ESR? Event Status Register Query. Queries and clears contents of the Standard Event Status Register.
*IDN? Identification query Returns the (unquoted) identification string:
*OPC Operation Complete This command always immediately sets the operation complete bit (bit 0) in the
*OPC? Operation Complete Query This command always returns a 1 since there are never any pending operations.
*RCL<state> Recalls stored instrument
*RST Resets the module Resets the module to the settings shown in the "Power-On and Reset State" table
*SAV<state> Save state to memory Saves the present instrument state in the specified memory location (1 to 9).
Event Status Enable Sets the bits in the Event Status Enable Register. <mask> has a range of 0 through
255 and must be entered in decimal format.
HEWLETT-PACKARD,E1459A/Z2404B,0,revision
Standard Event Register because there are never any pending operations.
Recalls the specified stored instrument state where <state> has a value of 0
state from memory
through 9. The following conditions or settings are saved/recalled: debounce
time, positive edge detect, positive edge mask, negative edge detect, negative
edge mask, QUEStionable and OPERation PSUMmary Status Enable Registers,
QUEStionable and OPERation Status Event Register, QUEStionable and OPERation
PORT Status Event Register, QUEStionable and OPERation PSUM Status Event
Register.
following the individual common command descriptions.
Refer to *RCL.
*SRE
<mask>
*SRE? Service Request Enable
*STB? Status Byte Returns the current value of the Status Byte Register.
*TRG Bus Trigger *TRG is not supported on the Keysight E1459A.
*TST? Self-Test Returns "0" if self-test passed. Returns "1" if read of ID register (00
76 Keysight E1459A/Z2404B User and SCPI Programming Guide
Service Request Enable Sets the bits in the Service Request Enable Register. <mask> has a range of 0
through 255 and must be entered in decimal format.
Returns the current programmed value of the Service Request Enable Register.
Query
) failed,
returns "2" if read of Device Type Register (02
Port n failed. Instrument state returned to the power-on / reset state after *TST?
) failed, "20n" if interrupt test on
h
h
IEEE 488.2 Common Commands Keysight E1459A SCPI Command Reference
Command Title Description
*WAI Wait to Complete Prevents execution of commands until the No Operation Pending message is true.
Since each command is fully executed at the time of execution, the No Operation
Pending message is always true and the *WAI command always immediately
executes when received.
*EMC <n> Enable Macro Enables execution of macro <n>.
*EMC? <n> Enable macro query Queries execution state of macro <n>.
*RMC Remove macros Deletes all macros.
*LMC? List macros Lists macros by name.
*DMC Define macro Defines a macro.
*GMC? Menu query Gets results of menu query.
*PMC Purge macros Purges all system macros.
Keysight E1459A/Z2404B User and SCPI Programming Guide 77
Keysight E1459A SCPI Command Reference Command Quick Reference
Command Quick Reference
Command Subsystem Description
DIAG:SYSR:STAT?
:ENAB <state>
:ENAB?
DISP:MON:PORT <port>
:MON:PORT? [MIN | MAX | DEF]
:MON:PORT:AUTO <state>
:MON:PORT:AUTO?
:MON[:STAT] <state>
:MON[:STAT]?
INPn:CLOC[:SOUR] EXT | INT
:CLOC[:SOUR]?
:DEB:TIM <time> |MIN | MAX | DEF
:DEB:TIM? [MIN | MAX | DEF]
MEAS:DIG:DATAn[:type][:VAL]?
:DIG:DATAn[:type]:BITm?
MEM:DEL:MACR <name> Deletes the MACRO command defined by the name <name>.
[SENS:]EVEN:PORTn:DAV?
:PORTn:DAV:ENAB <state>
:PORTn:DAV:ENAB?
:PORTn:EDGE?
:PORTn:EDGE:ENAB <state>
:PORTn:EDGE:ENAB?
:PORTn:NEDG?
:PORTn:NEDG:ENAB <mask>
:PORTn:NEDG:ENAB?
:PORTn:PEDG?
:PORTn:PEDG:ENAB <mask>
:PORTn:PEDG:ENAB?
:PSUM:DAV?
:PSUM:EDGE?
Returns the value of the Watchdog Timer state (1=asserted, 0=not
asserted).
Turns the Watchdog Timer ON or OFF.
Returns the enabled state of the Watchdog Timer as either a +1, or +0.
Sets display monitor port (channel) or automatic mode.
Returns the port (channel) number of the current display.
Sets the automatic mode for the Display Monitor on or off.
Returns the state of the automatic display mode; either +0 or +1.
Turns the Display mode on or off.
Returns the value of the Display Monitor State; +0 (OFF) or +1 (ON).
Specifies the input circuitry clock source for Port n.
Returns the programmed value of the input clock source for Port n.
Programs the channel input debounce time for Port n
Returns the current debounce time as a floating point number.
Returns contents of Current Value Register(s) for the specified Port n.
Returns value of BIT m of Channel Data Register for specified Port n.
Returns status of DAVailable Event for Port n as either +0 or +1.
Enables Data Available interrupt into Port n by EXT clock source.
Returns state of DAVailable Event Enable for Port n as either +0 or +1.
Returns status of Edge Detect Event for Port n as either +0 or +1.
Enables / disables an edge event interrupt for Port n.
Returns state of the Edge Event Enable for Port n as a signed integer.
Returns value of Negative Edge Detect Register for 16 bits of Port n.
Sets the Negative Edge Detection Mask for Port n.
Returns value of Negative Edge Detection Mask as a 16 bit integer.
Returns value of Positive Edge Detect Register for 16 bits of Port n.
Sets the Positive Edge Detection Mask for Port n.
Returns value of the Positive Edge Detection Mask as a 16 bit integer.
Returns status of DAVailable Event for ALL ports as a 16 bit integer.
Returns the status of the edge events for ALL ports.
.
78 Keysight E1459A/Z2404B User and SCPI Programming Guide
Command Quick Reference Keysight E1459A SCPI Command Reference
Command Subsystem Description
STAT:OPER:COND?
:OPER:ENAB <mask>
:OPER:ENAB?
:OPER[:EVEN]?
:OPER:PSUM:COND?
:OPER:PSUM:ENAB <mask>
:OPER:PSUM:ENAB?
:OPER:PSUM[:EVEN]?
:PRES
:QUES:COND?
:QUES:ENAB <mask>
:QUES:ENAB?
:QUES[:EVEN]?
SYST:CDES? <number>
:CTYP? <number>
:ERR?
:VERS?
Returns value of Operation Status Condition Register as 16 bit int.
Sets the value of the OPERation Status Enable Register.
Returns value of OPERation Status Enable Register as 16 bit integer.
Returns value of OPERation Status Event Register as 16 bit integer.
Returns value of OPERation Status Port Condition Register as 16 bit int.
Sets the value of the OPERation Status Port Enable Register.
Returns value of Operation Status Port Enable Register as 16 bit integer.
Returns value of Operation Status Port Event Register as 16 bit integer.
Presets the Status system registers and conditions.
Returns value of Questionable Status Condition Register as 16 bit int.
Sets the value of the QUEStionable Status Enable Register.
Returns value of QUEStionable Status Enable Register as 16 bit integer.
Returns value of QUEStionable Status Event Register as 16 bit integer.
Returns the module description.
Returns the module card type.
Queries the error register for error value and string to identify the error.
Returns the SCPI version to which this module complies.
Keysight E1459A/Z2404B User and SCPI Programming Guide 79
Keysight E1459A SCPI Command Reference Command Quick Reference
80 Keysight E1459A/Z2404B User and SCPI Programming Guide
E1459A/Z2404B User and SCPI Programming Guide
A Keysight E1459A Specifications
Max Input Voltage: Between High and Low terminal of Each Channel: 60V DC.
Between Channels or Between any terminal and chassis: 125V AC or DC.
Module Size/Device Type: C, Register-based.
Connectors Used: P1 and P2.
Number of Slots: 1
VXIbus Interface Capability: Interrupter, D16.
Interrupt Level: 1-7, selectable.
Power Requirements: Voltage: +5Vdc
Peak Module Current IPM (A): 0.19
Dynamic Module Current IDM (A): 0.10
Watts/Slot: 1.0
Minimum Pulse Width: 100s + debounce time.
Operating Range:
Nominal Input Voltages
Threshold Voltage
MIN
MAX
Input Current Ma
at Nominal Voltage
Max Low Level
b
Voltage
a The Threshold Voltage represents the input voltage where the output goes high. An
input voltage between the Threshold Voltage MIN/MAX levels may trigger the output
to a high state.
b Any input voltage below the Max Low Level Voltage ensures a low output.
a
5 12 24 48
1
2.5
4
9.5
0.5 1.3
0.8 1.9 3.8 7.6
7
17
2.8
14
31
5.8
Debounce: Programmable from 16 S to 1074 S.
5 Volt Supply: Output voltage : 4.5 to 5.5 V DC. Maximum output current: 16 mA.
Typical Time to Read 16-bit Word: 4 S using register access.
81
Keysight E1459A Specifications
Input Circuit:
Terminal Module: Screw type, removable, maximum wire size 16AWG.
82 Keysight E1459A/Z2404B User and SCPI Programming Guide
B Keysight E1459A Register
Overview
E1459A/Z2404B User and SCPI Programming Guide
Definitions
The Keysight E1459A Isolated Digital Input/Interrupt module is a register-based
slave device. There are 64 isolated inputs which can be used for detecting rising
and/or falling edges independently. Each 16 channels has a set of registers used
to define the detection of interrupt conditions. Listed below are the different
register types on this module.
– ID Register - Identifies Keysight as the manufacturer, and that the card is
an A16 register based device.
– Device Type Register - Identifies card as a Keysight E1459A.
– Status/Control Register - When read it returns device specific status
information. When written it to, it sets control bits. Bit 4 specifies the
registers for the upper or lower 32 channels.
– Edge Interrupt Status Register - This register indicates which Port has
detected an edge interrupt.
– Data Available Status Register (DAV) - This register indicates which
register has been externally triggered and has data available.
– Watchdog Timer Control/Status Register - The watchdog timer on the
module is enabled and pet using this register.
– Command Register - There are two of these registers, each controls two
ports; used to control triggering and enabling interrupts.
– Channel Data Register - There are four of these registers, one for each
port; these registers contain the current channel data.
– Positive Edge Detect Register - There are four of these registers, one for
each port; used to capture transitions from low to high levels.
– Negative Edge Detect Register - There are four of these registers, one for
each port; used to capture transitions from high to low levels.
– Positive Mask Register - There are four of these registers, one for each
port; these registers enable data to be captured in the Positive Edge
Detect Registers.
– Negative Mask Register - There are four of these registers, one for each
port; these registers enable data to be captured in the Negative Edge
Detect Registers.
83
Keysight E1459A Register Definitions Overview
– Debounce Clock Register - There are two of these registers, one for the
lower two ports and one for the upper two ports. These registers control
the clock speed of the debouncers.
84 Keysight E1459A/Z2404B User and SCPI Programming Guide
Addressing the Registers Keysight E1459A Register Definitions
Addressing the Registers
To read or write to specific registers you must address a particular
register within a module. The registers within a module are located
using a fixed offset. The module address is based upon the module's
logical address. There are two basic ways of accessing registers. One
method uses the logical address directly to access a particular card
using VXI:READ and VXI:WRITE commands through a command
module. The other method can be used with an embedded controller
that locates A16 data space within its memory map. The memory
mapping allows registers to be directly read or written with moves
to/from memory.
The factory setting of the logical address dip switch is 144 (90 hex).
This value is used in the following examples.
Register Access with Logical Address
When using the Keysight E1406 Command Module to access registers
via VXI:READ and VXI:WRITE commands, the logical address is used
to determine which VXI module is being accessed.
Refer to the Keysight E1406 Command Module documentation for
usage of the VXI:READ and VXI:WRITE commands and other
related commands.
The following commands are sent to the Keysight E1406 Command
Module via the GPIB. The following example shows a portion of an
BASIC program. The controller could either be external or embedded
in the VXI Mainframe. This example shows the Status/Control Register
being accessed.
! Writes FFFF hex to Control Register
OUTPUT 70900;"VXI:WRITE 144,4,#HFFFF"
! Reads from Status Register
OUTPUT 70900;"VXI:READ? 144,4"
ENTER 70900;Status
Register Access with Memory Mapping
When using an embedded controller VXI A16 address space is usually
mapped to some block of memory within the controllers addressable
memory space.
Keysight E1459A/Z2404B User and SCPI Programming Guide 85
Keysight E1459A Register Definitions Register Definitions
Refer to your embedded controller manual to determine where
VXI A16 is mapped. There may be other methods of accessing the
VXI backplane. What is shown here is the method in which A16
addresses are calculated for a module.
For example, for the Keysight 75000 Series C Mainframe with an Keysight E1406
Command Module, VXI A16 address space starts at 1F0000
= HEX). In the
h (h
Keysight E1406 Command Module, the A16 space is divided so modules are
addressed only at locations beginning with C000
allocated 64 register addresses (40
). The module base address is related to the
h
within A16. Each module is
h
logical address set by the logical address switch on the module:
base address (
For the Keysight E1459A, the factory-set logical address is 144 (90h), so to
address the Status/Control register of an Keysight E1459A using the Keysight
E1406 Command Module:
base address = (90
register address = [A16 location]h + [base addr]h + [register offset]
register address = 1F0000h + E400h + 04h = 1FE404
Register Definitions
The following registers can be accessed on the Keysight E1459A:
– ID Register (base + 00
– Device Type Register (base + 02
– Status/Control Register (base + 04
– Edge Interrupt Status Register (base + 06
– Data Available Status Register (base + 08
– Watchdog Timer Control/Status Register (base + 0A
– Command Register of Port 0/2 (base + 10
– Channel Data Register of Port 0/2 (base + 12
– Positive Edge Detect Register of Port 0/2 (base + 14
– Negative Edge Detect Register of Port 0/2 (base + 16
– Positive Mask Register of Port 0/2 (base + 18
– Negative Mask Register of Port 0/2 (base + 1A
– Debounce Clock Control/Status Register of Port 0 and 1/Port 2 and 3
(base + 1E
– Command Register of Port 1/3 (base + 20
) = (logical addressh)*40h + C000
h
)*(40h) + C000h> = E400
h
)
h
)
h
)
h
)
h
h
h
h
h
)
h
)
h
)
h
)
h
)
h
)
h
)
h
)
h
)
h
)
h
86 Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions Keysight E1459A Register Definitions
– Channel Data Register of Port 1/3 (base + 22h)
Manufacturer ID Register
ID register (base = 00h) is a read only register. For the Isolated Digital
Input/Interrupt, a read of the ID register returns FFFF
manufactured by Keysight Technologies and are A16 only, register-based
devices.
Manufacturer ID Register (base + 00
b + 0
Write No Effect
Read Manufacturer ID
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
– Positive Edge Detect Register of Port 1/3 (base + 24
– Negative Edge Detect Register of Port 1/3 (base + 26
– Positive Mask Register of Port 1/3 (base + 28
– Negative Mask Register of Port 1/3 (base + 2A
)
h
h
)
h
)
h
)
– Debounce Clock Control/Status Register of Port 0 and 1/Port 2 and 3
(base + 2E
)
h
since the multiplexers are
h
)
h
* Returns FFFFh = Keysight Technologies A16 (only) register-based device
Device Type Register
Device Type register (base = 02h) is a read only register. For the Isolated Digital
Input/Interrupt, a read of the Device Type register returns 0154
is a model Keysight E1459A.
Device Type Register (base + 02
b + 2
Write No Effect
Read Always Returns 0154
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
. This indicates it
h
)
h
h
Keysight E1459A/Z2404B User and SCPI Programming Guide 87
Keysight E1459A Register Definitions Register Definitions
Status/Control Register
Status/Control register (base = 04h) can be read and written. Many of the bits
perform control functions. Reading this register returns the current state of the
status bits for the module.
Status/Control Register (base + 04
b + 4h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write Undefined D I BS Undefined
Read Undefined M Undefined D IRQ E IRQ Undefined D I BS Undefined
NOTE: Bits 8 and 9 are returned in the IACK response in the same bit positions.
)
h
WRITE
R = Reset to power-on state by writing a "1" in this bit (Must be set back to "0").
BS = Bank Select. When "0" Port 0 and Port 1 data are accessed in registers b +
through b + 2Eh. When "1" Port 2 and Port 3 data are accessed in the same
10
h
registers.
I = Interrupt Enable. When set to 1, an IRQ can be generated with an edge event
(assuming one is enabled).
D = Data Ready Enable. When set to 1 an IRQ can be generated with a DAVX
line is asserted.
READ
E IRQ = When "1" it indicates that an INTRX line has transitioned from being
asserted.
D IRQ = When "1" it indicates that a DAVX line had been asserted.
M = MODID bit = "0" module has been selected.
R
R
Bit 0 is the reset bit. Writing a "1" will force the card into reset. It must be written
back to "0" for normal operation of the card. The state of this bit is returned on a
read of this register.
Bit 4 is used to control which set of port registers are being accessed. Due to the
number of registers on this card, it is necessary to switch between registers. This
bit when set to "0" allows access to Port 0 and Port 1 data in registers 10
through 2E
. This corresponds to the first 32 channels. When this bit is a "1". Port
h
h
2 and Port 3 can be accessed in these same register locations. The state of this
bit is returned on a read of this register.
Bit 5 controls if edge interrupts are enabled ("1") or not ("0"). If enabled an edge
interrupt will generate an IRQ if other registers are properly enabled. At least one
port must have the Edge Enable bit set in the command register, and have at
least one bit enabled in one of the mask registers. If an edge event occurs, IRQ
will be asserted. This can be verified by reading the Edge Interrupt Status
88 Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions Keysight E1459A Register Definitions
Register to assure none are asserted. If any are asserted the Edge Detect
Register holding the edge event must be cleared. The state of this bit is returned
on a read of this register.
Bit 6 controls if IRQ will be asserted when data becomes available due to an
external trigger on any of the ports. A "1" enables the IRQ and a "0" disables it.
The interrupt will only occur if the following is true: The command register for at
least one of the ports must have the data ready enable bit set in order to
generate an interrupt. This can be verified by reading the Data Available Status
Register to assure that none are asserted. If any are asserted, the data available
indication will be cleared by reading any of the registers associated with the port.
The state of this bit is returned on a read of this register.
Bit 8 is a read only bit. When bit 5 is enabled, edge interrupts are enabled. It
indicates if an edge interrupt has occurred on any of the ports since the last time
IRQ was asserted. During the IACK cycle this bit will also appear as bit 8 of the
IACK response. It will then be reset. If bit 5 is not enabled this bit can be polled to
detect an edge event on any register. All pending edge events must be cleared
(read) before this bit can be reasserted.
Bit 9 is a read only bit. When bit 6 is enabled, data available interrupts are
enabled. It indicates if an external trigger has occurred on any of the ports since
the last time IRQ was asserted. During the IACK cycle this bit will also appear as
bit 9 of the IACK response. It will then be reset. If bit 6 is not enabled this bit can
be polled to detect an external trigger on any port. All pending data available
must be cleared (read) before this bit is reasserted.
In applications requiring interrupts, a commander will have to be
assigned as the interrupt handler of this module
Bit 14 is the MODID bit. When a "0" is returned in bit 14 then the module has
been selected with a high state on the P2 MODID line. If a "1" is returned then
the module has not been selected. This bit is read only.
Keysight E1459A/Z2404B User and SCPI Programming Guide 89
Keysight E1459A Register Definitions Register Definitions
Edge Interrupt Status Register
The Edge Interrupt Status Register (base + 06h) indicates if an edge interrupt has
been detected for any of the 4 ports. There are 4 bits used in this register, one for
each port. A bit will remain asserted ("1") in this register until all edge events for
a port have been cleared. Bit 0 is used for Port 0, bit 1 for Port 1, bit 2 for Port 2,
and bit 3 for Port 3. These bits reflect the state of the INTR lines available on the
terminal module. The INTR lines will be asserted when a bit is "1" in this register.
This register has no effect if it is written.
Edge Interrupt Status Register (base + 06h)
b + 6h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write No Effect
Read Always Returns FFF
INTRX = Edge interrupt for port 0 - 3. A "1" means an edge event has been
detected within the corresponding port and a "0" means one hasn't. A bit set to
"1" will only return to "0" by reading the interrupt register that caused the edge
detection to occur.
Data Available Status Register
The Data Available Status Register (base + 08h) indicates if an external trigger
has occurred for any of the 4 ports. There are 4 bits used in this register, one for
each port. A bit will be asserted when the DAV ENAB bit and the INT/EXT bit are
set ("1") in the command register for a port, and an external trigger occurs. (An
external trigger occurs on a negative edge). Bit 0 is used for Port 0, bit 1 for Port
1, bit 2 for Port 2, and bit 3 for Port 3. These bits reflect the state of the DAV lines
available on the terminal module. The DAV lines will be asserted when a bit is "1"
in this register. This register has no effect if it is written.
Data Available Register (base + 08h)
b + 8
Write No Effect
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
h
INTR3 INTR2 INTR1 INTR0
Read Always Returns FFF
h
DAV3 DAV2 DAV1 DAV0
DAVX = Data available in Port 0 - 3. A "1" means that new data has been latched
into the channel data register for that port. A "0" means it has not been triggered
yet. A bit set to "1" will only return to "0" by reading the DAV register associated
with that port.
90 Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions Keysight E1459A Register Definitions
Watchdog Timer Control/Status Register
The Watchdog Timer Control/Status Register (base + 0Ah) can be read or written.
A read of this register will automatically "pet" the Watchdog Timer and will return
a "1" in bit zero when the Watchdog Timer is enabled. A "0" means the timer is
disabled. Bit 2 returns the current state of the timer. If it is at "1" the timer is
asserted and, if enabled, would assert SYSRESET. The timer must be "pet"
periodically to keep it from asserting its output. Once the timer is unasserted
and pet it will remain unasserted, as long as it is pet within its pet time. The
timer is pet automatically whenever this register is read. Once the timer is
unasserted, it can then be enabled. It will then assert SYSRESET if it is not pet
continuously at least once within its pet time.
Watchdog Timer Control/Status Register (base + 0Ah)
b + A
Write No Effect DOGENAB
Read Always Returns FFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
h
1 1 DOGSTATE DOGENAB
DOGENAB = "0" the watchdog timer is disabled. "1" = enabled.
DOGSTATE = "0" the watchdog timer is not asserted. "1" the watchdog timer is
asserted. (If enabled when it is a "1" it will assert SYSRESET). The watchdog
timer can be "pet" by doing a read of this register. The "pet" time is selected by 2
jumpers on the PC board.
Command Register Port 0/2
The Command Register for Port 0/2 (base + 10h) can be read or written. It
contains three bits used to control operating characteristics of the port. If bit 4 of
the Control/Status Register is low ("0"), Port 0 is accessed. If bit 4 is high ("1"),
Port 2 will be accessed. All control bits default to "0" as the reset state.
Bit 0 enables ("1") and disables ("0") an edge event to be reported in the Edge
Interrupt Status Register. If this bit is "1" then any edge event captured in either
the positive or negative edge detect registers will appear in the Edge Interrupt
Status Register. An interrupt will only occur on the backplane (IRQ) if bit 5 in the
Status Register is set. If bit 0 is set to "0" then an edge event will not be
detected in the Edge Interrupt Status Register and can not cause an interrupt.
When this bit is enabled the INTR line on the terminal module is active, and will
be asserted as long as an edge event is captured in either edge detection
register. The state of this bit is returned on a read of the register.
Keysight E1459A/Z2404B User and SCPI Programming Guide 91
Keysight E1459A Register Definitions Register Definitions
Bit 1 is used to select between internal and external triggering. When set to "0",
the internal clock is used to latch in data. When in external trigger, the EXT input
(available on the terminal module) is used to clock data into the data capture
circuitry on the falling edge. The state of this bit is returned on a read of this
register.
Bit 2 enables ("1") and disables ("0") an external trigger being reported in the
Data Available Status Register. If this bit and bit 1 are set to "1", an external
trigger will cause data to be latched into the data capture circuitry. This will
cause the DAV line to be asserted and "1" to appear in the Data Available Status
Register. Once read, the DAV line will be unasserted, and the bit in the Data
Available Status Register will also be unasserted. An interrupt will only occur on
the backplane (IRQ) if bit 6 in the Status Register is set. The state of this bit is
returned on a read of this register.
Command Register Port 0/2 (base + 10h)
b + 10h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write No Effect DAV ENAB INT/EXT EDGE ENAB
Read Always Returns FFF
h
1 DAV ENAB INT/EXT EDGE ENAB
For reading and writing, when BS = 0 in the Status/Control Register, the data for
Port 0 is accessed. When BS = 1, the data for Port 2 is accessed.
EDGE ENAB = "1" allows an edge interrupt (INTR for Port 0/2 to cause an
interrupt, if enabled in the Status/Control register. When "0" edge interrupts
from Port 0/2 are disabled.
INT/EXT = "0" data will be latched using the internal clock. "1" data is latched
using EXT0/2 input.
DAV ENAB = "1" allows the DAV0/2 line to cause an interrupt if enabled in the
Status/Control Register. The DAV line is asserted when data is latched. This
should only be enabled when in external trigger mode. When set to "0" the
DAV0/2 line cannot cause an interrupt.
92 Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions Keysight E1459A Register Definitions
A potential hazard exists if software were to improperly program
the Keysight E1459A to post data-capture IRQ's with the
internally selected 1.0 MHz clock source. In this situation, a DAV
interrupt would be posted each microsecond (if software were
able to service at that rate), and would cause software to
continuously vector to interrupt service upon each "return from
service." Therefore, the Keysight E1459A should never be
programmed to generate DAV interrupts with the internal clock
source selected. (If bit 1 of the Command Register Word is set to a
one, then bit 2 must always be set to zero.)
In the Keysight E1459A the Data Ready Marker is guaranteed to
be cleared when the clock source is switched from internal to
external. Therefore, any capture clock which occurs within the
internal/external clock selection interval will not post a marker to
the control FPGA and will be lost.
Channel Data Register Port 0/2
b +
12
Write No Effect
Read
Read
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch1
Ch1
5
4
Ch4
Ch4
7
6
The Channel Data Register for Port 0/2 (base + 12h) is read only. This register
returns the current (last) data that has been clocked into the edge detection
circuitry based on either the internal or external trigger source. If bit 4 of the
Control/Status Register is low ("0"), Port 0 is accessed. If bit 4 is high ("1"), Port
2 data will be accessed.
Channel Data Register Port 0/2 (Channels 0-15/32-47) (base + 12h)
Ch1
Ch1
Ch1
Ch1
Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
3
2
1
0
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
5
4
3
2
1
0
9
8
7
6
5
4
3
Channels 0 through 15 are accessed when BS = 0 in the Status/Control Register.
Ch3
2
Channels 32 through 47 are accessed when BS = 1 in the Status/Control
Register.
Keysight E1459A/Z2404B User and SCPI Programming Guide 93
Keysight E1459A Register Definitions Register Definitions
Positive Edge Detect Register Port 0/2
The Positive Edge Detect Register for Port 0/2 (base + 14h) is read only. This
register captures any low to high transitions with a "1" in this register for any
channel that has been enabled. A channel is enabled by setting a corresponding
bit in the Positive Mask Register. Once the register is read, the data is
automatically cleared. A transition is only seen if it is held long enough to pass
through the debouncers. If bit 4 of the Control/Status Register is low ("0"), Port 0
data is accessed. If bit 4 is high ("1"), Port 2 data will be accessed.
Positive Edge Detect Register Port 0/2 (Channels 0-15/32-47) (base + 14h)
b + 14
Write No Effect
Read
Read
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch1
5
Ch4
7
Ch1
Ch1
Ch1
Ch1
Ch1
Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
4
3
2
1
0
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
6
5
4
3
2
1
0
9
8
7
6
5
4
For Positive/Negative Edge Detect and Mask Registers, channels 0 through 15
are accessed when BS = 0 in the Status/Control Register.
For Positive/Negative Edge Detect and Mask Registers, channels 32 through 47
are accessed when BS = 1 in the Status/Control Register.
Ch3
3
Ch3
2
94 Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions Keysight E1459A Register Definitions
Negative Edge Detect Register Port 0/2
The Negative Edge Detect Register for Port 0/2 (base + 16h) is read only. This
register captures any high to low transitions with a "1" in this register for any
channel that has been enabled. A channel is enabled by setting a corresponding
bit in the Negative Mask Register. Once the register is read, the data is
automatically cleared. A transition is only seen if it is held long enough to pass
through the debouncers. If bit 4 of the Control/Status Register is low ("0"), Port 0
data is accessed. If bit 4 is high ("1"), Port 2 data will be accessed.
Negative Edge Detect Register Port 0/2 (Channels 0-15/32-47) (base + 16h)
b +
16
Write No Effect
Read
Read
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch1
Ch1
5
4
Ch4
Ch4
7
6
Positive Mask Register Port 0/2
Ch1
Ch1
Ch1
Ch1
Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
3
2
1
0
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
5
4
3
2
1
0
9
8
7
6
5
4
3
The Positive Mask Register for Port 0/2 (base + 18h) can be read or written. This
register enables the Positive Edge Detect Register to capture low to high
transitions on individual channels. When a bit is set to "1" in this register it
enables that channel to be captured in the corresponding bit in the Positive Edge
Detect Register. When a bit is set to "0" it is disabled. If bit 4 of the
Control/Status Register is low ("0"), Port 0 data is accessed. If bit 4 is high ("1"),
Port 2 data will be accessed.
Positive Mask Register Port 0/2 (Channels 0-15/32-47) (base + 18h)
Ch3
2
b + 18
Read/Wr
ite
Read/Wr
ite
Keysight E1459A/Z2404B User and SCPI Programming Guide 95
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch1
Ch1
Ch1
Ch1
Ch1
Ch1
Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
5
4
3
2
1
0
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
7
6
5
4
3
2
1
0
9
8
7
6
5
4
Ch3
3
Ch3
2
Keysight E1459A Register Definitions Register Definitions
Negative Mask Register Port 0/2
The Negative Mask Register for Port 0/2 (base + 1Ah) can be read or
written. This register enables the Negative Edge Detect Register to
capture high to low transitions on individual channels. When a bit is
set to "1" in this register it enables that channel to be captured in the
corresponding bit in the Negative Edge Detect Register. When a bit is
set to "0" it is disabled. If bit 4 of the Control/Status Register is low
("0"), Port 0 data is accessed. If bit 4 is high ("1"), Port 2 data will be
accessed.
Negative Mask Register Port 0/2 (Channels 0-15/32-47) (base + 1Ah)
b + 1A
Read/Wr
ite
Read/Wr
ite
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch1
Ch1
Ch1
Ch1
Ch1
Ch1
Ch9 Ch8 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
5
4
3
2
1
0
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
7
6
5
4
3
2
1
0
9
8
7
6
5
4
Debounce Clock Register Port 0 and Port1/ Port 2 and Port 3
The Debounce Clock Register (base + 1Eh) can be read or written.
This register controls the clock rate to the debouncers. There are only
two programmable counters for all four ports. Port 0 and Port 1 share
one counter. This counter is controlled when bit 4 of the
Control/Status Register is "0". Port 2 and Port 3 share the other
counter and are accessed when bit 4 of the Control/Status Register is
"1". A 2
powers. Table 3-1 shows the allowed values for this register. This
register is mirrored at address base + 2E
1E
equivalent to programming it to 2, and programming it to 3 is the
same as 1.
N
counter is used to generate the clock, so times are binary
. Accessing register base +
h
is equivalent to base + 2Eh. Programming the register to 0 is
h
Ch3
3
Ch3
2
Debounce Clock Register Port 0 and Port 1/Port 2 and Port 3 (base + 1Eh)
b + 1E
Write No Effect DEBOUNCE TIME
Read Always Returns FFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
h
0 0 0 DEBOUNCE TIME
When BS = 0 in the Status/Control Register, the debounce clock for
Port 0 and Port 1 are accessed. Port 0 and Port 1 use the same
debounce clock. With BS = 0 any value programmed into or read from
this register will be the same as the register at b + 2E
96 Keysight E1459A/Z2404B User and SCPI Programming Guide
.
h
Register Definitions Keysight E1459A Register Definitions
When BS = 1 in the Status/Control Register, the debounce clock for Port 2 and
Port 3 are accessed. Port 2 and Port 3 use the same debounce clock. With BS =
1 any value programmed into or read from this register will be the same as the
register at b + 2E
.
h
The following table lists the actual values for the debounce times:
Register Value Bit pattern (hex) Clock Frequency Clock Period Debounce Time
(4 - 4.5 clock periods)
2 (or 0, default) 0002
3 (or 1) 0003
4 0004
5 0005
6 0006
7 0007
8 0008
9 0009
10 000A
11 000B
12 000C
13 000D
14 000E
15 000F
16 0010
17 0011
18 0012
19 0013
20 0014
21 0015
22 0016
23 0017
24 0018
25 0019
26 001A
27 001B
28 001C
29 001D
30 001E
31 001F
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
250 kHz 4 S 16 - 18 S
125 kHz 8 S 32 - 36 S
62.5 kHz 16 S 64 - 72 S
31.25 kHz 32 S 128 - 144 S
15.63 kHz 64 S 256 - 288 S
7.81 kHz 128 S 512 - 576 S
3.90 kHz 256 S 1.0 - 1.13 mS
1.95 kHz 512 S 2.0 - 2.26 mS
976 Hz 1 mS 4.1 - 4.6 mS
488 Hz 2 mS 8.2 - 9.2 mS
244 Hz 4.1 mS 16.4 - 18.4 mS
122 Hz 8.2 mS 32.8 - 36.9 mS
61 Hz 16.4 mS 65.5 - 73.8 mS
30.5 Hz 32.8 mS 131 - 148 mS
15.3 Hz 65.5 mS 262 - 294 mS
7.63 Hz 131 mS 524 - 59 mS
3.82 Hz 262 mS 1.05 - 1.16 S
1.91 Hz 524 mS 2.1 - 2.36 S
0.954 Hz 1.05 S 4.2 - 4.72 S
0.477 Hz 2.1 S 8.39 - 9.43 S
0.238 Hz 4.2 S 16.8 - 18.9 S
0.119 Hz 8.39 S 33.6 - 37.8 S
60.0 mHz 16.8 S 67.1 - 75 S
30.0 mHz 33.6 S 134 - 150 S
15.0 mHz 67.1 S 268 - 300 S
7.5 mHz 134 S 537 - 600 S
3.7 mHz 268 S 1074 - 1200 S
1.9 mHz 537 S 2147 - 2400 S
931 mHz 1074 S 4295 - 4800 S
465.5 Hz 2148 S 8590 - 9600 S
Keysight E1459A/Z2404B User and SCPI Programming Guide 97
Keysight E1459A Register Definitions Register Definitions
Command Register Port 1/3
The Command Register for Port 1/3 (base + 20h) can be read or written. It
contains three bits used to control operating characteristics of the port. If bit 4 of
the Control/Status Register is low ("0"), Port 1 data is accessed. If bit 4 is high
("1"), Port 3 data will be accessed. The operation of these Command Registers is
identical to those of Port 0/2.
Command Register Port 1/3 (base + 20h)
b + 20h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write No Effect DAV ENAB INT/EXT EDGE ENAB
Read Always Returns FFF
h
1 DAV ENAB INT/EXT EDGE ENAB
For reading and writing, when BS = 0 in the Status/Control Register, the data for
Port 1 is accessed. When BS = 1, the data for Port 3 is accessed.
EDGE ENAB = "1" allows an edge interrupt (INTR for Port 1/3 to cause an
interrupt, if enabled in the Status/Control Register. When "0" edge interrupts
from Port 1/3 are disabled.
INT/EXT = "0" data will be latched using the internal clock. "1" data is latched
using EXT1/3 input.
DAV ENAB = "1" allows the DAV1/3 line to cause an interrupt if enabled in the
Status register. The DAV line is asserted when data is latched. This should only
be enabled when in external trigger mode. When set to "0" the DAV1/3 line
cannot cause an interrupt.
A potential hazard exists if software were to improperly program
the Keysight E1459A to post data-capture IRQ's with the
internally selected 1.0 MHz clock source. In this situation, a DAV
interrupt would be posted each microsecond (if software were
able to service at that rate), and would cause software to
continuously vector to interrupt service upon each "return from
service." Therefore, the Keysight E1459A should never be
programmed to generate DAV interrupts with the internal clock
source selected. (If bit 1 of the Command Register Word is set to a
one, then bit 2 must always be set to zero.)
In the Keysight E1459A the Data Ready Marker is guaranteed to
be cleared when the clock source is switched from internal to
external. Therefore, any capture clock which occurs within the
internal/external clock selection interval will not post a marker to
the control FPGA and will be lost.
98 Keysight E1459A/Z2404B User and SCPI Programming Guide
Register Definitions Keysight E1459A Register Definitions
Channel Data Register Port 1/3
The Channel Data Register for Port 1/3 (base + 22h) is read only. This register
returns the current (last) data that has been clocked into the data capture
circuitry. If bit 4 of the Control/Status Register is low ("0"), Port 1 data is
accessed. If bit 4 is high ("1"), Port 3 data will be accessed. The operation of
these Channel Data Registers for Port 1/3 is identical to those of Port 0/2.
Channel Data Register Port 1/3 (Channels 16-31/48-63) (base + 22h)
b + 22
Write No Effect
Read
Read
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch3
1
Ch6
3
Positive Edge Detect Register Port 1/3
Ch3
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch1
Ch1
0
9
8
7
6
5
4
3
2
1
0
9
8
Ch6
Ch6
Ch6
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
2
1
0
9
8
7
6
5
4
3
2
1
0
Channels 16 through 31 are accessed when BS = 0 in the Status/Control
Register. Channels 48 through 63 are accessed when BS = 1 in the
Status/Control Register.
The Positive Edge Detect Register for Port 1/3 (base + 24h) is read only. If bit 4 of
the Control/Status Register is low ("0"), Port 1 data is accessed. If bit 4 is high
("1"), Port 3 data will be accessed. The operation of the Positive Edge Detect
Register for Port 1/3 is identical to those of Port 0/2.
Positive Edge Detect Register Port 1/3 (Channels 16-31/48-63) (base + 24h)
Ch1
7
Ch4
9
Ch1
6
Ch4
8
b + 24
Write No Effect
Read
Read
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h
Ch3
Ch3
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch1
Ch1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
Ch6
Ch6
Ch6
Ch6
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Ch1
7
Ch4
9
For Positive/Negative Edge Detect and Mask Registers, channels 16 through 31
are accessed when BS = 0 in the Status/Control Register.
Keysight E1459A/Z2404B User and SCPI Programming Guide 99
Ch1
6
Ch4
8
Keysight E1459A Register Definitions Register Definitions
For Positive/Negative Edge Detect and Mask Registers, channels 48 through 63
are accessed when BS = 1 in the Status/Control Register.
Negative Edge Detect Register Port 1/3
The Negative Edge Detect Register for Port 1/3 (base + 26h) is read only. If bit 4
of the Control/Status Register is low ("0"), Port 1 data is accessed. If bit 4 is high
("1"), Port 3 data will be accessed. The operation of the Negative Edge Detect
Register for Port 1/3 is identical to those of Port 0/2.
Negative Edge Detect Register Port 1/3 (Channels 16-31/48-63) (base + 26h)
b + 26h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write No Effect
Read
Read
b + 28
h
Read/Wr
ite
Read/Wr
ite
Ch3
Ch3
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch1
Ch1
Ch1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
Ch6
Ch6
Ch6
Ch6
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
Positive Mask Register Port 1/3
The Positive Mask Register for Port 1/3 (base + 28h) can be read or written. If bit
4 of the Control/Status Register is low ("0"), Port 1 data is accessed. If bit 4 is
high ("1"), Port 3 data will be accessed. The operation of the Positive Mask
Register for Port 1/3 is identical to those of Port 0/2.
Positive Mask Register Port 1/3 (Channels 16-31/48-63) (base + 28h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ch3
Ch3
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch1
Ch1
Ch1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
Ch6
Ch6
Ch6
Ch6
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
Ch1
6
Ch4
8
Ch1
6
Ch4
8
100 Keysight E1459A/Z2404B User and SCPI Programming Guide
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