KEMET KEM Z5U0805 100N Datasheet

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Case Size

Specication/

Capacitance

Rated Voltage

Failure Rate/

Packaging/Grade

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Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Overview

KEMET’s Z5U dielectric features an 85°C maximum operating temperature and is considered “general-purpose.” The Electronics Components, Assemblies & Materials Association (EIA) characterizes Z5U dielectric as a Class III

material. Components of this classication are xed, ceramic

dielectric capacitors suited for bypass and decoupling or other

Benets

• +10°C to +85°C operating temperature range

• Lead (Pb)-Free, RoHS and REACH compliant

• EIA 0805, 1206, 1210, 1812, 1825, and 2225 case sizes

• DC voltage ratings of 50 and 100 V

• Capacitance offerings ranging from 6,800 pF to 2.2 μF

• Available capacitance tolerances of ±20% and +80%/-20%

• Non-polar device, minimizing installation concerns

• 100% pure matte tin-plated termination nish allowing for

excellent solderability

applications in which dielectric losses, high insulation resistance and capacitance stability are not of major importance. Z5U exhibits a predictable change in capacitance with respect to time and voltage and displays wide variations in capacitance with reference to ambient temperature. Capacitance change is limited to +22%,

−56% from +10°C to +85°C.

Applications

Typical applications include limited temperature, decoupling and bypass.

Ordering Information

C 1825 C 225 M 5 U A C TU

Ceramic

Additional termination nish options may be available. Contact KEMET for details.

(L" x W")

0805 1206 1210 1812 1825 2225

Series

C = Standard Two signicant

Code (pF)

digits + number

of zeros

Tolerance

M = ±20% Z = +80%/-20

(VDC)

5 = 50 1 = 100

Dielectric

U = Z5U A = N/A C = 100% Matte

Design

Termination Finish

One world. One KEMET

(C-Spec)

See

"Packaging

C-Spec

Ordering

Options Table"

below

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Ordering Code (C-Spec)

Bulk Bag / Unmarked

Not required (Blank)

7" Reel / Unmarked

7411 (EIA 0603 and smaller case sizes)

7210 (EIA 0805 and larger case sizes)

7" Reel / Marked

7040 (EIA 0603 and smaller case sizes)

7215 (EIA 0805 and larger case sizes)

7" Reel / Unmarked / 2mm pitch

7081

13" Reel / Unmarked / 2mm pitch

7082

EIA

Code

Metric

Code

Minimum

See Table 2 for

Packaging C-Spec Ordering Options Table

Packaging Type

13" Reel / Unmarked

13" Reel / Marked

Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging.

The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors that have

not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking".

The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case size

devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information".

Packaging/Grade

Dimensions – Millimeters (Inches)

Size

0805 2012 2.00 (.079) ± 0.20 (.008) 1.25 (.049) ± 0.20 (.008)

1206 3216 3.20 (.126) ± 0.20 (.008) 1.60 (.063) ± 0.20 (.008) 0.50 (0.02) ± 0.25 (.010)

1210 3225 3.20 (.126) ± 0.20 (.008) 2.50 (.098) ± 0.20 (.008) 0.50 (0.02) ± 0.25 (.010)

1812 4532 4.50 (.177) ± 0.30 (.012) 3.20 (.126) ± 0.30 (.012) 0.60 (.024) ± 0.35 (.014)

1825 4564 4.50 (.177) ± 0.30 (.012) 6.40 (.252) ± 0.40 (.016) 0.60 (.024) ± 0.35 (.014)

2225 5664 5.60 (.220) ± 0.40 (.016) 6.40 (.248) ± 0.40 (.016) 0.60 (.024) ± 0.35 (.014)

Size

Length

Width

Thickness

Bandwidth

0.50 (0.02) ± 0.25 (.010)

Separation

0.75 (.030)

N/A

Mounting

Technique

Solder Wave or

Solder Reow

Solder Reow Only

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

250% of rated voltage

Qualication/Certication

Commercial Grade products are subject to internal qualication. Details regarding test methods and conditions are referenced in Table 4, Performance & Reliability.

Environmental Compliance

Lead (Pb)-Free, RoHS, and REACH compliant without exemptions.

Electrical Parameters/Characteristics

Item Parameters/Characteristics

Operating Temperature Range -10°C to +85°C

Capacitance Change with Reference to +25°C and 0 Vdc Applied (TCC) +22%, -5 6%

Aging Rate (Maximum % Capacitance Loss/Decade Hour) 7. 0 %

Dielectric Withstanding Voltage (DWV)

Dissipation Factor (DF) Maximum Limit @ 25°C 4.0%

Insulation Resistance (IR) Minimum Limit @ 25°C

Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part number specic

(5 ± 1 seconds and charge/discharge not exceeding 50mA)

100 megohm microfarads or 10GΩ (Rated voltage applied for 120 ± 5 secs @ 25°C)

datasheet for referee time details.

DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor.

Capacitance and dissipation factor (DF) measured under the following conditions: 1kHz ± 50Hz and 1.0 ± 0.2 Vrms if capacitance ≤10µF 120Hz ± 10Hz and 0.5 ± 0.1 Vrms if capacitance >10µF

To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits. Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as Automatic Level Control (ALC). The ALC feature should be switched to "ON".

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Dielectric

Z5U

Rated DC

Voltage

> 25

25 7.5

Capacitance

Value

All

Dissipation Factor

(Maximum %)

5.0

Capacitance

Shift

Insulation

Resistance

±30% 10% of Initial Limit

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

Case Size/Series

C0805C

C1206C

C1210C

C1812C

C1825C

C2225C

Table 1 – Capacitance Range/Selection Waterfall (0805 – 2225 Case Sizes)

Case Size/

Series

Capacitance

6,800 pF 682 M Z DN DN

8,200 pF 822 M Z DN DN 10,000 pF 103 M Z DN DN EB EB 12,000 pF 123 M Z DN EB EB 15,000 pF 153 M Z DN EB EB 18,000 pF 183 M Z DN EB EB 22,000 pF 223 M Z DN EB EB 27,000 pF 273 M Z DN EB EB 33,000 pF 333 M Z DN EB EB 39,000 pF 393 M Z DN EB EC 47,000 pF 473 M Z DN EB EC FB FB 56,000 pF 563 M Z DP EB EB FB FB 68,000 pF 683 M Z DP EB EB FB FB 82,000 pF 823 M Z DP EB EB FB FC GB GB

0.10 µ F 104 M Z DN EB EB FB FD GB GB

0.12 µ F 124 M Z EC FB FD GB GB

0.15 µ F 154 M Z EC FC FD GB GB

0.18 µ F 184 M Z EC FC GB HB HB

0.22 µF 224 M Z EC FC GB HB HB

0.27 µF 274 M Z FC GB HB HB

0.33 µF 334 M Z FD GB HB HB KB KC

0.39 µF 394 M Z FD GB HB HB KB KC

0.47 µF 474 M Z FD GB HB KB KC

0.56 µF 564 M Z FD GC HB KB

0.68 µF 684 M Z FD GC HB KB

0.82 µF 824 M Z FF GE HB KB

1.0 µF 105 M Z FH GE HB KB

1.2 µF 125 M Z HB KB

1.5 µF 155 M Z HC KC

1.8 µF 185 M Z HD KD

2.2 µF 225 M Z HF KD

Capacitance

Code

Capacitance

Code

Voltage Code 5 1 5 1 5 1 5 1 5 1 5 1

Rated Voltage ( VDC)

Capacitance Tolerance

Rated Voltage ( VDC)

Voltage Code 5 1 5 1 5 1 5 1 5 1 5 1

C0805C C1206C C1210C C1812C C1825C C2225C

50 100 50 100 50 10 0 50 100 50 10 0 50 100

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

0805

0.78 ± 0.10

4,000

15,000 0 0

0805

0.90 ± 0.10

4,000

15,000 0 0

1206

0.78 ± 0.10

4,000

10,000

4,000

10,000

1206

0.90 ± 0.10

0 0 4,000

10,000

1210

0.78 ± 0.10

0 0 4,000

10,000

1210

0.90 ± 0.10

0 0 4,000

10,000

1210

0.95 ± 0.10

0 0 4,000

10,000

1210

1.10 ± 0.10

0 0 2,500

10,000

1210

1.55 ± 0.15

0 0 2,000

8,000

1812

1.00 ± 0.10

0 0 1,000

4,000

1812

1.10 ± 0.10

0 0 1,000

4,000

1812

1.30 ± 0.10

0 0 1,000

4,000

1825

1.10 ± 0.15

0 0 1,000

4,000

1825

1.15 ± 0.15

0 0 1,000

4,000

1825

1.30 ± 0.15

0 0 1,000

4,000

1825

1.50 ± 0.15

0 0 1,000

4,000

2225

1.00 ± 0.15

0 0 1,000

4,000

2225

1.10 ± 0.15

0 0 1,000

4,000

2225

1.30 ± 0.15

0 0 1,000

4,000

Loose Packaging

Bulk Bag (default)

Case Size

Packaging Quantities (pieces/unit packaging)

0402

1005

0603

1608

0805

2012

1206

3216

1210

3225

1808

4520

1812

4532

1825

4564

2220

5650

2225

5664

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Thickness

Code

Thickness

Code

Package quantity based on nished chip thickness specications.

Case

Size

Case

Size

Thickness ± Range (mm)

Paper Quantity Plastic Quantity

7" Reel 13" Reel 7" Reel 13" Reel

Paper Quantity Plastic Quantity

Table 2B – Bulk Packaging Quantities

Packaging Type

Packaging C-Spec

EIA (in) Metric (mm) Minimum Maximum

The "Packaging C-Spec" is a 4 to 8 digit code which identies the packaging type and/or product grade. When ordering, the proper code must be included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details. Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk bag packaging option for Automotive Grade products.

A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The 15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to out standard "Bulk Bag" packaging.

N/A

50,000

20,000

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

CYXV1V2CYXV1V2CYXV1V2

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351

EIA

Size

Code

0805 2012 1.00 1.35 1.55 4.40 2.60 0.90 1.15 1.45 3.50 2.00 0.75 0.95 1.35 2.80 1.70

1206 3216 1.60 1.35 1.9 0 5.60 2.90 1.50 1.15 1.80 4.70 2.30 1.40 0.95 1.70 4.00 2.00

1210 3225 1.60 1.35 2.80 5.65 3.80 1.50 1.15 2.70 4.70 3.20 1.40 0.95 2.60 4.00 2.90

1210

1812 4532 2.15 1.60 3.60 6.90 4.60 2.05 1.40 3.50 6.00 4.00 1.95 1.20 3.40 5.30 3.70

1825 4564 2.15 1.60 6.90 6.90 7. 9 0 2.05 1.40 6.80 6.00 7.3 0 1.95 1.20 6.70 5.30 7. 0 0

2225 5664 2.70 1.70 6.90 8.10 7. 90 2.60 1.50 6.80 7.2 0 7. 3 0 2.50 1.30 6.70 6.50 7. 0 0

Only for capacitance values ≥ 22 µF Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805, and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reow solder processes. Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualication

testing based on the conditions outlined in IPC Standard 7351 (IPC –7351).

Image below based on Density Level B for an EIA 1210 case size.

Metric

Size

Code

3225 1.50 1.60 2.90 5.60 3.90 1.40 1.40 2.80 4.70 3.30 1.30 1. 20 2.70 4.00 3.00

Density Level A: Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

C C

Grid Placement Courtyard

X X

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Preheat/Soak

Temperature Minimum (T

Smin

)

100°C

150°C

Smax

Time (tS) from T

Smin

to T

Smax

60 – 120 seconds

Soldering Process

Recommended Soldering Technique:

• Solder wave or solder reow for EIA case sizes 0603, 0805 and 1206

• All other EIA case sizes are limited to solder reow only

Recommended Reow Soldering Prole:

KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual), convection,

IR or vapor phase reow techniques. Preheating of these components is recommended to avoid extreme thermal stress. KEMET’s recommended prole conditions for convection and IR reow reect the prole conditions of the IPC/J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reow passes at these conditions.

Prole Feature

Termination Finish

SnPb 100% Matte Sn

Temperature Maximum (T

Ramp-Up Rate (TL to TP) 3°C/second maximum 3°C/second maximum

Liquidous Temperature (TL) 183°C 217°C

Time Above Liquidous (tL) 60 – 150 seconds 60 – 150 seconds

Peak Temperature (TP) 235°C 260°C

Time Within 5°C of Maximum

Peak Temperature (tP)

Ramp-Down Rate (TP to TL) 6°C/second maximum 6°C/second maximum

Time 25°C to Peak

Temperature

Note 1: All temperatures refer to the center of the package, measured on the capacitor body surface that is facing up during assembly reow.

) 150°C 200°C

20 seconds maximum 30 seconds maximum

6 minutes maximum 8 minutes maximum

Maximum Ramp Up Rate = 3°C/sec Maximum Ramp Down Rate = 6°C/sec

smax

smin

Temperature

25° C to Peak

Time

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G. Flexible termination system – 3.0 mm (minimum).

Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor. Measurement at 24 hours +/- 4 hours after test conclusion.

Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor. Measurement at 24 hours +/- 4 hours after test conclusion.

t = 24 hours/cycle. Steps 7a and 7b not required. Measurement at 24 hours +/- 4 hours after test conclusion.

−55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 seconds, dwell

time – 15 minutes. Air – Air.

MIL–STD–202 Method 108

/EIA–198

5 g's for 20 min., 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick 7 secure

from any secure point. Test from 10 – 2,000 Hz

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress Reference Test or Inspection Method

Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Board Flex JIS–C–6429

Magnication 50 X. Conditions:

Solderability J–STD–002

Temperature Cycling JESD22 Method JA–104 1,000 Cycles (−55°C to +125°C). Measurement at 24 hours +/- 4 hours after test conclusion.

Biased Humidity MIL–STD–202 Method 103

Moisture Resistance MIL–STD–202 Method 106

Thermal Shock MIL–STD–202 Method 107

High Temperature Life

Storage Life MIL–STD–202 Method 108 150°C, 0 VDC for 1,000 hours.

Vibration MIL–STD–202 Method 204

Mechanical Shock MIL–STD–202 Method 213 Figure 1 of Method 213, Condition F.

Resistance to Solvents MIL–STD–202 Method 215 Add aqueous wash chemical, OKEM Clean or equivalent.

a) Method B, 4 hours @ 155°C, dry heat @ 235°C

b) Method B @ 215°C category 3

c) Method D, category 3 @ 260°C

1,000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied.

points on one long side and 2 secure points at corners of opposite sides. Parts mounted within 2"

Storage and Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term storage. In addition, packaging materials will be degraded by high temperature– reels may soften or warp and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70%

relative humidity. Temperature uctuations should be minimized to avoid condensation on the parts and atmospheres should be free of

chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of receipt.

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Construction (Typical)

Detailed Cross Section

Dielectric Material

(BaTiO

)

Termination Finish

(100% Matte Sn)

Barrier Layer

(Ni)

External Electrode

End Termination/

(Cu)

Inner Electrodes

(Ni)

Dielectric Material

(BaTiO3)

Inner Electrodes

(Ni)

End Termination/

External Electrode

(Cu)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

0603

1608

≤ 170 pF

0805

2012

≤ 150 pF

1206

3216

≤ 910 pF

1210

3225

≤ 2,000 pF

1808

4520

≤ 3,900 pF

1812

4532

≤ 6,700 pF

1825

4564

≤ 0.018 µF

2220

5650

≤ 0.027 µF

2225

5664

≤ 0.033 µF

KEMET

2-Digit

Capacitance

Code

Capacitor Marking (Optional):

These surface mount multilayer ceramic capacitors are normally supplied unmarked. If required, they can be marked as an extra cost option. Marking is available on most KEMET devices but must be requested using the correct ordering

code identi er(s). If this option is requested, two sides of the

ceramic body will be laser marked with a “K” to identify KEMET, followed by two characters (per EIA–198 - see table below) to identify the capacitance value. EIA 0603 case size devices are limited to the “K” character only.

Laser marking option is not available on:

• C0G, Ultra Stable X8R and Y5V dielectric devices

• EIA 0402 case size devices

• EIA 0603 case size devices with Flexible Termination option.

• KPS Commercial and Automotive Grade stacked devices.

• X7R dielectric products in capacitance values outlined below

EIA Case Size Metric Size Code Capacitance

Marking appears in legible contrast. Illustrated below is an example of an MLCC with laser marking of “KA8”, which designates a KEMET device with rated capacitance of 100 µF. Orientation of marking is vendor optional.

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Capacitance (pF) For Various Alpha/Numeral Identi ers

Numeral

901234567

Capacitance (pF)

0.1

1 0 10100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

0.11

1.111110

1,10 0

11,000

110,000

1,100,000

11,000,000

110,000,000

0.12

1 2 12120

1,20 0

12,000

120,000

1,200,000

12,000,000

120,000,000

0.13

1 3 13130

1,30 0

13,000

130,000

1,300,000

13,000,000

130,000,000

0.15

1 5 15150

1,50 0

15,000

150,000

1,500,000

15,000,000

150,000,000

0.16

1 6 16160

1,60 0

16,000

160,000

1,600,000

16,000,000

160,000,000

0.18

1 8 18180

1,80 0

18,000

180,000

1,800,000

18,000,000

180,000,000

0.2

2 0 20200

2,000

20,000

200,000

2,000,000

20,000,000

200,000,000

0.22

2 2 22220

2,200

22,000

220,000

2,200,000

22,000,000

220,000,000

0.24

2.424240

2,400

24,000

240,000

2,400,000

24,000,000

240,000,000

0.27

2.727270

2,700

27,000

270,000

2,700,000

27,000,000

270,000,000

0.3

3 0 30300

3,000

30,000

300,000

3,000,000

30,000,000

300,000,000

0.33

3 3 33330

3,300

33,000

330,000

3,300,000

33,000,000

330,000,000

0.36

3 6 36360

3,600

36,000

360,000

3,600,000

36,000,000

360,000,000

0.39

3 9 39390

3,900

39,000

390,000

3,900,000

39,000,000

390,000,000

0.43

4 3 43430

4,300

43,000

430,000

4,300,000

43,000,000

430,000,000

0.47

4.747470

4,700

47,000

470,000

4,700,000

47,000,000

470,000,000

0.51

5.151510

5,100

51,000

510,000

5,100,000

51,000,000

510,000,000

0.56

5 6 56560

5,600

56,000

560,000

5,600,000

56,000,000

560,000,000

0.62

6 2 62620

6,200

62,000

620,000

6,200,000

62,000,000

620,000,000

0.68

6 8 68680

6,800

68,000

680,000

6,800,000

68,000,000

680,000,000

0.75

7 5 75750

7,5 00

75,000

750,000

7,500,000

75,000,000

750,000,000

0.82

8 2 82820

8,200

82,000

820,000

8,200,000

82,000,000

820,000,000

0.91

9.191910

9,100

91,000

910,000

9,100,000

91,000,000

910,000,000

0.25

2 5 25250

2,500

25,000

250,000

2,500,000

25,000,000

250,000,000

0.35

3 5 35350

3,500

35,000

350,000

3,500,000

35,000,000

350,000,000

0.4

4 0 40400

4,000

40,000

400,000

4,000,000

40,000,000

400,000,000

0.45

4 5 45450

4,500

45,000

450,000

4,500,000

45,000,000

450,000,000

0.5

5 0 50500

5,000

50,000

500,000

5,000,000

50,000,000

500,000,000

0.6

6 0 60600

6,000

60,000

600,000

6,000,000

60,000,000

600,000,000

0.7

7 0 70700

7,000

70,000

700,000

7,000,000

70,000,000

700,000,000

0.8

8 0 80800

8,000

80,000

800,000

8,000,000

80,000,000

800,000,000

0.9

9 0 90900

9,000

90,000

900,000

9,000,000

90,000,000

900,000,000

Capacitor Marking (Optional) cont’d

Alpha

Character

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Embossed Plastic

Punched Paper

(C-Spec)

C-3190

Automotive grade 7" reel unmarked

C-3191

Automotive grade 13" reel unmarked

C-7081

Commercial grade 7" reel unmarked

C-7082

Commercial grade 13" reel unmarked

Tape & Reel Packaging Information

KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on reeling quantities for commercial chips.

Bar Code Label

Anti-Static Reel

KEMET

Embossed Plastic* or Punched Paper Carrier.

Chip and KPS Orientation in Pocket (except 1825 Commercial, and 1825 and 2225 Military)

Sprocket Holes

Embossment or Punched Cavity

178 mm (7.00")

330 mm (13.00")

8 mm, 12 mm or 16 mm Carrier Tape

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Anti-Static Cover Tape (.10 mm (.004") Maximum Thickness)

Table 5 – Carrier Tape Con guration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Tape

EIA Case Size

Size (W)*

01005 – 0402 8 2 2

0603 8 2/4 2/4

0805 8 4 4 4 4

1206 – 1210 8 4 4 4 4

1805 – 1808 12 4 4

≥ 1812 12 8 8

KPS 1210 12 8 8

KPS 1812 & 2220 16 12 12

Array 0508 & 0612 8 4 4

*Refer to Figures 1 & 2 for W and P *Refer to Tables 6 & 7 for tolerance speci cations.

7" Reel 13" Reel 7" Reel 13" Reel

)* Pitch (P1)*

Pitch (P

carrier tape reference locations.

Packaging

Ordering Code

* 2 mm pitch reel only available for 0603 EIA case size. 2 mm pitch reel for 0805 EIA case size under development.

Packaging Type/Options

Bene ts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs

• Double the parts on each reel results in fewer reel

changes and increased ef ciency

• Fewer reels result in lower packaging, shipping and storage costs, reducing waste

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Center Lines of Cavity

User Direction of Unreeling

Cover Tape

B1 is for tape feeder reference only, including draft concentric about B

ØD

ØDo

Embossment For cavity size, see Note 1 Table 4

[10 pitches cumulative tolerance on tape ± 0.2 mm]

D1 Minimum

Note 1

R Reference

Note 2

S1 Minimum

Note 3

Maximum

1.0

(0.039)

25.0

(0.984)

B1 Maximum

Note 4

Minimum

Maximum

4.35

6.25

3.5 ±0.05

4.0 ±0.10

2.5

8.3

Single (4 mm) &

Double (8 mm)

8.2

(0.323)

10.25

(0.404)

5.5 ±0.05

(0.217 ±0.002)

8.0 ±0.10

(0.315 ±0.004)

4.6

(0.181)

12.3

(0.484)

12.1

(0.476)

14.25

(0. 561)

7.5 ±0.05

(0.138 ±0.002)

12.0 ±0.10

(0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size D0

8 mm

12 mm

1.5 +0.10/-0.0

(0.059 +0.004/-0.0)

16 mm

1.5

(0.059)

1.75 ±0.10

(0.069 ±0.004)

P0 P2

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

(1.181)

0.600

(0.024)

0.600

(0.024)

Variable Dimensions — Millimeters (Inches)

Tape Size Pitch

8 mm Single (4 mm)

(0 .171)

(0.246)

16 mm Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S

< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B

dimension is a reference dimension for tape feeder clearance only.

5. The cavity de ned by A

, B0 and K0 shall surround the component with suf cient clearance that:

(a) the component does not protrude above the top surface of the carrier tape. (b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. (c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3). (d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4). (e) for KPS Series product, A

and B0 are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

F P1

(0.138 ±0.002)

(0.157 ±0.004)

(0.098)

(0.327)

A0,B0 & K

Note 512 mm

0.100

(0.0 04)

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

User Direction of Unreeling

Top Cover Tape

Center Lines of Cavity

ØDo

Cavity Size, See Note 1, Table 7

Bottom Cover Tape

[10 pitches cumulative tolerance on tape ± 0.2 mm]

0E1P0P2

R Reference

Note 2

0.10

Maximum

Variable Dimensions — Millimeters (Inches)

2.0 ±0.05

(0.079 ±0.002)

8.3

(0.327)

4.0 ±0.10

(0.157 ±0.004)

8.3

(0.327)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size D

8 mm

1.5 +0.10 -0.0

(0.059 +0.004 -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

Tape Size Pitch E2 Minimum F P1 T Maximum W Maximum A0 B

8 mm Half (2 mm)

8 mm Single (4 mm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1. The cavity de ned by A0, B0 and T shall surround the component with suf cient clearance that:

a) the component does not protrude beyond either surface of the carrier tape. b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. c) rotation of the component is limited to 20° maximum (see Figure 3). d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4). e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

T1 Maximum G Minimum

(0.004)

0.75

(0.030)

1.1

(0.098)

(0.984)

Note 1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width Peel Strength

8 mm 0.1 to 1.0 Newton (10 to 100 gf)

12 and 16 mm 0.1 to 1.3 Newton (10 to 130 gf)

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

° T

Maximum Component Rotation

Top View

Typical Pocket Centerline

Tape Maximum Width (mm) Rotation (

8,12 20 16 – 200 10

Typical Component Centerline

)

Maximum Component Rotation

Side View

Tape Maximum

Width (mm) Rotation (

8,12 20

16 – 56 10

72 – 200 5

)

Figure 4 – Maximum Lateral Movement

8 mm & 12 mm Tape

0.5 mm maximum

16 mm Tape

1.0 mm maximum

Figure 5 – Bending Radius

Embossed

Carrier

Bending

Radius

Punched

Carrier

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

D (See Note)

Full Radius,

See Note

B (see Note)

Access Hole at Slot Location (Ø 40 mm minimum)

If present, tape slot in core for tape start:

2.5 mm minimum width x

10.0 mm minimum depth

W3 (Includes

flange distortion at outer edge)

W2 (Measured at hub)

W1 (Measured at hub)

(Arbor hole

diameter)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

12.4 +2.0/-0.0

(0.488 +0.078/-0.0)

18.4

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

Figure 6 – Reel Dimensions

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size A B Minimum C D Minimum

8 mm 178 ±0.20

12 mm

16 mm

Tape Size N Minimum W1 W2 Maximum W3

8 mm

12 mm

16 mm

(7.008 ±0.008)

330 ±0.20

(13.000 ±0.008)

(1.9 6 9)

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

Variable Dimensions — Millimeters (Inches)

20.2

(0.795)

Shall accommodate tape width

without interference

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Punched Carrier 8 mm & 12 mm only

END

Trailer

160 mm Minimum

Top Cover Tape

Carrier Tape

Figure 8 – Maximum Camber

Elongated sprocket holes (32 mm & wider tapes)

1 mm Maximum, either direction

Straight Edge

Round Sprocket Holes

Components

100 mm

Minimum Leader

400 mm Minimum

Carrier Tape

START

Top Cover Tape

Elongated Sprocket Holes (32 mm tape and wider)

Round Sprocket Holes

250 mm

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

KEMET Corporation

World Headquarters

2835 KEMET Way Simpsonville, SC 29681

Mailing Address: P.O. Box 5928 Greenville, SC 29606

www.kemet.com Tel: 864-963-6300 Fax: 864-963-6521

Corporate Of ces

Fort Lauderdale, FL Tel: 954-766-2800

North America

Northeast

Wilmington, MA Tel: 978-658-1663

Southeast

Lake Mary, FL Tel: 407-855-8886

Europe

Southern Europe

Sasso Marconi, Italy Tel: 39-051-939111

Skopje, Macedonia Tel: 389-2-55-14-623

Central Europe

Landsberg, Germany Tel: 49-8191-3350800

Kamen, Germany Tel: 49-2307-438110

Northern Europe

Wyboston, United Kingdom Tel: 44-1480-273082

Espoo, Finland Tel: 358-9-5406-5000

Asia

Northeast Asia

Hong Kong Tel: 852-2305-1168

Shenzhen, China Tel: 86-755-2518-1306

Beijing, China Tel: 86-10-5877-1075

Shanghai, China Tel: 86-21-6447-0707

Seoul, South Korea Tel: 82-2-6294-0550

Taipei, Taiwan Tel: 886-2-27528585

Southeast Asia

Singapore Tel: 65-6701-8033

Penang, Malaysia Tel: 60-4-6430200

Central

Novi, MI Tel: 248-994-1030

Irving, TX

Tel: 972-915-6041

West

Milpitas, CA Tel: 408-433-9950

Mexico

Guadalajara, Jalisco

Tel: 52-33-3123-2141

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of KEMET Electronics Corporation.

Bangalore, India Tel: 91-806-53-76817

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Z5U Dielectric, 50 – 100 VDC (Commercial Grade)

Disclaimer

All product speci cations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for checking and

verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.

All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such applications, but are

not intended to constitute – and KEMET speci cally disclaims – any warranty concerning suitability for a speci c customer application or use. The Information is intended for use only

by customers who have the requisite experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no obligation or liability for the advice given or results obtained.

Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage.

Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other measures may not be required.

KEMET KEM Z5U0805 100N Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual