Kawasaki LSI KL5KUSB122 Datasheet

KL5KUSB122
USB Mini Host to 10/100 Ethernet
Kawasaki LSI 2570 North First Street Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
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General Description
The Kawasaki KL5KUSB122 Controller is a unique single chip solution that serves as a bridge between USB and Ethernet interfaces. The USB side of the controller supports both USB Host and Device modes. The KL5KUSB122 has been specifically designed to provide Ethernet connectivity to USB devices. This has been accomplished by its highly integrated functionality. The USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator, Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and SPORT Interface. The SIE (Serial Interface Engine) is fully compatible with the USB specification. This USB to Ethernet Mini Host controller is ideal for simple networking of peripherals such as home appliances, cameras, and phones.
Features
Advanced 16 Bit processor for USB transaction processing and control data processing
10/100BaseT compatibility
USB Host or USB Device interface ver. 1.0/1.1
compliant
Transceivers and SIE (Serial Interface Engine)
Internal Clock Generation - Utilizes low cost
external 12MHz crystal circuitry
MII Physical Layer interface
Remote NDIS for faster data transfer.
Debug UART
External memory interface
100 LQFP package
Serial Interface for external EEPROM
1.5K x 16 Internal RAM buffer
Block Diagram
RAM
(3KB)
Timer 0
USB Host / Device
Interface
16 Bit Address / Data Bus
Data -
Data +
Serial
Interface
Engine
Mask ROM
(8KB)
Timer 1
Watchdog
Timer
16 Bit
Processor
UART
Txd
Rxd
10/100 Mb/s
Ethernet
Interface
MII PHY
Interface
EEPROM
Serial Interface
DIO
CK
SRAM Interface
A15-0
D15-0
Cntrl.X2X1
Clock Gen. & Internal PLL
IRQ
INT 1-0
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KL5KUSB122
USB Mini Host to 10/100 Ethernet
Kawasaki LSI 2570 North First Street Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
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KL5KUSB122 Application Block Diagram
Pin Diagram 100LQFP
VDD GND
VCO_IN
CP_OUT
PLLEN
VDD
N/C PHRXD1 PHRXD2 PHRXD3 PHRXER PHRXDV
GND
PHTXD0
PHCOL PHTXEN PHTXD1 PHTXD2 PHTXD3 PHTXER
GND TXD
UGND
VP
VM
UVDD
N/C
N/C
PHTCLK
PHRXCLK
PHCRS
PH_RXD0
X_PCLK
RXD
IRQ0
IRQ1
DXA
TSCA
FS
VDD
SERROMD
SERROMCLK
PU#1
PCLK
DRA
GND
CLK
X2
XA_15
VDD
XA_7
XA_6 XA_5 XA_4 XA_3 XA_2 XA_1 nTST nRESET nXROMSEL nXWR nXRD GND nPDN GND VDD N/C N/C LED_ON nXRAMSEL IGND nXBHE XA_0 XA_14 OVDD
VDD
XD_15
XD_14
OGND
XD_13
XD_12
IGND
XD_11
XD_10
XD_9
XD_8
XD_7
XD_6
XD_5
XD_4
XD_3
XD_2
XD_1
XD_0
XA_13
XA_12
XA_11
XA_10
XA_9
XA_8
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
9998979695949392919089888786858483828180797877
76
26272829303132333435363738394041424344454647484950
KL5KUSB122_L
Optional External Memory
Serial
EEPROM
KL5KUSB122
USB /
Ethernet
PHY
Transformer
USB Host or Device
Full duplex 10/100 Base – T Ethernet MII Interface
KL5KUSB122
USB Mini Host to 10/100 Ethernet
Kawasaki LSI 2570 North First Street Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
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Pin Description
Pin #
LQFP
I/O Pin Name Description
1 IN VDD VDD 2 GND GND PLL GND 3 IN VCO_IN PLL VCO IN 4 OUT CP_OUT PLL VCO OUT 5 IN PLLEN PLL Enable 6 IN VDD PLL VDD 7 N/C N/C Open connection 8 IN PHRXD1 MII PHY Receive Data 1
9 IN PHRXD2 MII PHY Receive Data 2 10 IN PHRXD3 MII PHY Receive Data 3 11 IN PHRXER MII Receive Data Error from PHY 12 IN PHRXDV MII Receive Data Valid from PHY 13 IN GND Ground 14 OUT PHTXD0 MII Transmit data to PHY 15 IN PHCOL MII Collision input from PHY 16 OUT PHTXEN MII Transmit Enable to PHY 17 OUT PHTXD1 MII Transmit Data 1 to PHY 18 OUT PHTXD2 MII Transmit Data 2 to PHY 19 OUT PHTXD3 MII Transmit Data 3 to PHY 20 OUT PHTXER MII Transmit Error to PHY 21 IN GND Ground 22 IN/OUT TXD UART TXD 23 IN UGND USB GND 24 IN/OUT VP USB + Pin 25 IN/OUT VM USB – Pin 26 IN UVDD USB VDD 27 NC NC Open connection 28 NC NC Open connection 29 IN PHTXCLK MII PHY Transmit Clock 30 IN PHRXCLK MII PHY Receive Clock 31 IN PHCRS MII PHY Carrier Sense 32 IN PH_RXD0 MII PHY Serial Receive Data, bit 0 33 IN/OUT X_PCLK External PCLK 34 IN/OUT RXD UART RXD 35 IN IRQ0 Edge sens. Interrupt 36 IN IRQ1 Edge sens. Interrupt 37 OUT DXA Sport Mode or GPIO7 38 IN TSCA Sport Mode or GPIO8 39 IN/OUT FS Sport Mode or GPIO9 40 IN VDD Open connection 41 IN/OUT SERROMD Serial ROM Data 42 OUT SERROMCLK Serial ROM Clock 43 IN/OUT PU#1 Pull up to USB + Pin for High Speed 44 IN PCLK Sport Mode or GPIO5 45 IN DRA Sport Mode or GPIO6
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