Kawasaki LSI KL5KUSB101 Datasheet

KL5KUSB101

USB to Ethernet Controller

1

Ver. 2.4

General Description

USB Interface

16 Bit Address / Data Bus

Data -

Data +

UART

Txd

Rxd

Interface

8

DIO

CK

SRAM Interface

A15-0

D15-0

Cntrl.X2X1

IRQ

INT 1-0

2

The Kawasaki KL5KUSB101 Controller is a unique single chip solution to interface peripheral
devices to the Universal Serial Bus (USB) and Ethernet. The KL5KUSB101 has been specifically
designed to provide a simple solution to communicate with Ethernet applications as well as other
USB peripheral devices. This has been accomplished by its highly integrated functionality. The
USB controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock generator,
Ethernet interface, UART, IRQ, Watchdog Timer, Serial interface, External Memory Interface and
SPORT Interface. The SIE (Serial Interface Engine) is fully compatible with the USB specification.
This USB to Ethernet controller is ideal for LAN (Local Area Network), HAN (Home Area
Network), Cable Modem, Set Top Boxes, or Mobile Networking applications.

Features

• Advanced 16 Bit processor for USB transaction
processing and control data processing

• USB interface ver. 1.0/1.1 compliant

• Transceivers and SIE (Serial Interface Engine)

• Internal Clock Generation

• Utilizes low cost external crystal circuitry

• 1.5K x 16 Internal RAM buffer

• Serial Interface for external EEPROM

Block Diagram

Timer 0

EEPROM

Serial Interface

Timer 1

• Watchdog timer

• Fully IEEE 802.3 compliant 10 Mbit/sec

Ethernet MAC Layer. Interfaces serially of
an external ENDEC PHY.

• UART

• External memory interface

• 100 pin QFP and LQFP package

Watchdog

16 Bit

Processor

Timer

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: [phone] • Fax: [phone] • www.klsi.com

10Mb/s

Ethernet

RAM

(3KB)

Mask ROM

(8KB)

Serial

Interface

Engine

Clock

Generator

KL5KUSB101

USB to Ethernet Controller

2

Ver. 2.4

KL5KUSB101 Application Block Diagram

EEPROM

KL5KUSB101

Transformer

XD_15

RXD

XA_10

XA_11

1

80

USB

USB /

Ethernet

Optional
External
Memory

Pin Diagram 100QFP

VDD
VDD
GND

VDD
GND

PHTXD0

PHCOL

PHTXEN
PHRXER
PHRXDV
PHTXER
PHLPBK

PHUTP

TXD

UGND

UVDD

N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

VP

VM
N/C

N/C

PHY

Serial

XD_14

OGND

XD_13

XD_12

IGND

XD_11

XD_10

XD_9

XD_8

XD_7

XD_6

XD_5

XD_4

XD_3

XD_2

XD_1

99989796959493929190898887868584838281

100

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

KL5KUSB101

31323334353637383940414243444546474849

PHCRS

PHTCLK

PHRXCLK

X_PCLK

PH_RXD0

IRQ1

IRQ2

N/C

N/C

N/C

N/C

SDA

SCL

N/C

N/C

XD_0

N/C

XA_13

XA_12

CLK

OGND

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

X2

XA_9
XA_8
XA_7
XA_6
XA_5
XA_4
XA_3
XA_2
XA_1
nTST
nRESET
nXROMSEL
nXWR
nXRD
GND
nPDN
N/C
N/C
N/C
N/C
LED_ON
nXRAMSEL
IGND
nXBHE
A0
XA_14
OVDD
VDD
XA_15

Full duplex
10 Base – T
Ethernet

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: [phone] • Fax: [phone] • www.klsi.com

KL5KUSB101

USB to Ethernet Controller

3

Ver. 2.4

Pin Diagram 100LQFP

RXD

XA_7

1

VDD
100

XD_15

XD_14

OGND

XD_13

XD_12

IGND

XD_11

XD_10

XD_9

XD_8

XD_7

XD_6

XD_5

XD_4

XD_3

XD_2

XD_1

XD_0

XA_13

XA_12

XA_11

9998979695949392919089888786858483828180797877

XA_10

XA_9

XA_8
76

VDD
GND

N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

N/C
VDD
GND

PHTXD0

PHCOL

PHTXEN
PHRXER
PHRXDV
PHTXER
PHLPBK

PHUTP

TXD

UGND

VP

VM

Pin Description

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

UVDD

KL5KUSB101_L

N/C

N/C

PHCRS

X_PCLK

PHTCLK

PH_RXD0

PHRXCLK

IRQ1

IRQ2

N/C

N/C

N/C

N/C

SDA

SCL

N/C

N/C

N/C

CLK

OGND

X2

VDD

XA_15

75

XA_6

74

XA_5

73

XA_4

72

XA_3

71

XA_2

70

XA_1

69

nTST

68

nRESET

67

nXROMSEL

66

nXWR

65

nXRD

64

GND

63

nPDN

62

N/C

61

N/C

60

N/C

59

N/C

58

LED_ON

57

nXRAMSEL

56

IGND

55

nXBHE

54

A0

53

XA_14

52

OVDD

51

Pin #

QFP

1 99 IN/OUT XD_15 External Data Pins
2 100 IN VDD VDD
3 1 IN VDD VDD
4 2 GND AGND GND
5 3 N/C N/C Open connection
6 4 N/C N/C Open connection
7 5 N/C N/C Open connection
8 6 N/C N/C Open connection

9 7 N/C N/C Open connection
10 8 N/C N/C Open connection
11 9 N/C N/C Open connection
12 10 N/C N/C Open connection
13 11 N/C N/C Open connection
14 12 IN VDD VDD

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: [phone] • Fax: [phone] • www.klsi.com

Pin #

LQFP

I/O Pin Name Description

KL5KUSB101

USB to Ethernet Controller

4

Ver. 2.4

Pin #

QFP

15 13 IN GND GND
16 14 OUT PHTXD0 Transmit data to PHY
17 15 IN PHCOL Collision input from PHY
18 16 OUT PHTXEN Transmit Enable to PHY
19 17 IN PHRXER Receive Data Error from PHY
20 18 IN PHRXDV Receive Data Valid from PHY
21 19 OUT PHTXER Transmit Data Error to PHY
22 20 OUT PHLPBK Loopback input to PHY
23 21 OUT PHUTP UTP/STP input to PHY
24 22 IN/OUT TXD UART TXD
25 23 IN UGND USB GND
26 24 IN/OUT VP USB + Pin
27 25 IN/OUT VM USB – Pin
28 26 IN UVDD USB VDD
29 27 NC NC NC
30 28 NC NC NC
31 29 IN PHTXCLK PHY Transmit Clock
32 30 IN PHRXCLK PHY Receive Clock
33 31 IN PHCRS PHY Carrier Sense
34 32 IN PH_RXD0 PHY Serial Receive Data
35 33 IN/OUT X_PCLK External PCLK
36 34 IN/OUT RXD UART RXD
37 35 IN IRQ1 Edge sens. Interrupt
38 36 IN IRQ2 Edge sens. Interrupt
39 37 NC NC Open connection
40 38 NC NC Open connection
41 39 NC NC Open connection
42 40 NC NC Open connection
43 41 OUT SDA SDA / EEPROM Serial Data
44 42 OUT SCL SCL / EEPROM Serial Clock
45 43 IN PU#1 Pull up to USB + Pin for High Speed
46 44 NC NC Open connection
47 45 NC NC Open connection
48 46 IN OGND GND
49 47 IN CLK 48MHz Clock/Crystal Input
50 48 OUT X2 48MHz Crystal Output
51 49 OUT XA_15 External Address Pin
52 50 IN VDD VDD
53 51 IN OVDD VDD
54 52 OUT XA_14 External Address Pin
55 53 OUT XA0 External Address Pin
56 54 OUT nXBHE External byte High Enable (Active low)
57 55 IN IGND GND
58 56 OUT nXRAMSEL External RAM CS (Active low)
59 57 OUT LED_ON Turns on 3.3V to TX LED
60 58 N/C N/C Open connection
61 59 N/C N/C Open connection
62 60 N/C N/C Open connection
63 61 N/C N/C Open connection
64 62 OUT nPDN Active low Powerdown mode signal to Phy

Pin #

LQFP

I/O Pin Name Description

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: [phone] • Fax: [phone] • www.klsi.com

KL5KUSB101

USB to Ethernet Controller

5

Ver. 2.4

Pin #

QFP

65 63 IN GND GND
66 64 OUT nXRD External Memory Read (Active low)
67 65 OUT nXWR External Memory Write (Active low)
68 66 N/C nXROMSEL External ROM CS, active LO
69 67 IN nRESET Reset Pin
70 68 IN nTST Test Pin, Disconnect for Normal Operation
71 69 OUT XA_1 External Address Pins
72 70 OUT XA_2 External Address Pins
73 71 OUT XA_3 External Address Pins
74 72 OUT XA_4 External Address Pins
75 73 OUT XA_5 External Address Pins
76 74 OUT XA_6 External Address Pins
77 75 OUT XA_7 External Address Pins
78 76 OUT XA_8 External Address Pins
79 77 OUT XA_9 External Address Pins
80 78 OUT XA_10 External Address Pins
81 79 OUT XA_11 External Address Pins
82 80 OUT XA_12 External Address Pins
83 81 OUT XA_13 External Address Pins
84 82 IN/OUT XD_0 External Data Pins
85 83 IN/OUT XD_1 External Data Pins
86 84 IN/OUT XD_2 External Data Pins
87 85 IN/OUT XD_3 External Data Pins
88 86 IN/OUT XD_4 External Data Pins
89 87 IN/OUT XD_5 External Data Pins
90 88 IN/OUT XD_6 External Data Pins
91 89 IN/OUT XD_7 External Data Pins
92 90 IN/OUT XD_8 External Data Pins
93 91 IN/OUT XD_9 External Data Pins
94 92 IN/OUT XD_10 External Data Pins
95 93 IN/OUT XD_11 External Data Pins
96 94 IN IGND GND
97 95 IN/OUT XD_12 External Data Pins
98 96 IN/OUT XD_13 External Data Pins
99 97 IN OGND GND

100 98 IN/OUT XD_14 External Data Pins

Pin #

LQFP

I/O Pin Name Description

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: [phone] • Fax: [phone] • www.klsi.com

KL5KUSB101

USB to Ethernet Controller

6

Ver. 2.4

Function Description

16 Bit Processor

The integrated 16 bit processor serves as a micro controller for USB peripherals. The
processor can execute approximately five million instructions per second. With this
processing power it allows the design of intelligent peripherals that can process data prior
to passing it on to the host PC, thus improving overall performance of the system. The
masked ROM (4K X 16) in the KL5KUSB101 or external memory contains a specialized
instruction set that has been designed for highly efficient coding of processing algorithms
and USB transaction processing.

The 16-bit processor is designed for efficient data execution by having direct access to
the RAM Buffer, external memory, I/O interfaces, and all the control and status registers.
The divide/multiply feature expands the capability of USB peripherals.

The processor supports prioritized vectored hardware interrupts. In addition, as many as
240 software interrupt vectors are available.

The processor provides six addressing modes, supporting memory-to-memory, memory­to-register, register-to-register, immediate-to-register or immediate-to-memory
operations. Register, direct, immediate, indirect, and indirect indexed addressing modes
are supported. In addition, there is an auto-increment mode in which a register, used as
an address pointer is automatically incremented after each use, making repetitive
operations more efficient both from a programming and a performance standpoint.

The processor features a full set of program control, logical, and integer arithmetic
instructions. All instructions are sixteen bits wide, although some instructions require
operands, which may occupy another one or two words. Several special “ short
immediate” instructions are available, so that certain frequently used operations with
small constant operand will fit into a 16-bit instruction.

The Processor – Divide/Multiply function

The processor’s divide/multiply function contains all the instructions of the base
processor that additionally includes integer divide and multiply instructions. A signed
multiply an instruction take two 16-bit operands and returns a 32-bit result. A signed
divide instruction divides a 32-bit operand by a 16-bit operand.

RAM Buffer

The USB controller contains a 3K byte (1.5K X 16) internal buffer memory. The memory
is used to buffer data and USB packets and accessed by the 16 Bit processor and the
SIE. USB transactions are automatically routed to the memory buffer. The 16-bit
processor has the ability to set up pointers and block sizes in buffer memory for USB
transactions. Data is read from the interface and is processed and packetized by the 16­bit I/O processor.

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: [phone] • Fax: [phone] • www.klsi.com