Kawasaki LSI KE5BLME064 Datasheet
Version 2.5.4 Proprietary and Confidential
Longest Match Engine
KE5BLME064
Ver. 2.5.4
Kawasaki LSI U.S.A., Inc.
Version 2.5.4 Proprietary and Confidential
Table of Contents
1. Features ................................................................................................................................................ 1
2. Block Diagram ...................................................................................................................................... 2
3. Pin Assignment and Description........................................................................................................ 3
3.1. Pin Assignment: Diagram ............................................................................................................... 3
3.2. Pin Assignment: List..................................................................................................................... 4
3.3. Pin Description................................................................................................................................ 6
4. Functional Descriptions ...................................................................................................................... 9
4.1. Overview .........................................................................................................................................9
4.2. Reset............................................................................................................................................... 9
4.3. Initialization ................................................................................................................................... 10
4.4. Data Insertion................................................................................................................................ 10
4.5. Search........................................................................................................................................... 11
4.6. Data Deletion………………………………………………………………………………………...…...14
4.7. Data Insertion/Deletion Rate………………………………………….………………….…...……..….14
4.8. Search via CPU Port..................................................................................................................... 14
4.9. Interruption.................................................................................................................................... 15
4.10. Typical Operational Flow............................................................................................................... 17
4.11. Cascade Connection………………...………………………………………………………………..….17
5. SRAM................................................................................................................................................... 20
5.1. SRAM Specification ......................................................................................................................22
5.2. Connecting to SRAM .................................................................................................................... 22
6. Register ............................................................................................................................................... 23
6.1. Register Map................................................................................................................................. 23
6.2. Register Description ..................................................................................................................... 23
7. Command Description....................................................................................................................... 27
8. Package Outline ................................................................................................................................. 33
9. Electrical Characteristics .................................................................................................................. 34
9.1. Absolute Maximum Rating............................................................................................................ 34
9.2. Operating Conditions ....................................................................................................................34
9.3. DC Characteristics........................................................................................................................ 34
9.4. AC Characteristics ........................................................................................................................35
Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
Version 2.5.4 Proprietary and Confidential 1
1. Features
The KE5BLME064 provides the best solution to a high-speed route search with the
following functions:
• 64K Route Entries
The device can store 65,528-route prefixes
Each entry has 40-bit width
• Clock
Maximum Clock Frequency: 66 MHz
• Longest Match Search Capability
• Exact Match Search Capability
• Search Throughput
6.7 Mpps (packe t per sec. at 66MHz clock) (10 clocks)
• Search Latency
270 ns (hit flag; match length output) (18 clocks)
555 ns (associative data output) (37 clocks)
• Data Insertion/Deletion
534 entries/sec typical (During Search Operation) (66MHz)
400k entries/sec maximum (During initialization Operation) (66MHz)
• Triple-Port Architecture
CPU port: 16 bit
Input port: 40 bit
Output port: 18 bit
• Embedded External SRAM Control
3pcs of 2Mbits flow through type Synchronous Burst SRAM
• Cascade Connection to Increase Density
• Interface
LVTTL
• Voltage
Single 3.3V
±
0.3V Supply
• Package
416 BGA ( BGA352+TB64, TB:T hermal Ball )
• CMOS Technology
Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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2. Block Diagram
Fig. 2.1 Block Diagram
Output Port
ADD[3:0]
HON
CPU Port
SRAM1,2,3 Port
MBWD3N
MBWC3N
MBWB3N
MBWA3N
MBWE3N
MDAT3[31:0]
MCS3N
MOE3N
MADD3[15:0]
MBWD1N
MBWC1N
MBWB1N
MBWA1N
MBWE1N
MDAT1[31:0]
MCS1N
MOE1N
MADD1[15:0]
MBWD2N
MBWC2N
MBWB2N
MBWA2N
MBWE2N
MDAT2[31:0]
MCS2N
MOE2N
MADD2[15:0]
DAT[15:0]
CEN
RWN
IRQN
FLN
AMFLN
CCMPN
RSTN
Input Port
CLK
SRCHN
INP[39:0]
Registers
Control
Logic
S R A M
Control
Ins/Del
Queue
Search Table
ODONEN
OUT[17:0]
OEN
MDONEN
MLE[5:0]
MLOEN
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64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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Pin Assignment and Description
3.1 Pin Assignment: Diagram
Fig. 3.1 Pin Assignment
BOTTOM
VIEW
INDEX
TOP VIEW
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
ABCDEFGHJKLMNPRTUVWY
26
25
24
23
22
21
AFAEADACABA
A
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64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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3.2 Pin Assignment: List
No. PIN NAME I/O No. PIN NAME I/O No. PIN NAME I/O No. PIN NAME I/O
A1 GND - B19 MLOEN in D11 DAT<15> io H23 GND A2 INP<28> in B20 OUT<17> out D12 GND - H24 MADD3<10> out
A3 INP<21> in B21 OUT<16> out D13 DAT<8> io H25 MADD3<9> out
A4 INP<16> in B22 OUT<13> out D14 DAT<4> io H26 MADD3<8> out
A5 INP<12> in B23 OUT<10> out D15 VDD - J1 GND A6 INP<9> in B24 OUT<6> out D16 RSTN in J2 MADD1<1> out
A7 INP<5> in B25 GND - D17 GND - J3 MADD1<2> out
A8 INP<2> in B26 GND - D18 MLE<4> out J4 GND -
A9 IRQN out C1 INP<35> in D19 VDD - J23 VDD A10 CCMPN out C2 INP<29> in D20 GND - J24 MADD3<12> out
A11 DAT<12> io C3 INP<23> in D21 GND - J25 MADD3<11> out
A12 DAT<9> io C4 INP<18> in D22 GND - J26 VDD A13 DAT<5> io C5 INP<14> in D23 GND - K1 MADD1<3> out
A14 DAT<1> io C6 INP<11> in D24 OUT<8> out K2 MADD1<4> out
A15 DAT<0> io C7 INP<7> in D25 OUT<4> out K3 MADD1<5> out
A16 ADD<0> in C8 INP<4> in D26 OUT<1> out K4 GND A17 MLE<5> out C9 INP<0> in E1 INP<37> in K23 VDD A18 MLE<1> out C10 AMFLN out E2 INP<31> in K24 MADD3<15> out
A19 MLE<0> out C11 DAT<14> io E3 INP<25> in K25 MADD3<14> out
A20 OEN in C12 DAT<11> io E4 INP<19> in K26 MADD3<13> out
A21 OUT<15> out C13 DAT<7> io E23 MADD3<2> out L1 MADD1<6> out
A22 OUT<12> out C14 DAT<3> io E24 MADD3<1> out L2 MADD1<7> out
A23 OUT<9> out C15 ADD<3> in E25 MADD3<0> out L3 MADD1<8> out
A24 OUT<5> out C16 ADD<2> in E26 ODONEN out L4 MADD1<9> out
A25 OUT<2> out C17 RWN in F1 INP<38> in L23 GND A26 VDD - C18 MLE<3> out F2 INP<32> in L24 MDAT3<2> io
B1 INP<34> in C19 MDONEN out F3 INP<26> in L25 MDAT3<1> io
B2 VDD - C20 HON out F4 GND - L26 MDAT3<0> io
B3 INP<22> in C21 VDD - F23 VDD - M1 MADD1<10> out
B4 INP<17> in C22 OUT<14> out F24 MADD3<5> out M2 MADD1<11> out
B5 INP<13> in C23 OUT<11> out F25 MADD3<4> out M3 MADD1<12> out
B6 INP<10> in C24 OUT<7> out F26 MADD3<3> out M4 VDD -
B7 INP<6> in C25 OUT<3> out G1 INP<39> in M23 GND -
B8 INP<3> in C26 OUT<0> out G2 INP<33> in M24 MDAT3<5> io
B9 SRCHN in D1 INP<36> in G3 INP<27> in M25 MDAT3<4> io
B10 FLN out D2 INP<30> in G4 INP<20> in M26 MDAT3<3> io
B11 DAT<13> io D3 INP<24> in G23 GND - N1 MADD1<13> out
B12 DAT<10> io D4 VDD - G24 GND - N2 MADD1<14> out
B13 DAT<6> io D5 INP<15> in G25 MADD3<7> out N3 MADD1<15> out
B14 DAT<2> io D6 VDD - G26 MADD3<6> out N4 GND B15 GND - D7 INP<8> in H1 GND - N23 MDAT3<9> io
B16 ADD<1> in D8 GND - H2 OPEN - N24 MDAT3<8> io
B17 CEN in D9 INP<1> in H3 MADD1<0> out N25 MDAT3<7> io
B18 MLE<2> out D10 VDD - H4 VDD - N26 MDAT3<6> io
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64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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No. PIN NAME I/O No. PIN NAME I/O No. PIN NAME I/O No. PIN NAME I/O
P1 MBWE1N out W23 VDD - AC17 VDD - AE9 MDAT2<9> io
P2 MCS1N out W24 MDAT3<17> io AC18 VDD - AE10 MDAT2<12> io
P3 MOE1N out W25 MDAT3<16> io AC19 GND - AE11 MDAT2<15> io
P4 GND - W26 MDAT3<15> io AC20 GND - AE12 MDAT2<19> io
P23 GND - Y1 MDAT1<10> io AC21 VDD - AE13 MDAT2<22> io
P24 GND - Y2 MDAT1<11> io AC22 VDD - AE14 MDAT2<24> io
P25 MBWD3N out Y3 GND - AC23 GND - AE15 MDAT2<28> io
P26 GND - Y4 GND - AC24 MDAT3<27> io AE16 MDAT2<31> io
R1 MBWC1N out Y23 MDAT3<20> io AC25 MDAT3<26> io AE17 MBWB2N out
R2 MBWD1N out Y24 MDAT3<19> io AC26 MDAT3<25> io AE18 MBWD2N out
R3 GND - Y25 GND - AD1 MDAT1<20> io AE19 MADD2<14> out
R4 GND - Y26 MDAT3<18> io AD2 MDAT1<21> io AE20 MADD2<13> out
R23 VDD - AA1 MDAT1<12> io AD3 MDAT1<22> io AE21 MADD2<10> out
R24 MBWC3N out AA2 MDAT1<13> io AD4 MDAT1<23> io AE22 MADD2<7> out
R25 MOE3N out AA3 MDAT1<14> io AD5 MDAT1<24> io AE23 MADD2<4> out
R26 CLK in AA4 VDD - AD6 MDAT2<1> io AE24 MADD2<2> out
T1 MBWA1N out AA23 GND - AD7 MDAT2<4> io AE25 MDAT3<31> io
T2 MBWB1N out AA24 MDAT3<22> io AD8 MDAT2<7> io AE26 MDAT3<30> io
T3 MDAT1<0> io AA25 MDAT3<21> io AD9 GND - AF1 VDD -
T4 MDAT1<1> io AA26 VDD - AD10 MDAT2<13> io AF2 MDAT1<29> io
T23 MCS3N out AB1 MDAT1<15> io AD11 MDAT2<16> io AF3 GND T24 MBWA3N out AB2 MDAT1<16> io AD12 MDAT2<20> io AF4 MDAT1<30> io
T25 MBWB3N out AB3 MDAT1<17> io AD13 MDAT2<23> io AF5 MDAT1<31> io
T26 GND - AB4 VDD - AD14 MDAT2<25> io AF6 VDD -
U1 MDAT1<2> io AB23 GND - AD15 MDAT2<29> io AF7 MDAT2<2> io
U2 MDAT1<3> io AB24 GND - AD16 MOE2N out AF8 MDAT2<5> io
U3 MDAT1<4> io AB25 MDAT3<24> io AD17 MCS2N out AF9 MDAT2<8> io
U4 VDD - AB26 MDAT3<23> io AD18 MBWE2N out AF10 MDAT2<11> io
U23 GND - AC1 MDAT1<18> io AD19 MADD2<15> out AF11 MDAT2<14> io
U24 MDAT3<11> io AC2 GND - AD20 GND - AF12 MDAT2<18> io
U25 MDAT3<10> io AC3 MDAT1<19> io AD21 MADD2<11> out AF13 MDAT2<21> io
U26 MBWE3N out AC4 GND - AD22 MADD2<8> out AF14 GND -
V1 GND - AC5 GND - AD23 MADD2<5> out AF15 MDAT2<27> io
V2 MDAT1<5> io AC6 GND - AD24 GND - AF16 MDAT2<30> io
V3 MDAT1<6> io AC7 GND - AD25 MDAT3<29> io AF17 MBWA2N out
V4 VDD - AC8 VDD - AD26 MDAT3<28> io AF18 MBWC2N out
V23 MDAT3<14> io AC9 MDAT2<10> io AE1 MDAT1<25> io AF19 GND V24 MDAT3<13> io AC10 GND - AE2 GND - AF20 MADD2<12> out
V25 MDAT3<12> io AC11 MDAT2<17> io AE3 MDAT1<26> io AF21 MADD2<9> out
V26 GND - AC12 VDD - AE4 MDAT1<27> io AF22 MADD2<6> out
W1 MDAT1<7> io AC13 GND - AE5 MDAT1<28> io AF23 MADD2<3> out
W2 MDAT1<8> io AC14 MDAT2<26> io AE6 MDAT2<0> io AF24 MADD2<1> out
W3 MDAT1<9> io AC15 GND - AE7 MDAT2<3> io AF25 MADD2<0> out
W4 GND - AC16 GND - AE8 MDAT2<6> io AF26 VDD -
Table 3.1 Pin Assignment (cont’d)
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64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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3.3 Pin Description
Pin Name Attribute Description #of
Pins
CLK Clock CLK is the master clock input. Input 1
Input signals refer to the rising edge of CLK.
LVTTL
SRCHN Search Enable SRCHN enables a search operation; 1
Input search commences when Low is
LVTTL signaled.
INP Input Bus INP<39:0> is a 40-bit input bus used 40
<39:0> Input search key inputs.
LVTTL
OUT Output Bus OUT<17:0>, a 18-bit output bus, 18
<17:0> Output outputs the associate data.
LVTTL
OEN Output Enable OEN controls OUT<17:0>. OEN 1
Input Low enables OUT<17:0> ; and OEN
LVTTL High enables High-Z.
ODONEN Output DONE ODONEN Low Active indicates that 1
Output the associate data is output to the OUT
LVTTL <18:0> after a search.
HON Hit Output HON outputs a search result. 1
Output Low indicates a hit; High indicates a
LVTTL miss hit.
MLE Match Length MLE outputs match-length 6
<5:0> Output information (prefix lengh-1) between
LVTTL the data stored in the table and the
relevant search key.
MLOEN Match Length Output Enable MLOEN controls MLE<5:0> Output 1
Input Enable. Low enables MLE<5:0>;
LVTTL High changes it to High-Z.
MDONEN MLE Done MDONEN Low indicates that the 1
Output completion of the search, outputting
LVTTL the match length to MLE<5:0>.
RSTN Reset RSTN input Low resets the hardware. 1
Input
LVTTL
IRQN Interrupt Request IRQN indicates Low when an interrupt 1
Output condition occurs in the CNTL register.
Open Drain
CCMPN Command Execution Completion CCMPN signals High during the 1
Output command operation executed via CPU
LVTTL port, and signals Low upon the
completion of its execution.
ADD CPU Port Address ADD<3:0> is a register address. 4
<3:0> Input
LVTTL
DAT CPU Port Data Bus DAT<15:0> is an input/out put data bus 16
<15:0> Input/Output for a CPU port.
LVTTL
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64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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Pin Name Attribute Description #of
Pins
CEN CPU Port Enable CEN serves as the CPU port access; CEN 1
Input Low enables the input operations of data
LVTTL and command.
RWN Read/Write RWN determines the direction of the CPU 1
Input bus; RWN Low selects “write” cycle,
LVTTL and RWN High “read” cycle.
FLN Full FLN outputs Low when all entries are 1
Output filled with valid data.
LVTTL
AMFLN Almost Full AMFLN outputs Low when reaching 1
Output “almost full”; the number of entries is
LVTTL equal to or exceeds the value stored in
the Almost Full Register.
MADD1 SRAM1 Address MADD1 is SRAM1 address output. 16
<15:0> Output Ensure that it is connected to SRAM1
LVTTL address pins.
MDAT1 SRAM1 Data Bus MDAT1 is a bi-directional Bus for 32
<31:0> Input/Output SRAM1. Ensure that it is connected to
LVTTL SRAM1 data pins.
MCS1N SRAM1 Chip Enable MCS1N is SRAM1 chip enable signal. 1
Output Ensure that it is connected to SRAM1
LVTTL chip enable.
MOE1N SRAM1 Output Enable MOE1N is SRAM1 Output Enable signal. 1
Output Ensure that it is connected to SRAM1
LVTTL output enable input.
MBWE1N SRAM1 Byte Write Enable MBWE1N is SRAM1 Byte Write Enable 1
Output signal. Ensure that it is connected to
LVTTL SRAM1 Byte write enable input.
MBWA1N SRAM1 Synchronous Byte Write Enable MBWA1N is SRAM1 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM1 Synchronous Byte write enable A input.
MBWB1N SRAM1 Synchronous Byte Write Enable MBWB1N is SRAM1 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM1 Synchronous Byte write enable B input.
MBWC1N SRAM1 Synchronous Byte Write Enable MBWC1N is SRAM1 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM1 Synchronous Byte write enable C input.
MBWD1N SRAM1 Synchronous Byte Write Enable MBWD1N is SRAM1 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM1 Synchronous Byte write enable D input.
MADD2 SRAM2 Address MADD2 is SRAM2 address output. 16
<15:0> Output Ensure that it is connected to SRAM2
LVTTL address pins.
MDAT2 SRAM2 Data Bus MDAT2 is a bi-directional Bus for SRAM2. 32
<31:0> Input/Output Ensure that it is connected to SRAM2
LVTTL data pins.
MCS2N SRAM2 Chip Enable MCS2N is SRAM2 chip enable signal. 1
Output Ensure that it is connected to SRAM2
LVTTL chip enable.
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Pin Name Attribute Description #of
Pins
MOE2N SRAM2 Output Enable MOE2N is SRAM2 Output Enable signal. 1
Output Ensure that it is connected to SRAM2
LVTTL output enable input.
MBWE2N SRAM2 Byte Write Enable MBWE2N is SRAM2 Byte Write Enable 1
Output signal. Ensure that it is connected to
LVTTL SRAM2 Byte write enable input.
MBWA2N SRAM2 Synchronous Byte Write Enable MBWA2N is SRAM2 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM2 Synchronous Byte write enable A input.
MBWB2N SRAM2 Synchronous Byte Write Enable MBWB2N is SRAM2 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM2 Synchronous Byte write enable B input.
MBWC2N SRAM2 Synchronous Byte Write Enable MBWC2N is SRAM2 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM2 Synchronous Byte write enable C input.
MBWD2N SRAM2 Synchronous Byte Write Enable MBWD2N is SRAM2 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM2 Synchronous Byte write enable D input.
MADD3 SRAM3 Address MADD3 is SRAM3 address output. 16
<15:0> Output Ensure that it is connected to SRAM3
LVTTL address pins.
MDAT3 SRAM3 Data Bus MDAT3 is a bi-directional Bus for SRAM3. 32
<31:0> Input/Output Ensure that it is connected to SRAM3
LVTTL data pins.
MCS3N SRAM3 Chip Enable MCS3N is SRAM3 chip enable signal. 1
Output Ensure that it is connected to SRAM3
LVTTL chip enable.
MOE3N SRAM3 Output Enable MOE3N is SRAM3 Output Enable signal. 1
Output Ensure that it is connected to SRAM3
LVTTL output enable input.
MBWE3N SRAM3 Byte Write Enable MBWE3N is SRAM3 Byte Write Enable 1
Output signal. Ensure that it is connected to
LVTTL SRAM3 Byte write enable input.
MBWA3N SRAM3 Synchronous Byte Write Enable MBWA3N is SRAM3 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM3 Synchronous Byte write enable A input.
MBWB3N SRAM3 Synchronous Byte Write Enable MBWB3N is SRAM3 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM3 Synchronous Byte write enable B input.
MBWC3N SRAM3 Synchronous Byte Write Enable MBWC3N is SRAM3 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM3 Synchronous Byte write enable C input.
MBWD3N SRAM3 Synchronous Byte Write Enable MBWD3N is SRAM3 Synchronous Byte Write 1
Output Enable signal. Ensure that it is connected to
LVTTL SRAM3 Synchronous Byte write enable D input.
VDD Supply The voltage required is 3.3V. 24
GND Ground Ground pin. 49
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64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
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4. Functional Descriptions
4.1 Overview
KL5BLME064 is a search device for 40-bit IP address searches in IP routing
applications. Its capability extends beyond a simple lookup of data entries stored in a
routing table. With its compatibility with the CIDR (Classless Inter-Domain Routing), it
outputs associated data for the longest match dat a w hen there ar e mul ti pl e matchi ng
entries. KE5BLME064 also ha s the search capability of finding the exact 40-bit match
for searching the host address.
Moreover, LME064 provides a solution to routes having the same address with different
prefix length. Let us assume, for instance, the presence of both 0.192.1.0.0/24 and
0.192.1.0.0/32 in a routing table; the search key of 0.192.1.1.2 outputs associated data
relative to 0.192.1. 0.0/2 4 whereas the search key of 0.192.1.0.3 outputs ones rel ative to
0.192.1.0.0/32.
KL5BLME064 is a triple-port architecture equipped with task-specific ports: Input port
conducting a search, Output port effecting a result, and CPU port executing commands
and accessing to a register. This triple-port architecture facilities insertion and
deletions of entries without interrupting a search operation.
In order to store data, LME064 operates with 3pcs of 2Mbits SRAM.
4.2. Reset
The LME064 device requires a reset after chip power up. A reset can be applied by
either supplying a low pulse to the RSTN pins or writing any data onto a Reset register.
The values reassigned for both pins and registers are as follows:
Registers Pins
CNTL: 0000000b IRQN: High-Z
STAT0: 1x00b FLN: High
STAT1: 0000000b AMFLN: High
PR0 – RR2: Unknown CCMPN: Low
Almost Full constant: 7FFFh ODONEN: High
Default Associate Data: Unknown MDONEN: High
Entry Counter constant: 0000h HON: High
MCS#N: High
MOE#N: Low
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MBWE#N: High
MBWA#N High
MBWB#N High
MBWC#N High
MBWD#N High
(#: 1, 2, 3)
4.3. Initialization
When the Initialize command is executed, insertion / de le tion Queue and search table
are initialized, Entry Counter constant becomes 0000h. This command is suitable for
constructing a new search table.
As in using other command, before proceeding with the subsequent commands, check
anew by monitoring the CCMPN pin whether the initialization process has been
completed.
4.4. Data Insertion
To enter data in the table, use the Insert command. Ensure that the IP address is set
to WR0-2, the associated data(ASD) to WR3-4, and PL (prefix length –1) to WR2.
Example:
When inserting 0.192.1.2.0/32 with associated data 34 56h, enter the f ollowing.
WR0: IP[15:0] 0200h (2.0)
WR1: IP[31:16] C001h (192.1)
WR2: 2’bxx, PL[5:0], IP[39:32] 1F00h (31=32-1.0)
WR3: ASD[15:0] 3456h
WR4: 14’bx..x, ASD[17:16] 0000h
Ensure that the value entered in WR2 is the prefix-length minus 1, not the prefixlength itself. Please put the value of 0 in the host address part.
The completion of the Insert command is confirmed by a low signal on the CCMPN pin.
Proceed with the subsequent commands after checking the CCMPN status.
Actually, the data is acknowledged as the data of the search table within 20 clocks after
the Insert command is issued and the Entry Counter is increased before the completion
of the Insert command.
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Notes:
l Even if the signal of the CCMPN pin becomes low level on the completion of
the Insert command, the inserted data is not stored in the search table and the
Entry Counter is not increased when the search table is full (the signal of FLN
pin is low).
l The entry counter does not i ncrease when IP address and PL (pre fix l eng th - 1)
of the inserted data are the same as that of the retrieval table on the
completion of the Insert command.
l These status are known as the value of STAT1 register.
LME064 is capable of storing the exact data match, i.e., the entry data hitting only when
all the 40 bits coincide with the input key data. When inserting exact match data, set
39 to WR2 (PL[5:0]) because this device considers the prefix length to be a range of the
retrieval. This particular function is useful for storing the host address in the table.
4.5. Search
To conduct a longest match search, apply data to INP [39:0], and set a SRCHN pin Low
(see Fig.4.1). At the 18th clock after starting a search, MDONEN will be changed to
Low, allowing both MLE [5:0] and HON to output. MLE [5:0] output should be equal to
the match length minus one. That is to say, MLE [5:0] is the maximum value of the
match length of a search key minus 1. The HON status indicates a lookup result, with
Low a hit, and High as a miss hit. MDONEN will revert from High to Low after 4 clock
cycles, while both MLE [5:0] and HON will be held until the next loo kup result.
At the 37th clock after starting a search, ODONEN will be changed into Low, allowing
OUT [17:0] to output associated data. If the search results in a miss match, the value
pre-registered at the default ass ociated data will be ret urned and MLE [5:0] outp ut is 00h.
ODONEN will revert from High to Low after 4 clock cycles, whereas OUT [17:0] will be
held until the next result. For instance, let us assume the presence of the following
data in the table:
0.133.5.0.0/24 [associated data: 01111h]
0.133.5.16.0/32 [associated data: 02222h]
Cf. Default associated data: 00000h
Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
Version 2.5.4 Proprietary and Confidential 12
The result is as follows:
Search Key Result HON status MLE[5:0] OUT[17:0]
0.133.5.16.2 Hit at
0.133.5.16.0/
32
Low 31 (1Fh) 02222h
0.133.5.17.3 Hit at
0.133.5.0.0/2
4
Low 23 (17h) 01111h
0.133.6.0.1 Miss hit* High 0 00000h
Note: “*”
indicates that0.133.5.0.0 and 0.133.6.0.1 have the matching length of
22bits; a miss hit occurs because the matching length is shorter than
the registered value of “24.”
Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
Version 2.5.4 Proprietary and Confidential 13
CLK
SRCHN
INP<39:0>
HON
MDONEN
MLE<5:0>
ODONEN
OUT<17:0>
37 Clocks
4 Clocks
Key1 Key2
Search result of Key 1
Search result of Key 1
Search result of Key 1
Search result of Key 2
Search result of Key 2
Search result of Key 2
10 Clocks min.
4 Clocks
18 Clocks
18 Clocks
37 Clocks
Fig. 4.1 Search Timing
Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064) PRELIMINARY
Version 2.5.4 Proprietary and Confidential 14
4.6. Data Deletion
To delete data from the table, use the Delete command. Ensure that the IP address is
set to WR0-2, and PL to WR2 with a prefix-length minus 1 before executing the
commands.
Example:
If deleting 0.192.1.2.0/32, set the registers as follows.
WR0: IP[15:0] 0200h (2.0)
WR1: IP[31:16] C001h (192.1)
WR2: 2’bxx, PL[5:0], IP[39:32] 1F00h (31=32-1.0)
The completion of the Delete command will be confirmed by a low status of CCMPN pin.
Before proceeding with the subsequent commands, check anew to confirm that the
Delete command execution has finished.
Actually, the data is acknowledged as the deleted data of the search table within 20
clocks after the Delete command is issued and the Entry Counter is decreased before
the completion of the Delete command.
Notes:
l Ensure that the value set to WR2 is the prefix-length minus 1, not the prefix-
length itself. No deletion can be performed if the value entered to WR2 differs
from that of the initial entry, that is the prefix-length minus 1, and the Entry
Counter is not decreased.
l Even if the signal of the CCMPN pin becomes low level on the completion of
the Delete command, no deletion can be performed if the value entered to
WR0-2 differs from that of the search table entry and the Entry Counter is not
decreased.
l These status are known as the value of STAT1 register.
4.7. Data Insertion/Deletion Rate
The maximum Insertion rate is about 400k entries per second (at 66Mhz system clock
operation) after the Initialize command is executed. This rate is performed on the
condition that each new IP address data is sequentially inserted from the small one to
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