Kawasaki LSI KE5BCCA9M Datasheet

Kawasaki LSI
9M Classification CAM PRELIMINARY

Version 1.2.0 Confidential

Contents

1. Features.........................................................................................1

2. Block Diagram...............................................................................2

3. Pin Descriptions ...........................................................................4

3.1. Pin Assignment (T.B.D.)..............................................................................4

3.2. Pin Descriptions..........................................................................................4

4. Functional Descriptions...............................................................7

4.1. Overview.....................................................................................................7

4.2. Segment Structure......................................................................................7

4.3. Output Format.............................................................................................7

4.4. CAM Table Example....................................................................................8

4.5. CNTL Bus (CNTL[15:0])..............................................................................9

4.6. Timing Chart..............................................................................................10

5. Command Descriptions..............................................................13

6. Register.......................................................................................15

7. Product Information ...................................................................15

7.1. Ordering Information.................................................................................15

7.2. Package Outline........................................................................................15

8. Electrical Characteristics...........................................................16

8.1. Absolute Maximum Rating ........................................................................16

8.2. Operating Range.......................................................................................16

8.3. DC Characteristics....................................................................................16

Kawasaki LSI
9M Classification CAM PRELIMINARY

Version 1.2.0 1 Confidential

1. Features

Kawasaki’s KE5BCCA9M is a high-performance Content Addressable Memory (CAM). The
following features enable high-speed and high-density “switching," “address filtering,” and "packet
classification" applications required for internetworking switching and routing:

•

Density: 9.4Mbits Ternary or Binary

•

Configurable table Size:
72-bit x 128K, 144-bit x 64K, 288-bit x 32K, or 576-bit x 16K(Ternary or Binary)

•

Mixed table size configuration:
Selected by each bank (8banks). Each bank can be individually configured as a 72-bit x 16K,

144-bit x 8K, 288-bit x 4K, or 576-bit x 2K(Ternary or Binary) table.

•

Input Clock rate: 83MHz/100MHz/125MHz clock (CLK)

•

High-speed search and deterministic latency:

-125: Sustained 125MLPS, (maximum key data width T.B.D.), (latency T.B.D.)

-100: Sustained 100MLPS, 10ns per 144-bit maximum, (latency T.B.D.)

- 83: Sustained 83MLPS, 12ns per 144-bit maximum, 3 cycles latency

•

Dual-port architecture

•

72-bit I/O Port Data Bus:
144-bit per 8(T.B.D.)/10/12ns write-in throughput is possible. 72-bit I/O port data bus is also

configurable as a 40-bit wide bus.

•

24-bit Output Port: Search results are output

•

Multi-hit support (Highest Hit Address output)

•

18 x 72-bit Global MASK Registers

•

Weighted Search without data sorting

•

Effective Command Set for Table Management:

- Purge (Invalidate) all the hit entries in one Cycle

- Automatic Learning

•

Cascading:
Up to 8pcs --- Glueless without degradation in performance --- 72-bit x 512k table
Cascadable up to 32pcs --- Maximum 72-bit x 2M table

•

External SRAM direct connection (Address bypass to SRAM)

•

Space-saving package: 324-pin BGA (27mm x 27mm)

•

Power supply: 1.2V (core), 2.5V or 1.8V(I/O) --- Selectable I/O voltage (T.B.D.)

Kawasaki LSI
9M Classification CAM PRELIMINARY

Version 1.2.0 2 Confidential

2. Block Diagram

Fig. 2-1 Functional Block Diagram

CEN

RWN

SAD

CLK

RSTN

OEDATN

DAT[63:0]

EDAT[7:0]

DATWDT

CNTL[15:0]

PHOUN[1:0]

PHODN[1:0]
PMIN

PMON
FLIN[6:0]

FLON[1:0]

BHIDN
BHODN

BHIUN
BHOUN

BFLIN
SSHON

SMON

ODBYP
OEODN

OD[23:0]

PHIUN[6:0]

PHIDN[6:0]

INPMD

LMSTN

I/O

Port

Control

Control and

Status Registers

Pipeline

Execution

Control

Global Mask

Registers

CAM Control

Decoder

72bits x 131072

CAM

8 Banks

(72bitsx16Kx8)

structure

Mixable with

72bits x 16384

144bits x 8192
288bits x 4096
576bits x 2048

Empty Bit

Flag Control Output Port Control

Priority Encoder

Kawasaki LSI
9M Classification CAM PRELIMINARY

Version 1.2.0 3 Confidential

Kawasaki’s KE5BCCA9M has the following components:

•

I/O Port Control
I/O port to input search key data and read/write data. I/O port data bus can be configured as a

72-bit or 40-bit wide bus.

•

Pipeline Execution Control
Controls operation with pipeline through the CNTL [15:0].

•

Control/Status Register
Defines CAM functions.

•

Mask Registers
18 Global Mask Registers in total: 16 72-bit wide user-definable registers and 2 fixed registers

(ALL 0 and ALL 1) for search and write operations.

•

Search Logic/Control Logic
Controls CAM functions.

•

CAM

72-bit x 128k CAM data table partitioned into 8 banks. Each of which can be configured as

ternary or binary and in table width of 72-bit, 144-bit, 288-bit, or 576-bit. The search operations
can be performed simultaneously on multiple banks. By way of these features, various kinds of
data for Layer-2, 3 and 4 can be stored in one device and managed in different ways.

•

Output Port Control
Controls output port, which outputs search results. The DAT data bypass function is provided

for the external SRAM access through this CAM device.

•

Flag Logic
Controls the flag status (e.g. Full and Hit). Interfaces with other devices in a cascaded system.

When the CAM table is divided into multiple blocks, the status of the searched block is output.

Kawasaki LSI
9M Classification CAM PRELIMINARY

Version 1.2.0 4 Confidential

3. Pin Descriptions

3.1. Pin Assignment (T.B.D.)

Pin assignment is backward compatible with 4.7M CAM (KE5BCCA4M). OD[23] is assigned to the
NC pin of 4.7M CAM, and CNTL[15:14] to the GND pins.

VDDQ (I/O): 2.5V or 1.8V --- Selectable I/O voltage (T.B.D.)
VDD (core): 1.2V

3.2. Pin Descriptions

Pin Name Description Attribute Function
RSTN Hardware Reset Input RSTN low resets the device.

CLK Clock Input CLK is the clock input. All operations are synchronized with CLK.

The internal PLL generate the double rate clock of CLK, called
CLKX2 and all input signals are referenced to the CLKX2.

INPMD Input Mode Input When all input signals are referenced to only CLK rising edge;

not falling edge, fix INPMD high.

DAT[63:0] I/O Port

Data Bus

Input/
Output
Tristate

DAT[63:0] is a 64-bit bi-directional data bus for read/write of
CAM memory and registers. RWN controls the bus direction.

EDAT[7:0] EXTRA Bit Data

Bus

Input/
Output
Tristate

EDAT[7:0] is a 8-bit bi-directional data bus for read/write of
EXTRA bits of CAM memory and registers. RWN controls the
bus direction.

DATWDT I/O Port Data Bus

Width

Input DATWDT defines DAT[63:0] width. Fix low to employ all

DAT[63:0]; fix high not to employ DAT[63:32] and to employ
DAT[31:0] with SAD as a substitute for DAT[63:0].

CNTL[15:0] Control Bus Input CNTL[15:0] is the 16-bit control bus to control the device. The

search operations, the command assertions, and the register
accesses are invoked corresponding to CNTL[15:0].

SAD Sub Address Input SAD assigns DAT[31:0] to internal 64-bit data bus when

DAT[63:32] is unused (DATWDT=high). When SAD is low,
DAT[31:0] is assigned to lower 32-bit; when high, it is assigned
to upper 32-bit.

CEN Device Enable Input CEN low invokes operations such as read/write, search and

command.

RWN Read/Write Input RWN determines the direction of the I/O Port data bus

DAT[63:0] and that of the EXTRA bit data bus EDAT[7:0]. RWN
low selects a write cycle and RWN high selects a read cycle.

OEDATN I/O Port Data Bus

Output Enable

Input OEDATN is output enable signal for DAT[63:0] and EDAT[7:0].

This signal is also referenced to CLK rising edge.