Kaskod CANPC527D User Manual

CANPC527D Isolated 1 Mb/s

Full CAN Interface Board

User,s Manual

KASKOD

1999

Sankt-Peteterburg

189625, S-Petrsburg, Pavlovsk,
Filtrovskoy road, 3
tel.: [phone]
Fax: [phone]

E-mail : [e-mail]

[e-mail]

http://www.kaskod.ru

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CANPC527D

INTRODUCTION 2

CAN bus controller 2
Physical interface 2
Mechanical description 2
Connector description 2
T erminal resistors 3
What comes with your board 3
Board accessories 3

CHAPTER 1 - BOARD SETTINGS 4

Base address jumpers 5
Interrupt request number 5

CHAPTER 2 - BOARD INSTALLATION 6

Board installation 6

CHAPTER 3 - HARDWARE DESCRIPTION 7

CANPC527D CAN bus controller 7
Galvanic isolation of the CAN bus 8

CHAPTER 4 - BOARD OPERATION AND PROGRAMMING 9

Defining the memory map 9
Interrupts 9

What is an interrupt 9
Interrupt request lines 9
8259 Programmable interrupt controller 9
Interrupt mask register (IMR) 9
End-Of-Interrupt (EOI) Command 10
What exactly happens when an interrupt occurs? 10
Using interrupt in your program 10
Writing an interrupt service routine (ISR) 10
Saving the startup IMR and interrupt vector 12
Common Interrupt mistakes 12

APPENDIX A - CANPC527D Specification 14

APPENDIX B. What is CAN Interface? 15

APPENDIX C. Architectural Overlview 26

Table of Contents Page

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CANPC527D

This user‘s manual describes the operation of the CANPC527D Can-bus interface board.

Some of the key properties of the CANPC527D include:

l 1 Mb/s maximum datarate (fully programmable)
l Full CAN-functionally 2.0 B
l Intel 82527 CAN-bus controller
l Galvanically isolated physical interface with CAN transceiver
l +5V only operation

The following paragraphs briefly describe the major features of the CANPC527D. A more de­tailed discussion is included in Chapter 3 (Hardware description) and in Chapter 4 (Boad opera­tion and programming). The boad set-up is described in Chapter 1 (Board Setting). A full descrip­tion of the Intel 82527 CAN-controller is included in Chapter 4.

CAN-bus controller

The CANPC527D CAN-bus interface is implemented using the Intel 82527 chip. This controller
supports CAN Specification 2.0B. This versatile chip supports standard and extended Data and
remote frames as follows: A Programmable Global Message Identifier Mask; 15 message objects of
8-byte Data Length and a Programmable Bit Rate. This fully integrated chip supports all the functinality
of the CAN-bus protocol.

Physical Interface

Industrial environments require galvanic isolation and bus filtering to provide reliable data
communication and safety. CANPC527D has option for the physical interface.

The galvanically isolated physical interface is implemented using high speed optocouplers and a
DC/DC converter. T o protect the input from radiated bus noise a special balanced bus filter is
used. This filter is designed to meet EMI requirements.

Mechanical description

The CANPC527D is designed on a ISA form factor. An easy mechanical interface to both PC/104 and
EUROCARD systems can be achieved. PUT your CANPC527D directly on a ISA compatible computer
using the onboard mounting holes.

Connector description

For the switching on two identical connectors are used P1 (channel 1) and P2 (channel 2).
Pinout is as follows:

TABLE 1-1

contact signal

1nc

2 BUS_L

3 GND

4nc

5nc

6nc

7 BUS_H

8nc

9 VCC

INTRODUCTION

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Explanation:

n c – not connected (may be used anyhow)
BUS_L – bus active low ( relatevely GND)
BUS_H – bus active high ( relatevely GND)
GND – may be not used
VCC – power supply voltage +5V (in this version is not used)

Terminal Resistors

CAN Standard implies terminal resistors at the end-nodes of the net. If in your specific configuration
channel 1 is the end-node, then setting of J2 is needed, if it is channel 2 then J3.

What commes with your board

Y ou will receive the following items in youe CANPC527D package:

lCANPC527D CAN-bus interface module
l Software diskette with C source code for CAN bus interfacing for DOS
l User‘s manual

Board accessories

In addition to the items included in your CANPC527D delivery , several software and hardware accesso­ries are available. Call your distributor for more information on these accessories and for help in choosing
the best items to support your distributed control system.

l Application software

Third party high level protocol drivers
WIN 95/98 and WIN NT drivers and driver source code

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The CANPC527D CAN bus interface board has jumper settings which can be changed to
suit your applicacation and host computer memory configuration. The factory setting are
listed and shown in the diagram in the beginning of this chapter.

Fig.1

CANPC527D contains 2 identical optoisolated CAN 2.0B specification channels. First chan­nel registers begin from base address, the second - base address+100h. Each channel can
generate its interrupt request with its interrupt vector, or both channels can use one vector.
In this case interrupt request program must process both chanels simultaneously.

CHAPTER 1 - BOARD SETTING

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Base Address Jumpers

For base address setting J2 is used.
J2 consists of 11 sections, and each section is associated with its address line.

Note: Section 0 (connectors 1-2) is reserved for S version.

Sections are arranged as following:

TABLE 1-2

Section 0 (connectors 1-2)  reserved

Section 1 (connectors 3-4)  A9

Section 2 (connectors 5-6  A10

Section 3 (connectors 7-8  A11

Section 4 (connectors 9-10)  A12

Section 5 (connectors 11-12)  A13

Section 6 (connectors 13-14)  A14

Section 7 (connectors 15-16)  A15

Section 8 (connectors 17-18)  A16

Section 9 (connectors 19-20)  A17

Section 10 (connectors 21-22)  A18

Thus base address possible range setting is: 080000h-0FFE00h.
Explanation: Board starts working when address line signal A19 is set high. Connection corresponds

to high level.

Examples:

To set base address 0C8000h - connect 21 and 22 in Section10, 15 and 16 in Section 7
(FACTOR Y SETTING).
T o set base address 0D1E00h -

connect 21 and 22 in Section 10, 17 and 18 in Section 8
connect 1 and 2 in Section 1 3 and 4 in Section 2

connect 5 and 6 in Section 3, 7 and 8 in Section 4

Interrupt request number setting

J4, J5 is used for the selection of interrupt request.
J4, J5 consists of 11 sections.
Followin interrupts are available

Channel number J4 J5

resistor insert 1-2 1-2
15 3-4 3-4

14 5-6 5-6
12 7-8 7-8
1 1 9-10 9-10
10 11-12 11-12
7 13-14 13-14
6 15-16 15-16
5 17-18 17-18
4 19-20 19-20

3 21-22 21-22

Other setting of jumpers switch off the interrupt requests.

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Board Installation

Keep your board in its antistatic bag until you are ready to install it to your system! When removing it from
the bag, hold the board at the edges and do not touch the components or connectors. Please handle the
board in an antistatic environment and use a rounded workbench for testing and handling of your hardware.

Before installing the board in your computer, check the jumper setting. Chapter 1 reviews the
factory settings and how to change them. If you need to change any setting, refer to the appropri­ate instructions in Chapter 1. Note that incompatible jumper settings can result in unpredictable
board operation and erratic response.

General installation guidelines:

1. Turn OFF the power to your computer and all devices connected to CANPC527D

2. T ouch the grounded metal housing of your computer to discharge any antistatic buildup and
then remove the board from its antistatic bag.

3. Hold the board by the edge and install it in an enclosure or place it on the table on an antistatic
surface.

4. Connect the board to the CAN fieldbus interface header connectors. Make sure the polarity of
the cable is correct. Both connectors are identical, one of these headers may be used to bring the
CAN bus to the one channel; the other connector interfaces for second channel.

CHAPTER 2 - BOARD INSTALLATION

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Chapter 3 - Hardware discription describes the major features of the CANPC527D: the Intel 82527
CAN bus controller, Galvanic isolation of the CAN-bus.

Figure 3-1 shows the general block diagram of the CANPC527D. This chapteer describes the major
features of the CANPC527D: the Intel 82527 CAN-bus controller, Galvanic isolation of the CAN-bus,
the Fiberoptic interface, the Onboard configuration EEPROM, and Digital I/O.

Fig. 3-1. CANPC527D Block diagram

82527 CAN bus controller

Reference note:

(Intel publication CAN Architectural Overview , Automotive Products Databook)

The 82527 CAN controller consists of six functional block. The CPU interface logic manages the
communication to the host computer. The CAN controller interface to the CAN bus and implements the
protocol rules of the CAN protocol for the transmission and reception of messages. The RAM is the
physical interface layer between the host CPU and the CAN bus. One eight bit I/O port provides low
speed I/O capabilities.

The 82527 RAM provides storage for 15 message objects of 8 byte length. Each message object has a
unique identifier and can be configured to either transmit of to receive except for the last message object.
The last message object is a receive-only buffer with a special mask design to allow selected groups of
different message identifiers to be received.

Each message identifier contains control and status bits. A message object with a direction set for receive
will send a remote frame by requesting a message transmission. A message set as transmit will be configured
to automatically send a data frame whenever a remote frame with a matching identifier is received over the
CAN bus. All message objects have separate transmit and receive interrupt and status bits, allowing the
CPU full flexibility in detecting when a remote frame has been sent or received.

CHAPTER 3 - HARDWARE DESCRIPTION