JVC XVM-50-BK Service manual
A0008B200211
XV-M50BK
SERVICE MANUAL
DVD VIDEO PLAYER
XV-M50BK
Supplement
Because service manual XV-M50BK (Issue No.A0008)
which has already been issued contains some mistakes,
the following pages are modified in this service manual.
< Modified pages >
*Description of major ICs
*Block diagrams
Refer to the service manual XV-M50BK (Issue No. A0008)
which has already been issued for other pages.
Area Suffix
J ------------- U.S.A.
C ---------- Canada
TABLE OF CONTENTS
1 Description of major ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
COPYRIGHT © 2002 VICTOR COMPANY OF JAPAN, LTD.
No.A0008B
2002/11
XV-M50BK
1.1 AK93C65AF-X (IC403) : EEPROM
• Pin layout
• Block diagram
SECTION 1
Description of major ICs
• Pin function
Pin no. Symbol Function
1 PE Program enable (With built-in pull-up resistor)
2 VCC Power supply
3 CS Chip selection
4 SK Cereal clock input
5 DI Cereal data input
6 DO Cereal data output
7 GND Ground
8 NC No connection
NOTE :
The pull-up resistor of the PE pin is about 2.5Mohm (VCC=5V)
2
1.2 AN8702FH(IC101):Frontend processor
• Pin layout
• Pin function
Pin No. Symbol I/O Description
1 PC1 I Input for Laser current monitor
2 PC01 O Laser power control output for DVD
3 PC2 I Photo detector fo CD
4 PC02 O Laser power control output for CD
5 TGBAL I Tangential phase balance control terminal
6 TBAL I Tracking balance control terminal
7 FBAL I Focus balance control ter
8 POFLT O Track detection threshold level terminal
9 DTRD I Data slice part data read signal input terminal (For RAM)
10 IDGT I Data slice part address part gate signal input terminal (For RAM)
11 STANDBY I Standby mode control terminal
12 SEN I SEN(Serial data input terminal)
13 SCK I SCK(Serial data input terminal)
14 STDI I STDI(Serial data input terminal)
15 RSEL I DVD and CD selection
16 JLINE I J-line setting output (FEP)
17 TEN I Tracking error output amplifier reversing input terminal
18 TEOUT O Tracking error signal output terminal
19 ASN I Off set adjustment terminal for DRC
20 ASOUT O All added signal output terminal
21 FEN I Focus error output amplifier reversing input terminal
22 FEOUT O Focus error signal output terminal
23 VSS - Connect to GND
24 TG O Tangential phase error signal output terminal
25 VDD - Power supply terminal 3V
26 GND2 - Connect to GND
27 VREF2 O VREF2 voltage output terminal
28 VCC2 - Power supply terminal 5V
29 VHALF O VHALF voltage output terminal
30 DFLTON O Filter amplifier reversing output terminal
31 DFLTOP O Filter amplifier output terminal
32 DSFLT O Connected capacitor terminal for filter output
33 GND3 - Connect to GND
34 RFDIFO O RF operation output terminal
35 RFOUT O RF output terminal
36 VCC3 - Power supply terminal 5V
37 RFC I Filter for RF amplifier
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XV-M50BK
Pin No. Symbol I/O Description
38 DCRF O All addition amplifier capacitor terminal
39 OFTR O OFTR output teminalr
40 BDO O BDO output terminal
41 RFENV O RF envelope output terminal
42 BTTOM O Bottom envelope detection filter terminal
43 PEAK O Peak envelope detection filter terminal
44 AGCG O AGC amplifier gain control teminalr
45 AGCO O AGC amplifier level control terminal
46 TESTSG I TEST signal input terminal
47 RFINP I RF signal positive input terminal
48 RFINN I RF signal negative input terminal
49 VIN5 I RF input of external division into 4 terminal for CD
50 VIN6 I RF input of external division into 4 terminal for CD
51 VIN7 I RF input of external division into 4 terminal for CD
52 VIN8 I RF input of external division into 4 terminal for CD
53 VIN9 I RF input of external division into 2 terminal for DVD
54 VIN10 I RF input of external division into 2 terminal for DVD
55 VCC1 - Power supply terminal 5V
56 VREF1 O VREF1 voltage output terminal
57 VIN1 I External division into four (DVD/CD) RF input terminal1
58 VIN2 I External division into four (DVD/CD) RF input terminal2
59 VIN3 I External division into four (DVD/CD) RF input terminal3
60 VIN4 I External division into four (DVD/CD) RF input terminal4
61 GND1 - Connect to GND
62 VIN11 I 3 beem sub input terminal for CD
63 VIN12 I 3 beem sub input terminal for CD
64 HDTYPE I HD type switching
4
1.3 HY57V161610DTC8(IC504,IC505) : 16MB SDRAM
• Block diagram
• Pin function
Pin No. Symbol Description
1 VCC Power supply
2,3 DQ0,1 Data input/output
4 VSS Connect to GND
5,6 DQ2,3 Data input/output
7 VDD Power supply
8,9 DQ4,5 Data input/output
10 VSS Connect to GND
11,12 DQ6,7 Data input/output
13 VCC Power supply
14 LDQM Lower DQ mask enable
15
16
17
18
19,20 A11,10 Address inputs
21~24 A0~3 Address inputs
25 VCC Power supply
26 VSS Connect to GND
27~32 A4~9 Address inputs
33 NC Non connect
34 CKE Clock enable
35 CLK System clock input
36 UDQM Upper DQ mask enable
37 NC Non connect
38 VCC Power supply
39,40 DQ8,9 Data input/output
41 VSS Connect to GND
42,43 DQ10,11 Data input/output
44 VDD Power supply
45,46 DQ12,13 Data input/output
47 VSS Connect to GND
48,49 DQ14,15 Data input/output
50 VSS Connect to GND
WE
CAS
RAS
CS
Write enable
Column address strobe
Row address strobe
Chip enable
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5
XV-M50BK
1.4 M35500AFP(IC802) : FL Driver
• Pin layout
• Pin function
Pin No. Symbol I/O Description
1 VDD - Power supply terminal
2 XOUT O The short-circuit is made and the capacitor is connected with XIN on the outside
3 VSS - Connect to ground
4 XIN I The short-circuit is made and the capacitor is connected with XOUT on the outside
5 RESET I Reset input L:Reset
6~11 AIN5~0 I Key control signal input
12 CS I Chip select input L:The serial transfer is possible
13 SIN I Serial data input
14 SOUT O Serial data output
15 SCLK I Clock input of serial transfer
16,17 VEE - The voltage supplied to the pull down resistance is impressed
18~20 DISC3~1 IND O Indicator control signal output of disc indicator 1~3
21,22 NC - Not use
23~29 7G~1G O FL Grid control signal output
30~43 S14~S1 O FL Segment control signal output
44 VDD - Power supply terminal
6
1.5 M56788FP-W (IC271) : Traverse mechanism driver
• Terminal Layout
XV-M50BK
• Block diagram
7
XV-M50BK
1.6 MN101C49GGJ1(IC701): System controller
• Terminal layout
• Pinfunction
Pin No. Symbol I/O Function
1 GND - Connect to ground
2 NC - No connect
3 NC - No connect
4 NC - No connect
5 NTSEL I NTSC/PAL selection
6 POWER SW I Power switch detect terminal
7 SHUT1 - Connect to VDD
8 KEY1-5 - Connect to VDD
9 KEY6-10 - Connect to VDD
10 VREF+ I Reference voltage
11 VDD I Power supply
12 OSC2 O External terminal for connected oscirator
13 OSC1 I External terminal for connected oscirator
14 VSS - Connect to ground
15 XI - Connect to ground
16 XO - No connect
17 MMOD - Connect to ground
18 DADATA I/O Data bus for DAC
19 DACSO O Serial bus output for DAC
20 DACK I/O Clock for DAC
21 S2UDT O Communication between unit microcomputers DATA output
22 U2SDT I Communication between unit microcomputers DATA output
23 SCLK I/O Serial clock bus
24 BUSY I/O Busy bus
25 CPURST O Unit microcomputer reset
26 REQ I Commnication between unit microcomputers REQ
27 REMO I Remote control interrruption
28 - Non connect
29 - Non connect
30 - Connect to ground
31 - Connect to ground
32 - Connect to ground
33 RESET I DVD reset
34 - No connect
35 - No connect
36 VCD - No connect
37 OSDCK - No connect
38 NT - No connect
39 FS2 - No connect
8
Pin No. Symbol I/O Function
40 CHREQ I Changer commnication REQUEST
41 CHST O Changer commnication STROBE
42 CHDATA O Changer commnication DATA I/O
43 - No connect
44 CHCK I Channel clock
45 FLDATAO O Serial data output
46 FLDATAI I Serial data input
47 FLCK O Clock output of serial transfer
48 FLCS O Chip select output
49 FLRST O Reset output
50 EEDO O Data output to EEPROM
51 EEDI I Data input from EEPROM
52 EECK O Clock signal output to EEPROM
53 EECS O Chip select output to EEPROM
54 VS1 O Fanction SW control
55 VS3 O Fanction SW control
56 DMUT1 - No connect
57 DMUT2 - No connect
58 PDB2 - No connect
59 PDB1 - No connect
60 DEMP2 - No connect
61 DEMP1 - No connect
62 DENA - No connect
63 KARAOKE O KARAOKE Mode switching terminal
64 POWER ON O Power on control output
65 VS2 - No connect
66 - No connect
67 - No connect
68 - No connect
69 - No connect
70 - No connect
71 - No connect
72 - No connect
73 - No connect
74 - No connect
75 - No connect
76 - No connect
77 AVCI I AV compulink signal input
78 AVCO O AV compulink signal output
79 RGB O RGB select control signal output
80 STDIND O Standby LED control signal output
81 - No connect
82 - No connect
83 - No connect
84 - No connect
85 - No connect
86 CS4 - No connect
87 MA - No connect
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XV-M50BK
Pin No. Symbol I/O Function
88 MB - No connect
89 M1M3 - No connect
90 MD - No connect
91 MC - No connect
92 GAIN2 - No connect
93 GAIN1 - No connect
94 HPMUT - No connect
95 DAVSS - No connect
96 LMUTE - No connect
97 CMUTE - No connect
98 SMUTE - No connect
99 MUTE O Muting control signal output
100 DAVDD - Power supply terminal
10
1.7 MN102L62GGP (IC401) : Unit CPU
XV-M50BK
PinNo. Symbol I/O Function
1 WAIT I Micon wait signal input
2 RE O Read enable
3 SPMUTE O Spindle muting output to IC251
4 WEN O Write enable
5CS0-Not use
6 CS1 O Chip select for ODC
7 CS2 O Chip select for ZIVA
8 CS3 O Chip select for outer ROM
9 DRVMUTE O Driver mute
10 SPKICK - Non connect
11 LSIRST O LSI reset
12 WORD I Bus selection input
13 A0 O Address bus 0 for CPU
14 A1 O Address bus 1 for CPU
15 A2 O Address bus 2 for CPU
16 A3 O Address bus 3 for CPU
17 VDD - Power supply
18 SYSCLK - Non connect
19 VSS - Ground
20 XI - Not use (Connect to vss)
21 XO - Non connect
22 VDD - Power supply
23 OSCI I Clock signal input(13.5MHz)
24 OSCO O Clock signal output(13.5MHz)
25 MODE I CPU Mode selection input
26 A4 O Address bus 4 for CPU
27 A5 O Address bus 5 for CPU
28 A6 O Address bus 6 for CPU
29 A7 O Address bus 7 for CPU
30 A8 O Address bus 8 for CPU
31 A9 O Address bus 9 for CPU
32 A10 O Address bus 10 for CPU
33 A11 O Address bus 11 for CPU
34 VDD - Power supply
35 A12 O Address bus 12 for CPU
36 A13 O Address bus 13 for CPU
37 A14 O Address bus 14 for CPU
38 A15 O Address bus 15 for CPU
39 A16 O Address bus 16 for CPU
40 A17 O Address bus 17 for CPU
41 A18 O Address bus 18 for CPU
42 A19 O Address bus 19 for CPU
43 VSS - Ground
44 A20 O Address bus 20 for CPU
45 TXSEL O TX Select
46 HAGUP O Connect to pick-up
47 CD/DVD I CD/DVD Detect signal
48 ADPD O Power down control signal to IC511
49 HMFON O HFM Control output to IC102
50 TRVSW I Detection switch of traverse inside
51 FGIN I Focus gain input
52 TRS
53 ADSCEN O Servo DSC serial I/F chip select
PinNo. Symbol I/O Function
54 VDD - Power supply
55 FEPEN O Serial enable signal for FEP
56 SLEEP O Standby signal for FEP
57 BUSY I Communication busy
58 REQ O Communication request
59 CIRCEN O CIRC serial I/F chip select
60 HSSEEK
61 VSS - Ground
62 EPCS O EEPROM chip select
63 EPSK O EEPROM clock
64 EPDI I EEPROM data input
65 EPDO O EEPROM data output
66 VDD - Power supply
67 SCLKO O Communication clock
68 S2UDT I Communication input data
69 U2SDT O Communication output data
70 CPSCK O Clock for ADSC serial
71 SDIN I ADSC serial data input
72 SDOUT O ADSC serial data output
73 - I Not use (Pull up)
74 - I Not use (Pull up)
75 NMI I NMI Terminal
76 ADSCIRQ I Interrupt input of ADSC
77 ODCIRQ I Interrupt input of ODC
78 DECIRQ I Interrupt input of ZIVA
79 WAKEUP - Connect to ground
80 ODCIRQ2 I Interruption of system control
81 ADSEP I Address data selection input
82 RST I Reset input
83 VDD - Power supply
84 TEST1 I Test signal 1 input
85 TEST2 I Test signal 2 input
86 TEST3 I Test signal 3 input
87 TEST4 I Test signal 4 input
88 TEST5 I Test signal 5 input
89 TEST6 I Test signal 6 input
90 TEST7 I Test signal 7 input
91 TEST8 I Test signal 8 input
92 VSS - Ground
93 D0 I/O Data bus 0 of CPU
94 D1 I/O Data bus 1 of CPU
95 D2 I/O Data bus 2 of CPU
96 D3 I/O Data bus 3 of CPU
97 D4 I/O Data bus 4 of CPU
98 D5 I/O Data bus 5 of CPU
99 D6 I/O Data bus 6 of CPU
100 D7 I/O Data bus 7 of CPU
11
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