JVC KDLX-100, KDLX-330 Service manual

KD-LX300/KD-LX100

SERVICE MANUAL

CD RECEIVER

KD-LX300/KD-LX100

J Northern America

Area Suffix

Difference piont

KD-LX300 KD-LX100

Contents

Safety preccaution Preventing static electricity Disassembly method Adjustment method Extension cord connectiong method Functions of the mechanism under the service mode Flow of functional operation until TOC read Maintenance of laser pickup Replacement of laser pickup Description of major ICs

9

SEL

78

LINE IN

O X

11 12

10

SUBWOOFER OUT

OFF

O X

1-2 1-3 1-4 1-13 1-14

1-16

1-18 1-19 1-19 1-21~37

No.49635

Apr. 2001

Description of major ICs

FAN8037 (IC661) : CD driver

1. Pin layout & Block diagram

48 47 46 45 44 43 42 41 40 39 38 37

1

2

3

4

5

6

KD-LX300/KD-LX100

36

35

34

33

32

31

2. Pin function

Symbol

No.

1

IN2+

2

IN2-

3

OUT2

4

IN3+

5

IN3-

6

OUT3

7

IN4+

8

IN4-

9

OUT4

10

CTL1

11

FWD1

12

REV1

13

CTL2

14

FWD2

15

REV2

16

SGND

17

FWD3

18

REV3

19

CTL3

20

SB

21

PS

22

MUTE

23

PVCC2

24

DO7-

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

Function

I/O

I

CH2 op-amp input(+)

I

CH2 op-amp input(-)

O

CH2 op-amp output

I

CH3 op-amp input(+)

I

Ch3 op-amp input(-)

O

CH3 op-amp output

I

CH4 op-amp input(+)

I

CH4 op-amp input(-)

O

CH4 op-amp output(+)

I

CH5 motor speed control

I

CH5 forward input

I

CH5 reverse input

I

CH6 motor speed control

I

CH6 forward input

I

CH6 reverse input

-

Signal ground

I

CH7 forward input

I

CH7 reverse input

I

CH7 motor speed control

I

Stand by

I

Power save

I

All mute

-

Power supply voltage

O

CH7 drive output(-)

M

s

S

w

C

M

s

S

w

C

M

s

S

w

C

T.S . D

D

STAND BY

ALL MUTE

POWER SAVE

Pin No.

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Symbol

DO7+

DO6-

DO6+

PGND2

DO5-

DO5+

DO4-

DO4+

DO3-

DO3+

PGND1

DO2-

DO2+

DO1-

DO1+ PVCC1 REGOX

REGX RESX

VREF

SVCC

IN1+

IN1-

OUT1

30

29

28

27

26

25

Function

I/O

O

CH7 drive output(+)

O

CH6 drive output(-)

O

CH6 drive output(+)

-

Power ground2

O

CH5 drive output(-)

O

CH5 drive output(+)

O

CH4 drive output(-)

O

CH4 drive output(+)

O

CH3 drive output(-)

O

CH3 drive output(+)

-

Power ground1

O

CH2 drive output(-)

O

CH2 drive output(+)

O

CH1 drive output(-)

O

CH1 drive output(+)

-

Power supply voltage

I

Regulator feedback input

O

Regulator output

I

Regulator reset input

I

Bias voltage input

-

Signal supply voltage

I

CH1 op-amp input(+)

I

CH1 op-amp input(-)

O

CH1 op-amp output

1-21

KD-LX300/KD-LX100

UPD784215AGC-128 (IC701) : UNIT CPU

1.Terminal Layout

75 ~ 51

76

~

50

~

100

1 ~ 25

2.Pin Function (1/2)

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Symbol

SW2 SW3 SW4

REST-SW

LM0 LM1

DIMMER-OUT

LCD-PWR

VDD

X2 X1

VSS

XT2 XT1

RESET

SW1

BUS-INT

PS2

CRUISE

NC NC

REMOCON

AVDD

AVREF0

VOL1 VOL2 KEY0 KEY1 KEY2

LEVEL

NC

S.METER

AVSS

W-VOL

DOT-CONT

AVREF BUS-SI

BUS-SO

BUS-SCK

STAGE2 LCD-DA

LCDCL

26

I/O

Detection switch of CD mechanism

I

Detection switch of CD mechanism

I

Detection switch of CD mechanism

I

Reset signal input from CD mechanism

I

Loading motor control signal output

O

Loading motor control signal output

O

Dimmer signal output

O

LCD driver power supply control output H:ON

O

Power supply terminal

Connecting the crystal oscillator for system main clock

Power supply terminal

Connecting the crystal oscillator for system sub clock

System reset signal input

I

Detection switch of CD mechanism

I

Cut-in input for J-BUS signal

I

Power save 2, Working together back up by H input, to stop mode

I

Pulse signal input port for Cruise control

I

Clock signal input for RDS

RDS data input

Remote control signal input

I

Power supply terminal

Input for rotation volume detection pulse judgment to relation V1

I

Input for rotation volume detection pulse judgment to relation V2

I

Key control signal input 0

I

Key control signal input 1

I

Key control signal input 2

I

Signal input port of level meter

I

Non connect

I

S.Meter level input

I

Connect to GND

Subwoofer volume control analogue output

O

Dot contrast signal output

O

Power supply terminal

J-BUS data input

I

J-BUS data output

O

J-BUS Clock signal I/O

I/O

Initial setting

I

Data output to LCD driver

O

Clock output to LCD driver

O

Function

1-22

Pin Function (2/2)

KD-LX300/KD-LX100

Pin No.

43 44 45 46 47 48 49 50 51 52 53 54 55

56~60

61,62

63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

95~98

99

100

Symbol

LCD-CE1

BUZZER

E2PR-DA-I

E2PR-DA-O

E2PR-CLK

BUS-I/O

TM0

TM1 DM0 DM1

SD/ST

LOCAL

MONO

CA-SW1~5

NC

SEEK/STOP

NC

FM/AM PLL-CE PLL-DA PLL-CK

BAND IN

NC

AMP KILL

VSS

DIMMER-IN

PS1

POWER

CD-ON

MUTE W-LPF1 W-LPF2

W-MUTE

VDD

VO-DA

VOL-CLK

NC

GVSW

LCDRST

LCD-CE2

DMK TMK

NC

BUCK

CCE

RST

TEST

BUS0~3

DISC SEL

NC

I/O

Chip enable output to LCD driver

O

BUZZER control signal output

O

Data input terminal from EEPROM

I

Data output terminal for EEPROM

O

Clock signal I/O terminal with EEPROM

O

J-BUS I/O signal terminal

I/O

Tray motor negative signal output terminal

O

Tray motor positive signal output terminal

O

Door motor negative signal output terminal

O

Door motor positive signal output terminal

O

Station detector, Stereo signal input, H:Find Station L:Stereo

I

Local ON/OFF select signal output terminal

O

Monaural ON/OFF selecting output, H:MONO ON

O

DOOR/TRAY open close detect switch signal input terminal

I

Non connect

Auto seek/stop selecting output, H:Seek L:Stop

O

Non connect

Selecting output for FM/AM, L:FM H:AM

O

CE output for IC control for PLL

O

Data output for IC control for PLL

O

Clock output for IC control for PLL

O

AM detect signal input

I

Non connect

Connect to GND

DIMMER signal input terminal

I

Power supply terminal

I

Selecting output for power ON/OFF, H:power ON

O

Power supply control signal for CD H:CD

O

MUTE output, L:MUTE ON

O

Subwoofer cut off frequency output 1

O

Subwoofer cut off frequency output 2

O

MUTE output for Subwoofer

O

Power supply terminal

Data output terminal

O

Clock signal output terminal

O

Non connect

AGC/FE/TE amp gain change terminal

O

LCD reset signal output terminal

O

Chip enable 2 output terminal for LCD driver

O

Motor speed control signal output terminal

O

Tray motor control signal output terminal

O

Non connect

Micon interface clock output terminal

O

Command and data sending/receiving chip enable signal output

O

Reset signal output terminal reset at "L" level

O

Connect to GND

Micon interface data input/output terminal

I/O

Initial setting

I

Non connect

-

Function

1-23

KD-LX300/KD-LX100

TC9490FA (IC521) : DSP

1. Pin layout & Block diagram

DVss3 49

RO 50

DVDD3 51

DVR 52

LO 53

DVss3 54

ZDET 55

Vss5 56

BUS0 57

BUS1 58

BUS2 59

BUS3 60

47 XO

48 XVDD3

LPF

46 XI

Clock

generator

1-bit

DAC

45 XVss3

44 TESIN

circuit

Correction

43 VDD3

Address

circuit

16 k

RAM

42 Vss3

41 DMO

PWM

39 AVDD3

40 FMO

Servo control

ROM

RAM

CLV servo

Sync signal

protection

EFM

38 SEL

37 TEBC

Digital equalizer

automatic

adjustment circuit

36 RFGC

35 VREF

D/A

A/D

Data

slicer

VCO

34 TRO

33 FOO

32 TEZI

31 TEI

30 SBAD

29 FEI

28 RFRP

27 RFZI

26 RFCT

25 AVDD3

24 RFI

23 SLCO

22 AVss3

21 VCOF

BUCK 61

/CCE 62

/RST 63

VDD5 64

BCK 1

2. Pin function (1/2) Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13

Symbol

BCK

LRCK AOUT DOUT

IPF

VDD3

Vss3

SBOK

CLCK

DATA SFSY SBSY

/HSO

Micro-

controller

interface

LRCK 2

I/O

O O O O O

-

O O O O O O

Audio output

AOUT 3

circuit

DOUT 4

Digital output

IPF 5

VDD3 6

Vss3 7

CLCK 9

SBOK 8

Sub code

decoder

DATA 10

Function Bit clock output terminal L/R channel clock output terminal Audio data output terminal Digital data output terminal Correction flag output terminal Digital 3.3V power supply voltage terminal Digital GND terminal Subcode Q data CRCC result output terminal Subcode P-W data read clock I/O terminal Subcode P-W data output terminal Playback frame sync signal output terminal Subcode block sync signal output terminal Playback speed mode output terminal

SFSY 11

SBSY 12

PLL

TMAX

/HSO 13

/UHSO 14

20 PVREF

19 LPFO

18 LPFN

17 TMAX

PDO 16

PVDD3 15

1-24

2. Pin function (2/2) Pin No.

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Symbol

/UHSO

PVDD3

PDO

TMAX

LPFN LPFO

PVREF

VCOF AVss3 SLCO

RFI

AVDD3

RFCT

RFZI

RFRP

FEI

SBAD

TEI TEZI FOO

TRO VREF RFGC TEBC

SEL

AVDD3

FMO DMO Vss3

VDD3

TESIN XVss3

XI

XO

XVDD3

DVss3

RO

DVDD3

DVR

LO

DVss3

ZDET

Vss5 BUS0 BUS1 BUS2 BUS3

BUCK

/CCE /RST

VDD5

I/O

Function

O

Playback speed mode output terminal

-

PLL-only 3.3V power supply voltage terminal

O

EFM and PLCK phase difference signal output terminal

O

TMAX detection result output terminal

I

Inverted input terminal for PLL LPF amp

O

Outpuit terminal for PLL LPF amp

-

PLL-only VREF terminal

O

VCO filter terminal

-

Analog GND terminal

O

DAC output terminal for data slice level generation

I

RF signal input terminal

-

Analog 3.3V power supply voltage terminal

I

RFRP signal center level input terminal

I

RFRP signal zero-cross input terminal

I

RF ripple signal input terminal

I

Focus error signal input terminal

I

Sub-beam adder signal input terminal

I

Tracking error input terminal

I

Tracking error signal zero-cross input terminal

O

Focus equalizer output terminal

O

Tracking equalizer output terminal

-

Analog reference power supply vpltage terminal

O

RF amplitude adjustment control signal output terminal

O

Tracking balance control signal output terminal

O

APC circuit ON/OFF signal output terminal

-

Analog 3.3V power supply voltage terminal

O

Feed equalizer output terminal

O

Disc equalizer output terminal

-

Digital GND terminal

-

Digital 3.3V power supply voltage terminal

I

Test input terminaal

-

System clock oscillator GND terminal

I

System clock oscillator input terminal

O

System clock oscillator output terminal

-

System clock oscillator 3.3V power supply voltage terminal

-

DA converter GND terminal

O

R-channel data forward output terminal

-

DA converter 3.3V power supply terminal

-

Reference voltage terminal

O

L-channel data forward output terminal

-

DA converter GND terminal

O

1 bit DA converter zero data detection flag output terminal

-

Microcontroller interface GND terminal

I/O

Microcontroller interface data I/O terminal

I/O

Microcontroller interface data I/O terminal

I/O

Microcontroller interface data I/O terminal

I/O

Microcontroller interface data I/O terminal

I

Microcontroller interface clock input terminal

I

Microcontroller interface chip enable signal input terminal

I

Reset signal input terminal

-

Microcontroller interface 5V power supply terminal

KD-LX300/KD-LX100

1-25

KD-LX300/KD-LX100

BA3220FV-X (IC301,IC401) : Driver

1. Pin layout & Block diagram

CL- LGND OUTL OUTR RGND CR - CR +

1314

REFL REFR

1112 9 810

FILTER

2143675

CL+ Vcc INL NFL FIL NFR INR

2. Pin function

Symbol Function

No.

1

10 11 12 13 14

2 3 4 5 6 7 8 9

CL+

Vcc

INL

NFL

FIL

NFR

INR

CR+

CR-

RGND

OUTR

OUTL

LGND

CL-

Powe supply terminal for amp. power supply terminal. input terminal. Negative feedback terminal. Filter terminal. Negative feedback terminal. Input terminal Power supply terminal for amp. Output terminal of internal amp. Rch GND terminal. Rch output terminal. Lch output terminal. Lch GND terminal. Output terminal of internal amp.

000874360-T (IC702) : System reset

1. Pin layout 2. Block diagram 13

2

1-26

1 Vcc

3 Vout

OP1

2 GND

BD3860K (IC911) : E. volume

1.Terminal layout

33 23

KD-LX300/KD-LX100

2.Bockdiagram

GND FIL VCC SEL1

6 5 9 40 36 35 343328323130 2919 15 14

POWER SUPPLY

A1

41

B1

42

C1

43

D1

44

INPUT

1

2

3

4

SELECTOR

A2

B2

C2

D2

34

44

1 11

INPUT

GAIN

0 18 dB

INPUT

GAIN

0 18 dB

22

12

VIN1 LOUD1 HF1 LF1 DET1 TIN1 TNF1 BNF1

MAIN VOLUME 0 -40 dB

LOUDNESS

MAIN VOLUME 0 -40 dB

LOUDNESS

LOW(f=50Hz) 6dB PROCESS CONTROL +3 to 12dB (f=10kHz)

LOGIC

LOW(f=50Hz) 6dB PROCESS CONTROL +3 to 12dB (f=10kHz)

TREBLE

-14 +14dB

TREBLE

-14 +14dB

BASS

BOUT1VCA1 MIX1 BBOUT1

FADER

CH1 FRONT

0 -5 dB

FADER

CH1 REAR

0 -5 dB

FADER

CH2 REAR

0 -5 dB

FADER

CH2 FRONT

0 -5 dB

13

12

10

11

7

8

OUTF1

OUTR1

SI

SC

OUTR2

OUTF2

3.Pin function

Symbol Function

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

A2

B2 C2 D2 FIL

GND

SI

SC

VCC

OUTR2

OUTF2

OUTR1

OUTF1

BOUT1

BNF1

BOUT2

BNF2

TNF2 TNF1

TIN2

BBOUT2

MIX2

CH2 Input Pin A CH2 Input Pin B CH2 Input Pin C CH2 Input Pin D 1/2 VCC Pin Ground Pin Serial Data Receiving Pin Serial Clock Receiving Pin Power Supply Pin CH2 Rear Output Pin CH2 Front Output Pin CH1 Rear Output Pin CH1 Front Output Pin CH1 Bass Filter Setting Pin CH1 Bass Filter Setting Pin CH2 Bass Filter Setting Pin CH2 Bass Filter Setting Pin CH2 treble Filter Setting Pin CH1 treble Filter Setting Pin CH2 treble Input Pin CH2 BBE II Signal Output Pin CH2 Output MIX Amplifier Inverse Input Pin

39 38 37 25 24 26 23 22 21 20 18 17 16

Symbol Function

No.

23 24 25 26 27 28 29

BBOUT1

30 31 32 33 34

LOUD1

35 36

LOUD2

37 38 39 40 41 42 43 44

VCA2

LF2

HF2

DET2

NC

DET1

TIN1

MIX1

VCA1

LF1

HF1

VIN1

VIN2 SEL2 SEL1

A1 B1 C1 D1

CH2 High Pass VCA Output Pin CH2 Low Pass Filter Setting Pin CH2 High Pass Filter Setting Pin CH2 High Pass Attack/Release Time Setting Pin Non connect CH1 High Pass Attack/Release Time Setting Pin CH1 treble Input Pin CH1 BBE II Signal Output Pin CH1 Output MIX Amplifier Inverse Input Pin CH1 High Pass VCA Output Pin CH1 Low Pass Filter Setting Pin CH1 High Pass Filter Setting Pin CH1 Loudness Filter Setting Pin CH1 Main Volume Input Pin VCH2 Loudness Filter setting Pin CH2 Main Volume Input Pin CH2 Input Gain Output Pin CH1 Input Gain output Pin CH1 Input Pin A CH1 Input Pin B CH1 Input Pin C CH1 Input Pin D

BOUT2BNF2TNF2TIN2BBOUT2MIX2VCA2DET2LF2HF2LOUD2VIN2SEL2

1-27

KD-LX300/KD-LX100

BR24C16F-X (IC703) : EEPROM

1. Pin layout

VCC WP SCL SDA

A0 A1 A2 GND

3. Block diagram

A0 1

A1 2

A2 3

11bit

Address decoder

16kbit EEPROM allay

11bit

START

Control circuit

2. Pin function

Symbol

VCC GND

A0,A1,A2

SCL

SDA

WP

Slave Ward Address resister

STOP

I/O

-

Power supply.

-

GND

I

No use connect to GND.

I

Serial clock input.

I/O

Serial data I/O of slave and ward address.

I

Write protect terminal.

8bit

Data resister

Function

8 Vcc

7 WP

6 SCL

ACK

GND 4

High voltage osc circuit

Power supply voltage det.

BU4066BCFV-X (IC322) : Quad analog switch

1. Pin layout & Block diagram VDD C1 C4 I/O4 I/O3O/I4 O/I3

14 13 12 11 810 9

5 SDA

1-28

1234 756

I/O1 O/I1 O/I2 I/O2 VssC2 C3

HA13164 (IC961) : Regulator

1.Terminal layout

123456789101112131415

KD-LX300/KD-LX100

2.Block diagram

3.Pin function

ANT OUT

C3

0.1u

EXT OUT

C4

0.1u

ANT CTRL

CTRL

CD OUT

C5

0.1u

AUDIO OUT

C6

10u

11

12

10

BATT.DET OUT

9

COMPOUT

6

VDD OUT

4

SW5VOUT

5

14

UNIT R:

+B

ACC

ILMOUT

R1

C7

0.1u

C8

0.1u

C1

100u

VCC ACC

8

2

1

7

Surge Protector

BIAS TSD

15

3

note1) TAB (header of IC)

connected to GND

ILM AJGND

13

C2

0.1u

C:F

Pin No. Symbol Function

1 2

EXTOUT ANTOUT

Output voltage is VCC-1 V when M or H level applied to CTRL pin. Output voltage is VCC-1 V when M or H level to CTRL pin and H level

to ANT-CTRL. 3 4 5 6 7 8 9

10 11 12 13 14 15

ACCIN VDDOUT SW5VOUT COMPOUT ANT CTRL VCC BATT DET AUDIO OUT CTRL CD OUT ILM AJ ILM OUT GND

Connected to ACC.

Regular 5.7V.

Output voltage is 5V when M or H level applies to CTRL pin.

Output for ACC detector.

L:ANT output OFF , H:ANT output ON

Connected to VCC.

Low battery detect.

Output voltage is 9V when M or H level applied to CTRL pin.

L:BIAS OFF, M:BIAS ON, H:CD ON

Output voltage is 8V when H level applied to CTRL pin.

Adjustment pin for ILM output voltage.

Output voltage is 10V when M or H level applies to CTRL pin.

Connected to GND.

1-29