JUNSUNGTECH JSWAM83 User Manual
Rev0.0
JSWAM83 Module
JSWAM83
9
Tri Band Module
USER Manual
Product Name :
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The JSWAM83 module is a wireless audio module (60X21mm)) based on the SMSC
Automatic Frequecncy Allocation.
JSWAM83 Block Diagram
9
1. Product Description
DARR83. This module can used to build an uncompressed wireless digital audio
transceiver operating in the 2.4GHz, 5.2GHz and 5.8GHz bands.
The wireless audio link supports up to two stereo audio streams and comes together with
additional features such as: data encryption, pairing functionality, bi-directional control
data messages, low power audio snooze mode,
The DARR83 chip itself provides the basic functions of Audio Processing and buffering, Data
Link Layer and Physical Layer. The WISP50S module integrates all functionality for a wireless
digital and analog audio connection, comprising:
2. Features
DARR83 Wireless Audio Processor
2.4GHz/ 5.2GHz/ 5.8 GHz RF Transceiver
Embedded Antennas
Digital audio interfaces (I
Integrated 24 bit stereo Audio DAC + Headphone AMP
Integrated 16 bit Audio ADC + Microphone AMP
Built-in SPI interface Flash
9 pins interface connector for power, audio output, control interface and GPIOs
Regulated 5V supply
2
S)
3.
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Using RF Frequency
4. Description of operations
4.1 Operating Conditions ( 5 V 450 mA)
Symbol Parameter Min. Typ Max Unit
VCC Supply Voltage 4.7 5.0 5.25 V
Temp Operating Temperature 0 25 60 °C
4.2 RF Information
Parameter Value Unit
Modulation QPSK
2400 – 2483.5
RF Frequency range (band)
Audio Latency
5150 – 5250
5725 – 5875
Ch1 – 2412
Ch2 – 2436
Ch3 – 2464
Ch4 – 5180
Ch5 – 5210
Ch6 – 5240
Ch7 – 5736
Ch8 – 5726
Ch9 – 5814
20ms
MHz
MHz
Audio Bit Resolution
Audio Sampling Rate
Note: Country/ Region dependent.
16bit
48ksps
4.3 Receive mode
In receive mode, antenna diversity is supported. The single ended output of the TR switch is
connected to the RF LNA input through Diplexer and matching networks. Filtering and amplification is
all performed by the radio transceiver. The gain setting is controlled by the BB. The analog IQ outputs
are sampled by the BB by its integrated 22Msps dual channel 8bit ADC. This received data is
demodulated and fed to the audio processing engine controlling the audio function.
4.4 Transmit mode
In transmit mode, the audio engine transforms the audio data into packetized digital IQ signals. These
are in turn pulse-shaped before conversion by a 10bits 44Msps DAC to match to the analog IQ inputs
of the radio IC. The radio IC has programmable baseband filters to lower the RF spectrum side lobes
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and to suppress the DAC image and the DAC spurious. The output power is programma ble. A power
detector (PD_out) on the radio IC enables close-loop TX power control. The differential RF PA outputs
are connected via a baluns and Diplexer to a transmit/receive switch with TX diversity option to the RF
connectors.
5. Clock and synthesizer frequencies
The main crystal is connected to the Baseband IC crystal oscillator. This in turn buffers this 44MHz
and feeds it to the radio IC.
In standard configurations, the DARR83 based DWPCIe83 module’s RF section runs at the following
frequencies:
2.4GHz Band: The RF oscillator runs at 2 times the programmed RF output frequency.
Channel RF frequency (in MHz) VCO frequency (in MHz)
1 2412 4824
2 2438 4876
3 2464 4928
5.2GHz Band: The RF oscillator runs at 2/3 times the programmed RF output frequency.
Channel RF frequency (in MHz) VCO frequency (in MHz)
1 5180 3453.33
2 5210 3473.33
3 5240 3493.33
5.8GHz Band: The RF oscillator runs at 2/3 times the programmed RF output frequency.
Channel RF frequency (in MHz) VCO frequency (in MHz)
1 5736 3824
2 5762 3841.33
3 5814 3876
6. Modulation Diagram
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7. Pin out interface connector
Pin information.
Pin Number Pin Name I/O Description
1 5V
2 5V
3 GPIO_2
4 GPIO_13
5 GPIO_14
6 /RESET(DARR_RST)
7 I2C_SCL_SLV
8 I2C_SDA_SLV
9 I2C_SCL_MST
10 I2C_SDA_MST
11 MCLK
12 GND
13 BCK_W
14 LRCK_W
15 GPIO_5
16 GPIO_11
17 MON_TXD
18 GIPO_6
19 GPIO_12
20 GPIO_3
21 GPIO_15
22 GPIO_4
23 GPIO_7
24 GND
PWR
PWR
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
Regulated 4.7V to 5.2V input
Regulated 4.7V to 5.2V input
PWM_RST#
MUTE
POWER_CTL
Reset Darr83
I2C serial clock Slave
I2C serial data Slave
I2C serial clock Master
I2C serial data Master
12.288MHz audio clock I/O
GND
I2S port W Bit Clock
I2S port W Left Right Clock
DAT_W
DAT_X
Serial sync Data, for test purposes
FW_SEL
IR_RST#
ID_SET#
RED_LED
BLUE_LED (UART_RXD)
IR_SD#(HW_MUTE)
GND
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OEM Installation
8.
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