JRC NJU8402M, NJU8402D Datasheet
NJU8402
PRELIMINARY
DIGITAL TO ANALOG CONVERTER
FOR STEREO AUDIO
GENERAL DESCRIPTION
■
NJU8402
The
Converter for stereo audio. It cons ists of Ser ial A ud io Da ta
Interface, Digital Interpolation Filter, ∆Σ Modulator, SC LPF ,
Buffer Amp, System Controller for status control. It
operates on single +5V power supply. Furthermore, it
accepts 16-bit input audio data length or 18-bit, and
supports I
Therefore, the
and other digital audio applications.
FEATURES
■
●
∆Σ type 1bit stereo DAC
●
Sample Rate ( fs ) : 50kHz ( Maximum )
●
Signal-to-Noise Ratio : 94dB
●
Input Audio Data Length : 16bits or 18bits
●
Single ended Analog Output
●
Internal SC type Low Pass Filter
●
Operating Voltage +5V ±5%
●
Package Outline DIP16 / DMP16
is a 16-bit delta-sigma Digital-to-Analog
2
S serial data format and LSB justified.
NJU8402
is suitable for CD, MD, DAT
PACKAGE OUTLINE
■
NJU8402D NJU8402M
PIN CONFIGURATION
■
V
MCKI
SCK
DATA
REQ
AOUTL
VCOML
AV
1
DD
2
3
4
5
6
7
89
DD
16
15
14
13
12
11
10
V
SS
BCLK
LRCK
DIN
RST
AOUTR
VCOM
AV
SS
BLOCK DIAGRAM
■
DIN
BCLK
LRCK
Serial Audio
Data Interface
Digital
Interpolation
Filter
System
Controller
REQ
MCKI
RST
SCK
DD
AV
SS
AV
SC
LPF
SC
LPF
LPF
LPF
AOUTL
VCOML
AOUTR
VCOMR
∆Σ
Modulator
∆Σ
Modulator
SS
DD
V
DATA
V
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NJU8402
TERMINAL DESCRIPTION
■
PIN
SYMBOL
No.
1V
16 V
8AV
9AV
DD
SS
DD
SS
INPUT
/OUTPUT
FUNCTION
Digital Power Supply, +5V
Digital GND, 0V
Analog Power Supply, +5V
Analog GND, 0V
2 MCKI I Master Clock Input Terminal
The input signal frequency is 256 times or 384 times of fs.
13 DIN I Serial Audio Data Input Terminal
14 LRCK I
15 BCLK I
L/R Channel Clock Input Terminal
This clock must synchronize with MCKI.
Audio Serial Data Clock Input Terminal
This clock must synchronize with MCKI.
Control Register Serial Data Sift Clock Input Terminal
3SCK I
Control register leads the control data synchronizing the rising edge of SCK
signal. When the c ontrol register is not used, the state of SCK terminal h as to
keep level ”H”.
Control Register Serial Data Input Terminal
4DATA I
Input data sets various functions.
When the control register is not used, the state of DATA terminal has to keep level
“H”.
Control Register Serial Data Request Input Terminal
The control data are latched in the control register at the rising edge of REQ
5REQ I
signal.
When the control re gist er is not us ed, the s t ate of REQ terminal has to keep level
“H”.
12 RST I
Reset
“L” level signal into reset terminal initializes the system.
Left channel Analog Signal Common Terminal for Connecting Smooth Capacitor
7VCOML
A chemical capacitor should be connected between this terminal and AVSS for
stabilizing.
Right Channel Analog Signal Common T erminal for Connecting Smooth Capacitor
10 VCOMR
A chemical capacitor should be connected between this terminal and AVSS for
stabilizing.
6 AOUTL O L-Channel Analog Signal Output Terminal
11 AOUTR O R- Chann el An al og Sig na l Output Terminal
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FUNCTION DESCRIPTION
■
(1-1) Analog Audio Signal Output
Analog signal output is biased in the chip and the maximum amplitude is 0.56 × AV
switched capacitor Low Pass Filter is so effective that the ex ternal Low Pass Filters are requir ed only 2pole LPF or 3-pole.
(1-2) Serial Data Interface
DIN (Data Input), BCLK (Bit Clock) and LRCK (L/R Clock) are the serial data interface terminals. BCLK is
the bit clock of audio data and IO data are leaded at raising edge of the BCLK. The signa l into LRCK
terminal represents the signal for distinguishing between Lch and Rch, and the signal for starting data. The
frequency of LRCK is s ampling rate of s ystem ( fs ). The MCIK m ust be synchronized with LRCK and is
256 times or 384 of fs. The s erial data f orm at is com plem ent of 2, MSB-f irs t and compatib le with I
data protocol or LSB justified. This serial data format is set by the control register.
NJU8402
. The internal
DD
2
S serial
LRCK
BCLK
DIN
LRCK
BCLK
Left
151413 10 151413 10
2
S serial data format
I
Left
Right Channel
Right Channel
DIN
(1-3) System Clock
System Clock into the MCIK terminal must be 256 times or 384 times of fs and synchronizing with LRCK.
This frequency is set by the control register.
(1-4) Reset
The external reset is the asynchronous reset. Reset is released at the f alling edge at LRC K. Reset by
command is synchronous which operates as same as the external reset function.
15140 10 15142 10
LSB justified serial data format
2
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