JRC NJU6682CH Datasheet

NJU6682

PRELIMINARY

160-common x 132-segment

DOT MATRIX LCD DRIVER FOR 4 GRAY SCALE

■GENERAL DESCRIPTION ■PACKAGE OUTLINE
The NJU6682 is a b it map LC D dr iver to d ispla y graphic s or charac ters.
It contains 84,480 bits displ ay data RAM, m icr oprocess or interf ace cir cuits,
instruction decoder, and 160-common and 132-segment drivers.
The bit image data is transferred to the internal display data RAM by
serial interface or 8-bit/16-bit parallel interface.
The NJU6682 features 4- gray scale f unct ion whic h c reates 4 t ypes gra y
scale (for exam ple : white/light gray/dark gray/bl ack) or black & white with
displays 160 x 132 dots graphics or 8-caracter 10line by 16 x 16 dots
characters.
It oscillates by built-in OSC circuit without any external components.
Furthermore, the NJU6682 features Partial Display Function which
creates up to 2 blocks of activ e dis p lay area and optimizes duty cycle ratio.
This function sets opt imum boosted vol tage by the com bination with both
of programmable vo ltage booster circuit an d e lec tric a l var i able r es ister . As
result, it reduces the operating current.
The operating voltage f rom 2.4V to 3.3V and low o perating current are
useful for small size battery operating items.

■FEATURES

●Direct Correspondence between Display Data RAM and LCD Pixel

●Display Data RAM - 84,480 bits ;( 160-Com x 132-Seg) x 2-area ) x 2bit

….2 times over than display size

●Display Method – Monochrome 4-Gray Scale / Black & White

●Partial Display Function

( 2 blocks of active display area and automatic duty cycle ratio selection )

●Variable RAM Mapping
– The display screen can be composed from the RAM area in a maximum of 8 blocks not to continue.

●Easy Vertical Scroll by the variable start line address and over size display data RAM

(This function doesn’t work in Variable RAM Mapping mode )

●LCD drivers – 160-common and 132-segment

●Direct 8-bit / 16-bit Microprocessor interface for both of 68 type and 80 type MPU

●Serial Interface

●Programmable Bias selection ; 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14 bias

●Common Driver Order Assignment by mask option

Version C0 to C159( Pin Name )
NJU6682A COM0 to COM159
NJU6682B COM159 to COM0

●Useful Instruction Set
Display Data Read/W rite, Display ON/O FF, Z-Address Set, X-Address S et, Y-Address Set, Status Read, Norm al or
Inverse ON/OFF, Static Drive ON/OFF, Partial Display, n-Line I nverse, EVR Resister Set, Variable RAM Mapp ing
Mode, Gray Sca le Level Select, B ias Select, Voltag e Converter Multiple Select ( 7-times maximum ), Read Mod ify
Write, Reset ,Internal Power Supp ly, Driver Outputs ON/OFF, Po wer Save, ADC Sel ect, Displa y Mode Selec t, 8-bit /
16-bit Buss Select, etc.

●Power Supply Circuit for LCD; Programmable Booster Circuits( 7-time maximum ), Regulator, Voltage Follower x 4

●Precision Electrical Variable Resistance

●Low Power Consumption T.B.D ( typ. )

●Operating Voltage 2.4 to 3.3 V

●LCD Driving Voltage 6.0 to 18.0V

●Package Outline Bumped Chip / TCP

●C-MOS Technology

NJU6682CH

MAY 2000 Ver-1.3

■PAD LOCATION

S

S

80

81

S79

78

S

S1
S

0

DUMMY0

DUMMY1

V

DD

Chip Center :X=0um,Y=0um
Chip Size :X=8.27m,Y=5.67mm
Chip Thickness :675um ± 30um
Bump Size :45um x 83um
Pad Pitch :60um (min)
Bump Heght :15um (typ)
Bump Material :Au

NJU6682

S

C

S

C

130

131

159

158

Y

X

CS

PS

0

SEL68

RES

V

OSC

SS

1

2

DUMMY2

PS

1

RD

A0

D

WR

D

D

D

1

2

0

D

D

D

D

4

3

D

D

6

5

7

8

9

(SCL)

(SI)

OSC

D

D

D

D

13

12

11

10

V

C4

C6

V

C5

C2

D

D

OUT

SS

14

15

C3

-

-

-

-

-

C2

V

V

VR

C1

C1

+

-

5

DD

+

C

C

81

80

C79

78

C

C1
C

0

V

V

V

V

V

4

DD

3

1

2

■ PAD Cordinates

PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)

1 VDD -3933 -2675 51 C1 3975 -2126
2 DUMMY0 -3863 -2675 52 C2 3975 -2066
3 DUMMY1 -3793 -2675 53 C3 3975 -2006
4 DUMMY2 -3723 -2675 54 C4 3975 -1946
5 PS1 -3562 -2675 55 C5 3975 -1886
6 PS0 -3325 -2675 56 C6 3975 -1826
7 SEL68 -3105 -2675 57 C7 3975 -1766
8 RES -2869 -2675 58 C8 3975 -1706

9 VSS -2712 -2675 59 C9 3975 -1646
10 OSC1 -2555 -2675 60 C10 3975 -1586
11 OSC2 -2319 -2675 61 C11 3975 -1526
12 CS -2098 -2675 62 C12 3975 -1466
13 A0 -1862 -2675 63 C13 3975 -1406
14 WR -1641 -2675 64 C14 3975 -1346
15 RD -1405 -2675 65 C15 3975 -1286
16 D0 -1168 -2675 66 C16 3975 -1226
17 D1 -948 -2675 67 C17 3975 -1166
18 D2 -727 -2675 68 C18 3975 -1106
19 D3 -507 -2675 69 C19 3975 -1046
20 D4 -287 -2675 70 C
21 D5 -66 -2675 71 C
22 D6(SCL) 153 -2675 72 C
23 D7(SI) 374 -2675 73 C
24 D8 594 -2675 74 C
25 D9 814 -2675 75 C
26 D10 1035 -2675 76 C
27 D11 1255 -2675 77 C
28 D12 1476 -2675 78 C
29 D13 1696 -2675 79 C
30 D14 1916 -2675 80 C30 3975 -386
31 D15 2137 -2675 81 C31 3975 -326
32 VSS 2298 -2675 82 C32 3975 -266
33 V
34 C6- 2464 -2675 84 C34 3975 -146
35 C5- 2613 -2675 85 C35 3975 -86
36 C4- 2683 -2675 86 C36 3975 -26
37 C3- 2832 -2675 87 C37 3975 34
38 C2- 2902 -2675 88 C38 3975 94
39 C2+ 3050 -2675 89 C39 3975 154
40 C1- 3120 -2675 90 C40 3975 214
41 C1+ 3269 -2675 91 C41 3975 274
42 VDD 3339 -2675 92 C42 3975 334
43 VR 3519 -2675 93 C43 3975 394
44 V5 3589 -2675 94 C44 3975 454
45 V4 3659 -2675 95 C45 3975 514
46 V3 3729 -2675 96 C46 3975 574
47 V2 3799 -2675 97 C47 3975 634
48 V1 3869 -2675 98 C48 3975 694
49 VDD 3939 -2675 99 C49 3975 754
50 C0 3975 -2186 100 C50 3975 814

NJU6682

Chip Size 8.27x5.67mm(Chip Center X=0um, Y=0um)

20
21
22
23
24
25
26
27
28
29

2368 -2675 83 C33 3975 -206

OUT

3975 -986
3975 -926
3975 -866
3975 -806
3975 -746
3975 -686
3975 -626
3975 -566
3975 -506
3975 -446

NJU6682

PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)

101 C51 3975 874 151 C
102 C52 3975 934 152 C
103 C53 3975 994 153 C
104 C54 3975 1054 154 C
105 C55 3975 1114 155 C
106 C56 3975 1174 156 C
107 C57 3975 1234 157 C
108 C58 3975 1294 158 C
109 C59 3975 1354 159 C
110 C60 3975 1414 160 C
111 C61 3975 1474 161 C
112 C62 3975 1534 162 C
113 C63 3975 1594 163 C
114 C64 3975 1654 164 C
115 C65 3975 1714 165 C
116 C66 3975 1774 166 C
117 C67 3975 1834 167 C
118 C68 3975 1894 168 C
119 C69 3975 1954 169 C
120 C70 3975 2014 170 C
121 C71 3975 2074 171 C
122 C72 3975 2134 172 C
123 C73 3975 2194 173 C
124 C74 3975 2254 174 C
125 C75 3975 2314 175 C
126 C76 3975 2374 176 C
127 C77 3975 2434 177 C
128 C78 3975 2494 178 C
129 C79 3975 2554 179 C
130 C80 3930 2675 180 C
131 C81 3870 2675 181 C
132 C82 3810 2675 182 C
133 C83 3750 2675 183 C
134 C84 3690 2675 184 C
135 C85 3630 2675 185 C
136 C86 3570 2675 186 C
137 C87 3510 2675 187 C
138 C88 3450 2675 188 C
139 C89 3390 2675 189 C
140 C90 3330 2675 190 C
141 C91 3270 2675 191 C
142 C92 3210 2675 192 C
143 C93 3150 2675 193 C
144 C94 3090 2675 194 C
145 C95 3030 2675 195 C
146 C96 2970 2675 196 C
147 C97 2910 2675 197 C
148 C98 2850 2675 198 C
149 C99 2790 2675 199 C
150 C

2730 2675 200 C

100

2670 2675

101

2610 2675

102

2550 2675

103

2490 2675

104

2430 2675

105

2370 2675

106

2310 2675

107

2250 2675

108

2190 2675

109

2130 2675

110

2070 2675

111

2010 2675

112

1950 2675

113

1890 2675

114

1830 2675

115

1770 2675

116

1710 2675

117

1650 2675

118

1590 2675

119

1530 2675

120

1470 2675

121

1410 2675

122

1350 2675

123

1290 2675

124

1230 2675

125

1170 2675

126

1110 2675

127

1050 2675

128

990 2675

129

930 2675

130

870 2675

131

810 2675

132

750 2675

133

690 2675

134

630 2675

135

570 2675

136

510 2675

137

450 2675

138

390 2675

139

330 2675

140

270 2675

141

210 2675

142

150 2675

143

90 2675

144

30 2675

145

-30 2675

146

-90 2675

147

-150 2675

148

-210 2675

149

-270 2675

150

NJU6682

PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)

201 C
202 C
203 C
204 C
205 C
206 C
207 C
208 C
209 C
210 S
211 S
212 S
213 S
214 S
215 S
216 S
217 S
218 S
219 S
220 S
221 S
222 S
223 S
224 S
225 S
226 S
227 S
228 S
229 S
230 S
231 S
232 S
233 S
234 S
235 S
236 S
237 S
238 S
239 S
240 S
241 S

-330 2675 251 S90 -3330 2675

151

-390 2675 252 S89 -3390 2675

152

-450 2675 253 S88 -3450 2675

153

-510 2675 254 S87 -3510 2675

154

-570 2675 255 S86 -3570 2675

155

-630 2675 256 S85 -3630 2675

156

-690 2675 257 S84 -3690 2675

157

-750 2675 258 S83 -3750 2675

158

-810 2675 259 S82 -3810 2675

159

-870 2675 260 S81 -3870 2675

131

-930 2675 261 S80 -3930 2675

130

-990 2675 262 S79 -3975 2517

129

-1050 2675 263 S78 -3975 2457

128

-1110 2675 264 S77 -3975 2397

127

-1170 2675 265 S76 -3975 2337

126

-1230 2675 266 S75 -3975 2277

125

-1290 2675 267 S74 -3975 2217

124

-1350 2675 268 S73 -3975 2157

123

-1410 2675 269 S72 -3975 2097

122

-1470 2675 270 S71 -3975 2037

121

-1530 2675 271 S70 -3975 1977

120

-1590 2675 272 S69 -3975 1917

119

-1650 2675 273 S68 -3975 1857

118

-1710 2675 274 S67 -3975 1797

117

-1770 2675 275 S66 -3975 1737

116

-1830 2675 276 S65 -3975 1677

115

-1890 2675 277 S64 -3975 1617

114

-1950 2675 278 S63 -3975 1557

113

-2010 2675 279 S62 -3975 1497

112

-2070 2675 280 S61 -3975 1437

111

-2130 2675 281 S60 -3975 1377

110

-2190 2675 282 S59 -3975 1317

109

-2250 2675 283 S58 -3975 1257

108

-2310 2675 284 S57 -3975 1197

107

-2370 2675 285 S56 -3975 1137

106

-2430 2675 286 S55 -3975 1077

105

-2490 2675 287 S54 -3975 1017

104

-2550 2675 288 S53 -3975 957

103

-2610 2675 289 S52 -3975 897

102

-2670 2675 290 S51 -3975 837

101

-2730 2675 291 S50 -3975 777

100

242 S99 -2790 2675 292 S49 -3975 717
243 S98 -2850 2675 293 S48 -3975 657
244 S97 -2910 2675 294 S47 -3975 597
245 S96 -2970 2675 295 S46 -3975 537
246 S95 -3030 2675 296 S45 -3975 477
247 S94 -3090 2675 297 S44 -3975 417
248 S93 -3150 2675 298 S43 -3975 357
249 S92 -3210 2675 299 S42 -3975 297
250 S91 -3270 2675 300 S41 -3975 237

PAD No. Terminal X(um) Y(um)

301 S40 -3975 177
302 S39 -3975 117
303 S38 -3975 57
304 S37 -3975 -2
305 S36 -3975 -62
306 S35 -3975 -122
307 S34 -3975 -182
308 S33 -3975 -242
309 S32 -3975 -302
310 S31 -3975 -362
311 S30 -3975 -422
312 S29 -3975 -482
313 S28 -3975 -542
314 S27 -3975 -602
315 S26 -3975 -662
316 S25 -3975 -722
317 S24 -3975 -782
318 S23 -3975 -842
319 S22 -3975 -902
320 S21 -3975 -962
321 S20 -3975 -1022
322 S19 -3975 -1082
323 S18 -3975 -1142
324 S17 -3975 -1202
325 S16 -3975 -1262
326 S15 -3975 -1322
327 S14 -3975 -1382
328 S13 -3975 -1442
329 S12 -3975 -1502
330 S11 -3975 -1562
331 S10 -3975 -1622
332 S9 -3975 -1682
333 S8 -3975 -1742
334 S7 -3975 -1802
335 S6 -3975 -1862
336 S5 -3975 -1922
337 S4 -3975 -1982
338 S3 -3975 -2042
339 S2 -3975 -2102
340 S1 -3975 -2162
341 S0 -3975 -2222

NJU6682

A

r

NJU6682

■BLOCK DIAGRAM

Vss

Vdd

V1toV5

C1+

5

C1­C2+
C2­C3­C4­C5­C6-

VR

Voltage Generator

Reset

RES

Output Assignment Resister

Y Address Resister

I/O Buffer

C0 C159 S131 S0

SEG

Driver

132

Gray Scale/Black & White Control

132 x 2

Display Data Latch

COM

Driver

Register

Display Data RAM

132 x 2 x 160 x 2

Y Address Decoder

I/O Buffer

X Address Decoder

X Address Counter 6bit
X Address Resister 6bit

Multiplexer

Status

Instruction

Decoder

Internal Bus

0 CS WR RD

Shift

Z Address Decoder

BF

MPU Interface

SEL68

Bus Holder

P/S0

Z Counter

P/S1

Common

Timing

Generator

Z Registe

Generator

OSC

D0toD5
D6(SCL)
D7(SI)

Controler

FRC/PWM

Display

Timing

D8toD15

OSC1
OSC2

■■■■TERMINAL DESCRIPTION

No. Symbol I/O Function

2 to 4 DUMMY

1,42,49 VDD Power 2.4V to 3.3V

9,32 VSS GND GND

48
47
46
45
44

V1
V2
V3
V4
V5

Power

41
40
39
38
37
36
35
34

33 VOUT O

C1+

C1-

C2+

C2­C3­C4­C5­C6-

O

43 VR I

16

to

23
(23)
(22)

D0

to

D7

(SI)

(SCL)

I/O

Dummy Terminals.
These terminals are insulated.

LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not
used, supply each level of LCD driving voltage from outside with following relation.

VDD≥V1≥V2≥V3≥V4≥V5

When the internal power supply is used, the internal circuits generate and supply
following LCD bias voltage from V1 to V4 terminals.

Step up capacitor connecting terminals.
Voltage booster circuit ( adjustable with 2 to 7 times )

Step up voltage output terminal. Connect the step up capacitor between this terminal
and VSS.
Voltage adjust terminal. V5 level is adjusted by external bleeder resistance connecting
between VDD and V5 terminal.
( P/S="H" )In Pararel Interface Mode

( P/S="L" )In Serial Interface Mode

( CS=”H” ) D0 to D7 shown Hi-Z.

Bias V1 V2 V3 V4
1/4Bias V5+3/4Vlcd V5+2/4Vlcd V5+2/4Vlcd V5+1/4Vlcd
1/5Bias V5+4/5Vlcd V5+3/5Vlcd V5+2/5Vlcd V5+1/5Vlcd
1/6Bias V5+5/6Vlcd V5+4/6Vlcd V5+2/6Vlcd V5+1/6Vlcd
1/7Bias V5+6/7Vlcd V5+5/7Vlcd V5+2/7Vlcd V5+1/7Vlcd
1/8Bias V5+7/8Vlcd V5+6/8Vlcd V5+2/8Vlcd V5+1/8Vlcd
1/9Bias V5+8/9Vlcd V5+7/9Vlcd V5+2/9Vlcd V5+1/9Vlcd

1/10Bias V5+9/10Vlcd V5+8/10Vlcd V5+2/10Vlcd V5+1/10Vlcd
1/11Bias V5+10/11Vlcd V5+9/11Vlcd V5+2/11Vlcd V5+1/11Vlcd
1/12Bias V5+11/12Vlcd V5+10/12Vlcd V5+2/12Vlcd V5+1/12Vlcd
1/13Bias V5+12/13Vlcd V5+11/13Vlcd V5+2/13Vlcd V5+1/13Vlcd
1/14Bias V5+13/14Vlcd V5+12/14Vlcd V5+2/14Vlcd V5+1/14Vlcd

8-bit bus mode*1: I/O terminals for 8-bit bus.

•

16-bit bus mode*1: I/O terminals for the 8-bits of lower ranks of 16-bit bus.

•

1

To set these 8-bit / 16-bit mode, use Instruction ” 8-bit / 16-bit Bus

*

Select ”.

D7: Input terminal for serial data ( SI ).

•

D6: Input terminal for serial data clock ( SCL ).

•

When select these mode, D0 to D5 will be Hi-Z status.

NJU6682

(Vlcd=Vdd-V5)

No. Symbol I/O Function

24

to

30

D8

to

D15

13 A0 I

8 RES I

I/O

8-bit Bus Mode & Serial Mode

Output terminal with Hi-Z status.

•

16-bit Bus Mode

I/O terminals for the upper 8-bits of 16-bit bus.

•

Normaly, connect to the address bus of MPU. The data on the D0 to D7 is
distinguished as Display Data or Instruction by status of A0.

PS1 terminal PS0 terminal Ao terminal Distinction

Reset terminal. When the RES terminal goes to “L”, the initialization is performed.
Reset operation is executing during “L” state of RES.

H

L



H

L

12 CS I

15

RD I

(E) I

WR I

14

(R/W) I

7 SEL68 I

6
5

PS0
PS1

10
11

OSC1
OSC2

I

I/O

Chip serect terminal. Data Input/Output are available during CS=”L”.
< In case of 80 type MPU ( PS1=”H”, SEL68=”L” ) >

RD signal of 80 type MPU input terminal. Active “L”.
During this signal is “L”, D0 to D7 terminals are output.

< In case of 68 type MPU ( PS1=”H”, SEL68=”H” ) >
Enable signal of 68 type MPU input terminal. Active “H”.

< In case of 80 type MPU ( PS1=”H”, SEL68=”L” ) >
Connect to the 80 type MPU WR signal. Active “L”.
The data on the data bus input syncronizeing the rise edge of this terminal.

< In case of 68 type MPU ( PS1=”H”, SEL68=”H” ) >
The read / Write control signal of 68 type MPU input terminal.

R/W H L

State Read Write

MPU interface type selection terminal.

SEL68 H L

State 68 type 80 type

Serial or parallel type interface selection terminal.

PS1 PS0 Interface

“H” - Parallel CS A0 RD WR

“L”

“H”

“L”

Serial
4-wire
Serial
3-wire

Chip

Select

CS A0 SI(D7)

CS

The 17th data of serial

data is recognized as A0.

•

In case of serial interface ( PS1=0 ), RD and WR must be fixed to “H” or “L”,
and D0 to D5 will be Hi-Z.
System clock input terminal for Maker testing. ( This terminal should be Open )
For external clock operation, the clock should be input to OSC1 terminal.

NJU6682

H Display Data

L Instruction

H Display Data

L Instruction



Data/

Command

The 17th data of serial

data is recognized as A0.

 : H or L

Data

SI(D7)

Read/

Write
Write

Only

Write

Only

Write

Only

Serial

Clock

-

SCL
(D6)
SCL
(D6)

NJU6682

No Symbol I/O Function

50

to

209

341

to

210

C0

to

C159

S0

to

S131

O

LCD driving signal output terminal.

•Common output terminal :C0 to C159

•Segment output terminal :S0 to S131

•Segment output terminal

The following output voltage are selected by the combination of
FR and data in the RAM.

RAM Data

H

L

•Common output terminal
The following output voltage are selected by the combination of FR
and status of common.

Scan Data Alternating

H

L

Alternating
Signal

H VDD V2

L V5 V3

H V2 VDD

L V3 V5

Signal

H V5

L VDD

H V1

L V4

Disp. Positive Disp. Negative

COn Output Voltage

Sn OutPut Voltage

NJU6682

Functional Description
(1)Description for each blocks
1-1) Busy Flag (BF)

As for NJU6682, in c ase of the inner oper ation, busy flag ( BF) doesn't accept an ins truction except of "1". In the
status reed instructio n, a busy flag is outp ut by the D7 terminal. If c ycle time (tcyc) is sec ured, to check this f lag in
front of the instruction isn't necessary and the throughput of the CPU can be substantially improved.

1-2) X-Address Counter

The X-address counter is t he 6 bit pr esetta ble c ounter whic h gi ves an addr es s f or the row of the disp la y data RAM
as shown in figure 1 and is don e in +1 increment by the execut ion of the dis play data read / write instruct ion. But,
when the X-address count er reaches the maximum of the exist address, the count lock s by the X-address counter.
With to set X-address once again, as for the count lock of cancellation again this counter is independent with
Y-address register.

By the address inver se instruction(ADC), it is possible for X -address decoder to r everse correspondence r elation
between X-address and segment output of display data RAM.

1-3)Z-Address counter

The Y-address counter ge nerates an addr ess to the display RAM direction of the line, it is res et when th e inn er FR
signal switching timing and count up synchronizes with common cycle of NJU6682.

1-4)Y-Address Register

Y-address register is which gives an address to the displ ay data RAM direction of the line as sho wn in figure 1.
When replacing Y-address from the CPU and accessing to them, it does by the instruction of the set of Y-address.

1-5)Z-Address Register

Z-address register can be generally used for the sc rolling of a screen, in additi on to the display with the regis ter
which sets the low addr ess of the data R AM which c orres ponds to the dis play line ( being the best line gen erally ) of
COM0. It sets a display beginning line by setting the display beginning address of 9 bits in this register by the
instruction of the set of Z-address.

1-6)Display data RAM

Display data RAM is t he bit map RAM which stores the data for the displa y which corresponds to the LCD pixel
and is composed of 84,480 bits . Eac h bit of the disp lay da ta RAM c orres ponds to 2:1 in case of gra y scale dis pla y to
each pixel of L CD and in case of Blac k and White displa y, it corresponds to 1: 1. The relation betwe en the display
data and the LCD in case of gray scale display is as follows.

The relation between Display data and LCD in Gray Scale Display

The Display RAM data : "00" = Gray Scale Level 0 ( setting by the gray scale level select )
The Display RAM data : "01" = Gray Scale Level 1 ( “ )
The Display RAM data : "10" = Gray Scale Level 2 ( “ )
The Display RAM data : "11" = Gray Scale Level 3 ( “ )

The relation between Display data and LCD in Black and White Display

In Positive Display : "1"=Turn-On Display,"0" =Turn-Off Display
In Negative Display: "1"=Turn-Off Display,"0" =Turn-On Display

When the Displa y method chooses 16 bit access by the gray scale displa y, beca use RAM area of X-addres s = 16
become 8 bits, lo wer 8bit (D7-D0) is ignored ( F igure 1-1 ). W hen the dis play method c hooses 16 bit access by the
Black and W hite display, as for RAM area of X-address = 8 (Layer 0) or 40 (Layer1) becomes 4-bits, lower 12 bit
(D11-D0) is ignored. The bus with in acces s to t he Display Data RAM is 8- bit ac ces s an d 16-b it ac c ess with the 8- bit
/ 16-bit Bus Select instruction. The access can be chosen.

(

)

(

)

(

)

(

)

Correspondence with Display Data RAM Address ( in gray scale mode)

ADC=0 ADC=1

D15

010000

X Address

D8

D14

D9

D12

D13

10H

D11

D10

00H

000000

D11

D9

D10

D12

D13

D14

D6

D7

D5

D4

D3

D2

D1

D2

(001111)

D3

D4

D5

D0

0FH

D6

D7

D11

D9

D8

D10

D12

D13

D14

D15

D8

D0

D1

D15

Y
Address

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12

138
139
13A
13B
13C
13D
13E
13F

Sn

0

1 2 3 4 5 6 7

Output

Fig.1-1

NJU6682

0FH

000000

D11

D9

D6

D7

D5

D4

D3

D8

D10

D12

D13

D14

D15

(000000)

D0

D1

D2

D3

D4

126

125

124

10H

010000

D11

D2

D1

D0

D14

D15

D8

D9

D10

D12

D13

0

D6

D7

127

D8

D9

128

D10

D11

129

D12

D13

130

D14

D15

131

D5

0

(

)

(

)

(

)

(

)

3

5 6

0

3

5 6

Correspondence with Display Data RAM Address ( in black & white mode)

X Address

Y
address

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12

ADC=0 ADC=1

D15

8H

(001000)

D12

D14

D13

D13

D14

D12

D15

000000

D11

D9

D10

D0

D1

D2

0H

D8

D3

D6

D7

D5

D4

7H

(000111)

D4

D5

D6

D7

7H

000111

D3

D2

D1

D0

D11

D9

D6

D7

D5

D4

D8

D10

D12

D13

D14

D15

0H

D11

D9

D8

D10

D12

D13

D14

D15

(000000)

D0

D1

D2

D3

D4

D5

D6

D7

8H

(001000)

D3

D2

D1

D0

D14

D15

D13

D12

D14

D15

28H

D11

D9

D8

D10

(101000)

D12

D13

D14

D15

D12

D13

Layer 0

138
139
13A
13B
13C
13D
13E
13F

1

Sn

Output

2

4

7

124

125

126

127

128

129

130

131

Fig.1-1

NJU6682

D13

D14

D12

D15

20H

100000

D11

D9

D10

D0

D1

D2

D6

D7

D8

(100111)

D3

D4

D5

D5

D4

27H

D6

D7

D3

D2

D1

D0

D15

D11

D9

D8

D10

D12

D13

D14

D15

27H

100111

D11

D9

D6

D7

D5

D4

D8

D10

D12

D13

D14

20H

(100000)

D0

D1

D2

D3

D4

D5

D6

D7

Layer 1

1

2

4

7

D3

D8

124

D2

D9

125

D1

D10

126

28H

(101000)

D0

D14

D15

D11

D12

D13

127

128

129

D13

D14

130

D12

D15

131

NJU6682

1-7)Output Assignment Register
This circuit can choose the direction of the scan of the common output.

Table1

PAD No. 50 209

Terminal

Name
Ver. A COM0 COM159
Ver. B COM159 COM0

•Able to be changed with the mask option of it by the choice (version A or B) to the common scan direction.
1-8)Reset Circuit
This reset circuit does following initialization when the RES input becomes “L” level.

•The initialization condition (The default setting)

1.It sets a display method in the 4 Gray Scale Display Mode.

2.Display Off

3.Display Positive

4.ADC select ; Positive

5.Read Modify Write

6.Voltage Booster off, Voltage Regulator off, Voltage follower off

7.Static Drive off

8.Driver output off

9.Clear the register data of serial interface

10.Set the X-address counter to (00)h

11.Set the Y-Address register to (00)h

12.Set the Z-Address at (00)h

13.The continuous RAM address(Variable RAM Mapping Mode)

14.Set the EVR register to (FF)h

15.Set the Duty 1/160 (Whole Display On)

16.Bias select D3,2,1,0="1,0,1,0" (1/14 Bias)

17.Voltage Booster Select D2,1,0,="1,0,1" ((7 times)

18.Set n-line inverting register to (0)h

19.Set to 8 Bit bus interface mode
To be in " the MPU interf ace ( the r eferenc e exam ple ) ", the RES ter m inal m ake connec t with th e reset ter m inal of

the MPU and does at the same time as a MPU is initialized. The reset signal must put "L" pulse above minimum 10us
to be in the clause of " the DC c haracteristic ". The RES s ignal becomes an ope ration condition gener ally after 1us
from the rise-up edge.

When not using a built- in LCD power suppl y circuit in NJU6682, in c ase of the outside li quid crystal po wer supply

turning on, it is neces sary to be RES="L". It c lears each register b y RES="L" and it is set in the above initializa tion
condition but it doesn't have an influence about the oscillation circuit and output terminal (D0-D15).

When initializat ion by the RES terminal isn't acc omplished in power suppl y impress ing, it sometimes enters the

condition about which it is impossible to cancel.

When using a reset instruction, 9 - 19 of the above initialization are executed.

C0 C159

Common Output Terminal

NJU6682

1-9)The LCD drive circuit system

1-9-1)The LCD drive circuit

The common output h as a shift register and it forwards a common scan sig nal in order. It outputs liqui d crystal

drive voltage in t he combination of the display data, t he common sc an signal, the inner FR signal, the liq uid crystal
flowing mutually signal. A segment, common output corrugated example are shown in figure 2.

1-9-2)Display Data Latch-Circuit

The display data l atch circuit is the latc h which stores the disp lay data of 132 x 2 bits which are addres sed by the

Z-address counter and are output from the display data RAM to the LCD drive circuit every 1 comm on 1 period
temporarily. Data in the display data RAM is changed and not hel d because displa y turn to Positive / Negative ( In
case of Black & W hite display ),displa ying on / off, Static Drive O n / Off instructions ar e controls data in this latc h
circuit.

1-9-3)Gray Scale / Black & White Control Circuit

A Gray Scale control c ircuit chooses the gr ay scale lev el which was s et b y the co mmand ins truction from the gra y

scale data of 264 b its which latc hed with the displa y data latc h circuit a nd is out put for LCD drive out put Sn. A Black
& White displa y control cir cuit chooses layer which was set by the com mand instruction from the 264 bit Black &
White data which latched with the display data latch circuit and is output for LCD drive output Sn.

1-9-4)Z-Counter, Signal Genelate of Display Data Latch Circuit

It generates a latch s ignal to the clock(CL) to Z-counter and to the dis play data latch circuit . It synchronizes with

the internal displa y clock and the line addr ess of the display dat a RAM occurs, and the d isplay data of 132 x 2 bits
synchronizes with the displa y clock, latch es by the display dat a latch cir cuit and i s output b y the gra y scale contr ol /
Black & White disp la y control c ircuit. T he read out t o the disp la y data LCD dr ive c irc uit is i ndepen dent tota lly with t he
access to the display data RAM from the CPU.

1-9-5)Display Timing Genelate Circuit

The display timing occ urrence circuit generates th e internal timing of the displ ay system by the master clock and

the internal FR signal. As f or it, th e in tern a l FR s ig nal and th e LCD f lo win g mutually signal mak e the dr ive c o rr ugati on
of the 2 frame alternating current drive or the n-line inverting drive method occur to the LCD Driving circuit.

1-9-6)FRC / PWM Control Circuit

PWM & FRC(Frame Rate Control) to realize 4Gray Scale display function.

1-9-7)Common Timing Genegation
The common timing is generated by display clock CL ( refer to Fig. )

① 2 frame alternating current drive mode

159 160 1 2 3 4 5 6 7 8 158 159 160 1 2 3 4 5 6 7

CL

FR

C0

C1

RAM DATA

Sn

② n-line inverting drive mode

159 160 1 2 3 4 5 6 7 8 158 159 160 1 2 3 4 5 6 7

CL

FR

C0

C1

RAM DATA

Sn

Fig.2 Waveform of Display Timing

NJU6682

Vdd
V1

V4
V5
Vdd

V1

V4
V5

Vdd
V2

V3
V5

Vdd
V1

V4
V5
Vdd

V1

V4
V5

Vdd
V2

V3
V5

NJU6682

1-9-8)Oscillation Circuits
The Oscillation C irc uit is a l ow p ower CR osc illator incor porating with a Resistor and a Capacitor . it gener at es cloc ks
for display timing signal source and the clock for step up circuits for LCD driving. The oscillation circuit output
frequency is divided as display clock CL.

Table 3

Duty

Divide

Duty

Divide

Duty

Divide

1-9-9)Power Supply Circuits

Internal Power Suppl y Circuit gener ates voltage for LCD driving. The po wer supply circuits consists of Step Up

Circuits ( 2 tim es to 7 times ), Regu lator Circ uits, and Voltage F ollowers. T he internal Po wer Supply is des igned for
small size LCD panel, therefore it is not suitable for the large size LCD panel application, please supply the external.
The suitable value of the capacitors connecting to the V1 to V5 term inals and the s tep up circ uit, and the feedback
resistors for V5 op erational amplifier dep end on the LCD panel. A nd the power consum ption with the LCD panel is
depending on the display pattern. Please evaluate with actual LCD module.

The operation of Internal Power Supply Circuits is controlled by the Internal Power Supply Control Instruction.

A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 0 0 1 0 0 0 1 * * * * * DC VR VF

DC : Step Up Circuit

DC=1 : Step Up Circuit ON
DC=0 : Step Up Circuit O FF ( In this tim e, terminals C1+,C1-,C2 +,C2-,C3-,C4-,C5- and C6- should be open, a nd

VR : Regulator Circuit

VR=1 : Regulator Circuit ON
VR=0 : Regulator Circuit OFF ( In this time, terminal VR should be open, and V5 should be supplied from outside. )

VF : Voltage Follower

VR=1 : Voltage Follower ON
VR=0 : Voltage Follower OFF ( In this time, terminals V1 to V5 should be supplied from outside. )

1/4 1/8 1/12 1/16 1/20 1/24 1/28 1/32 1/36 1/40 1/44, 1/48 1/52, 1/56

1/1200 1/600 1/400 1/300 1/240 1/200 1/170 1/150 1/135 1/120 1/105 1/90

1/60, 1/64, 1/68 1/72, 1/76, 1/80, 1/84, 1/88 1/92, 1/96, 1/100, 1/104, 1/108, 1/112, 1/116, 1/120

1/75 1/60 1/45

1/124, 1/128, 1/132, 1/136, 1/140, 1/144, 1/148, 1/152, 1/156, 1/160

1/30

( R / W )

*:Don’t Care

VOUT should be supplied from outside. )

Examples for application circuits of the internal Power Supply
①None of the internal power supply functions ②All of the internal power supply functions.

( Step Up, Voltage Regulator, Voltage Follower )

( DC,VR,VF ) = ( 0, 0, 0 ) ( DC,VR,VF ) = ( 1, 1, 1 )

VDD

VDD

NJU6682

NJU6682

V1
V2
V3
V4
V5

VOUT
VSS

+

V1

+

V2

+

V3

+

V4

+

V5

+

VOUT
VSS

③Some of the internal power supply functions ④Some of the internal power supply functions.
( Voltage Regulator, Voltage Follower ) ( Voltage Follower )

( DC,VR,VF ) = ( 0, 1, 1 ) ( DC,VR,VF ) = ( 0, 0, 1 )

VDD

VDD

NJU6682

NJU6682

+
+

+
+
+

V1
V2
V3
V4
V5

VOUT
VSS

+

V1

+

V2

+

V3

+

V4
V5

VOUT
VSS

( Caution ) : These switches should be open during the power save mode.

NJU6682