■GENERAL DESCRIPTION ■PACKAGE OUTLINE
The NJU6682 is a b it map LC D dr iver to d ispla y graphic s or charac ters.
It contains 84,480 bits displ ay data RAM, m icr oprocess or interf ace cir cuits,
instruction decoder, and 160-common and 132-segment drivers.
The bit image data is transferred to the internal display data RAM by
serial interface or 8-bit/16-bit parallel interface.
The NJU6682 features 4- gray scale f unct ion whic h c reates 4 t ypes gra y
scale (for exam ple : white/light gray/dark gray/bl ack) or black & white with
displays 160 x 132 dots graphics or 8-caracter 10line by 16 x 16 dots
characters.
It oscillates by built-in OSC circuit without any external components.
Furthermore, the NJU6682 features Partial Display Function which
creates up to 2 blocks of activ e dis p lay area and optimizes duty cycle ratio.
This function sets opt imum boosted vol tage by the com bination with both
of programmable vo ltage booster circuit an d e lec tric a l var i able r es ister . As
result, it reduces the operating current.
The operating voltage f rom 2.4V to 3.3V and low o perating current are
useful for small size battery operating items.
■FEATURES
●Direct Correspondence between Display Data RAM and LCD Pixel
●Display Data RAM - 84,480 bits ;( 160-Com x 132-Seg) x 2-area ) x 2bit
….2 times over than display size
●Display Method – Monochrome 4-Gray Scale / Black & White
●Partial Display Function
( 2 blocks of active display area and automatic duty cycle ratio selection )
●Variable RAM Mapping
– The display screen can be composed from the RAM area in a maximum of 8 blocks not to continue.
●Easy Vertical Scroll by the variable start line address and over size display data RAM
(This function doesn’t work in Variable RAM Mapping mode )
●LCD drivers – 160-common and 132-segment
●Direct 8-bit / 16-bit Microprocessor interface for both of 68 type and 80 type MPU
Version C0 to C159( Pin Name )
NJU6682A COM0 to COM159
NJU6682B COM159 to COM0
●Useful Instruction Set
Display Data Read/W rite, Display ON/O FF, Z-Address Set, X-Address S et, Y-Address Set, Status Read, Norm al or
Inverse ON/OFF, Static Drive ON/OFF, Partial Display, n-Line I nverse, EVR Resister Set, Variable RAM Mapp ing
Mode, Gray Sca le Level Select, B ias Select, Voltag e Converter Multiple Select ( 7-times maximum ), Read Mod ify
Write, Reset ,Internal Power Supp ly, Driver Outputs ON/OFF, Po wer Save, ADC Sel ect, Displa y Mode Selec t, 8-bit /
16-bit Buss Select, etc.
●Power Supply Circuit for LCD; Programmable Booster Circuits( 7-time maximum ), Regulator, Voltage Follower x 4
●Precision Electrical Variable Resistance
●Low Power Consumption T.B.D ( typ. )
●Operating Voltage 2.4 to 3.3 V
●LCD Driving Voltage 6.0 to 18.0V
●Package Outline Bumped Chip / TCP
●C-MOS Technology
NJU6682CH
MAY 2000 Ver-1.3
■PAD LOCATION
S
S
80
81
S79
78
S
S1
S
0
DUMMY0
DUMMY1
V
DD
Chip Center :X=0um,Y=0um
Chip Size :X=8.27m,Y=5.67mm
Chip Thickness :675um ± 30um
Bump Size :45um x 83um
Pad Pitch :60um (min)
Bump Heght :15um (typ)
Bump Material :Au
NJU6682
S
C
S
C
130
131
159
158
Y
X
CS
PS
0
SEL68
RES
V
OSC
SS
1
2
DUMMY2
PS
1
RD
A0
D
WR
D
D
D
1
2
0
D
D
D
D
4
3
D
D
6
5
7
8
9
(SCL)
(SI)
OSC
D
D
D
D
13
12
11
10
V
C4
C6
V
C5
C2
D
D
OUT
SS
14
15
C3
-
-
-
-
-
C2
V
V
VR
C1
C1
+
-
5
DD
+
C
C
81
80
C79
78
C
C1
C
0
V
V
V
V
V
4
DD
3
1
2
■ PAD Cordinates
PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)
PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)
101 C51 3975 874 151 C
102 C52 3975 934 152 C
103 C53 3975 994 153 C
104 C54 3975 1054 154 C
105 C55 3975 1114 155 C
106 C56 3975 1174 156 C
107 C57 3975 1234 157 C
108 C58 3975 1294 158 C
109 C59 3975 1354 159 C
110 C60 3975 1414 160 C
111 C61 3975 1474 161 C
112 C62 3975 1534 162 C
113 C63 3975 1594 163 C
114 C64 3975 1654 164 C
115 C65 3975 1714 165 C
116 C66 3975 1774 166 C
117 C67 3975 1834 167 C
118 C68 3975 1894 168 C
119 C69 3975 1954 169 C
120 C70 3975 2014 170 C
121 C71 3975 2074 171 C
122 C72 3975 2134 172 C
123 C73 3975 2194 173 C
124 C74 3975 2254 174 C
125 C75 3975 2314 175 C
126 C76 3975 2374 176 C
127 C77 3975 2434 177 C
128 C78 3975 2494 178 C
129 C79 3975 2554 179 C
130 C80 3930 2675 180 C
131 C81 3870 2675 181 C
132 C82 3810 2675 182 C
133 C83 3750 2675 183 C
134 C84 3690 2675 184 C
135 C85 3630 2675 185 C
136 C86 3570 2675 186 C
137 C87 3510 2675 187 C
138 C88 3450 2675 188 C
139 C89 3390 2675 189 C
140 C90 3330 2675 190 C
141 C91 3270 2675 191 C
142 C92 3210 2675 192 C
143 C93 3150 2675 193 C
144 C94 3090 2675 194 C
145 C95 3030 2675 195 C
146 C96 2970 2675 196 C
147 C97 2910 2675 197 C
148 C98 2850 2675 198 C
149 C99 2790 2675 199 C
150 C
2730 2675 200 C
100
2670 2675
101
2610 2675
102
2550 2675
103
2490 2675
104
2430 2675
105
2370 2675
106
2310 2675
107
2250 2675
108
2190 2675
109
2130 2675
110
2070 2675
111
2010 2675
112
1950 2675
113
1890 2675
114
1830 2675
115
1770 2675
116
1710 2675
117
1650 2675
118
1590 2675
119
1530 2675
120
1470 2675
121
1410 2675
122
1350 2675
123
1290 2675
124
1230 2675
125
1170 2675
126
1110 2675
127
1050 2675
128
990 2675
129
930 2675
130
870 2675
131
810 2675
132
750 2675
133
690 2675
134
630 2675
135
570 2675
136
510 2675
137
450 2675
138
390 2675
139
330 2675
140
270 2675
141
210 2675
142
150 2675
143
90 2675
144
30 2675
145
-30 2675
146
-90 2675
147
-150 2675
148
-210 2675
149
-270 2675
150
NJU6682
PAD No. Terminal X(um) Y(um) PAD No. Terminal X(um) Y(um)
201 C
202 C
203 C
204 C
205 C
206 C
207 C
208 C
209 C
210 S
211 S
212 S
213 S
214 S
215 S
216 S
217 S
218 S
219 S
220 S
221 S
222 S
223 S
224 S
225 S
226 S
227 S
228 S
229 S
230 S
231 S
232 S
233 S
234 S
235 S
236 S
237 S
238 S
239 S
240 S
241 S
LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not
used, supply each level of LCD driving voltage from outside with following relation.
VDD≥V1≥V2≥V3≥V4≥V5
When the internal power supply is used, the internal circuits generate and supply
following LCD bias voltage from V1 to V4 terminals.
Step up capacitor connecting terminals.
Voltage booster circuit ( adjustable with 2 to 7 times )
Step up voltage output terminal. Connect the step up capacitor between this terminal
and VSS.
Voltage adjust terminal. V5 level is adjusted by external bleeder resistance connecting
between VDD and V5 terminal.
( P/S="H" )In Pararel Interface Mode
16-bit bus mode*1: I/O terminals for the 8-bits of lower ranks of 16-bit bus.
•
1
To set these 8-bit / 16-bit mode, use Instruction ” 8-bit / 16-bit Bus
*
Select ”.
D7: Input terminal for serial data ( SI ).
•
D6: Input terminal for serial data clock ( SCL ).
•
When select these mode, D0 to D5 will be Hi-Z status.
NJU6682
(Vlcd=Vdd-V5)
No. Symbol I/O Function
24
to
30
D8
to
D15
13 A0 I
8 RES I
I/O
8-bit Bus Mode & Serial Mode
Output terminal with Hi-Z status.
•
16-bit Bus Mode
I/O terminals for the upper 8-bits of 16-bit bus.
•
Normaly, connect to the address bus of MPU. The data on the D0 to D7 is
distinguished as Display Data or Instruction by status of A0.
PS1 terminal PS0 terminal Ao terminal Distinction
Reset terminal. When the RES terminal goes to “L”, the initialization is performed.
Reset operation is executing during “L” state of RES.
H
L
H
L
12 CS I
15
RD I
(E) I
WR I
14
(R/W) I
7 SEL68 I
6
5
PS0
PS1
10
11
OSC1
OSC2
I
I/O
Chip serect terminal. Data Input/Output are available during CS=”L”.
< In case of 80 type MPU ( PS1=”H”, SEL68=”L” ) >
RD signal of 80 type MPU input terminal. Active “L”.
During this signal is “L”, D0 to D7 terminals are output.
< In case of 68 type MPU ( PS1=”H”, SEL68=”H” ) >
Enable signal of 68 type MPU input terminal. Active “H”.
< In case of 80 type MPU ( PS1=”H”, SEL68=”L” ) >
Connect to the 80 type MPU WR signal. Active “L”.
The data on the data bus input syncronizeing the rise edge of this terminal.
< In case of 68 type MPU ( PS1=”H”, SEL68=”H” ) >
The read / Write control signal of 68 type MPU input terminal.
R/W H L
State Read Write
MPU interface type selection terminal.
SEL68 H L
State 68 type 80 type
Serial or parallel type interface selection terminal.
PS1 PS0 Interface
“H” - Parallel CS A0 RD WR
“L”
“H”
“L”
Serial
4-wire
Serial
3-wire
Chip
Select
CS A0 SI(D7)
CS
The 17th data of serial
data is recognized as A0.
•
In case of serial interface ( PS1=0 ), RD and WR must be fixed to “H” or “L”,
and D0 to D5 will be Hi-Z.
System clock input terminal for Maker testing. ( This terminal should be Open )
For external clock operation, the clock should be input to OSC1 terminal.
NJU6682
H Display Data
L Instruction
H Display Data
L Instruction
Data/
Command
The 17th data of serial
data is recognized as A0.
: H or L
Data
SI(D7)
Read/
Write
Write
Only
Write
Only
Write
Only
Serial
Clock
-
SCL
(D6)
SCL
(D6)
NJU6682
No Symbol I/O Function
50
to
209
341
to
210
C0
to
C159
S0
to
S131
O
LCD driving signal output terminal.
•Common output terminal :C0 to C159
•Segment output terminal :S0 to S131
•Segment output terminal
The following output voltage are selected by the combination of
FR and data in the RAM.
RAM Data
H
L
•Common output terminal
The following output voltage are selected by the combination of FR
and status of common.
Scan Data Alternating
H
L
Alternating
Signal
H VDD V2
L V5 V3
H V2 VDD
L V3 V5
Signal
H V5
L VDD
H V1
L V4
Disp. Positive Disp. Negative
COn Output Voltage
Sn OutPut Voltage
NJU6682
Functional Description
(1)Description for each blocks
1-1) Busy Flag (BF)
As for NJU6682, in c ase of the inner oper ation, busy flag ( BF) doesn't accept an ins truction except of "1". In the
status reed instructio n, a busy flag is outp ut by the D7 terminal. If c ycle time (tcyc) is sec ured, to check this f lag in
front of the instruction isn't necessary and the throughput of the CPU can be substantially improved.
1-2) X-Address Counter
The X-address counter is t he 6 bit pr esetta ble c ounter whic h gi ves an addr es s f or the row of the disp la y data RAM
as shown in figure 1 and is don e in +1 increment by the execut ion of the dis play data read / write instruct ion. But,
when the X-address count er reaches the maximum of the exist address, the count lock s by the X-address counter.
With to set X-address once again, as for the count lock of cancellation again this counter is independent with
Y-address register.
By the address inver se instruction(ADC), it is possible for X -address decoder to r everse correspondence r elation
between X-address and segment output of display data RAM.
1-3)Z-Address counter
The Y-address counter ge nerates an addr ess to the display RAM direction of the line, it is res et when th e inn er FR
signal switching timing and count up synchronizes with common cycle of NJU6682.
1-4)Y-Address Register
Y-address register is which gives an address to the displ ay data RAM direction of the line as sho wn in figure 1.
When replacing Y-address from the CPU and accessing to them, it does by the instruction of the set of Y-address.
1-5)Z-Address Register
Z-address register can be generally used for the sc rolling of a screen, in additi on to the display with the regis ter
which sets the low addr ess of the data R AM which c orres ponds to the dis play line ( being the best line gen erally ) of
COM0. It sets a display beginning line by setting the display beginning address of 9 bits in this register by the
instruction of the set of Z-address.
1-6)Display data RAM
Display data RAM is t he bit map RAM which stores the data for the displa y which corresponds to the LCD pixel
and is composed of 84,480 bits . Eac h bit of the disp lay da ta RAM c orres ponds to 2:1 in case of gra y scale dis pla y to
each pixel of L CD and in case of Blac k and White displa y, it corresponds to 1: 1. The relation betwe en the display
data and the LCD in case of gray scale display is as follows.
The relation between Display data and LCD in Gray Scale Display
The Display RAM data : "00" = Gray Scale Level 0 ( setting by the gray scale level select )
The Display RAM data : "01" = Gray Scale Level 1 ( “ )
The Display RAM data : "10" = Gray Scale Level 2 ( “ )
The Display RAM data : "11" = Gray Scale Level 3 ( “ )
The relation between Display data and LCD in Black and White Display
In Positive Display : "1"=Turn-On Display,"0" =Turn-Off Display
In Negative Display: "1"=Turn-Off Display,"0" =Turn-On Display
When the Displa y method chooses 16 bit access by the gray scale displa y, beca use RAM area of X-addres s = 16
become 8 bits, lo wer 8bit (D7-D0) is ignored ( F igure 1-1 ). W hen the dis play method c hooses 16 bit access by the
Black and W hite display, as for RAM area of X-address = 8 (Layer 0) or 40 (Layer1) becomes 4-bits, lower 12 bit
(D11-D0) is ignored. The bus with in acces s to t he Display Data RAM is 8- bit ac ces s an d 16-b it ac c ess with the 8- bit
/ 16-bit Bus Select instruction. The access can be chosen.
(
)
(
)
(
)
(
)
Correspondence with Display Data RAM Address ( in gray scale mode)
1-7)Output Assignment Register
This circuit can choose the direction of the scan of the common output.
Table1
PAD No. 50 209
Terminal
Name
Ver. A COM0 COM159
Ver. B COM159 COM0
•Able to be changed with the mask option of it by the choice (version A or B) to the common scan direction.
1-8)Reset Circuit
This reset circuit does following initialization when the RES input becomes “L” level.
•The initialization condition (The default setting)
1.It sets a display method in the 4 Gray Scale Display Mode.
2.Display Off
3.Display Positive
4.ADC select ; Positive
5.Read Modify Write
6.Voltage Booster off, Voltage Regulator off, Voltage follower off
19.Set to 8 Bit bus interface mode
To be in " the MPU interf ace ( the r eferenc e exam ple ) ", the RES ter m inal m ake connec t with th e reset ter m inal of
the MPU and does at the same time as a MPU is initialized. The reset signal must put "L" pulse above minimum 10us
to be in the clause of " the DC c haracteristic ". The RES s ignal becomes an ope ration condition gener ally after 1us
from the rise-up edge.
When not using a built- in LCD power suppl y circuit in NJU6682, in c ase of the outside li quid crystal po wer supply
turning on, it is neces sary to be RES="L". It c lears each register b y RES="L" and it is set in the above initializa tion
condition but it doesn't have an influence about the oscillation circuit and output terminal (D0-D15).
When initializat ion by the RES terminal isn't acc omplished in power suppl y impress ing, it sometimes enters the
condition about which it is impossible to cancel.
When using a reset instruction, 9 - 19 of the above initialization are executed.
C0 C159
Common Output Terminal
NJU6682
1-9)The LCD drive circuit system
1-9-1)The LCD drive circuit
The common output h as a shift register and it forwards a common scan sig nal in order. It outputs liqui d crystal
drive voltage in t he combination of the display data, t he common sc an signal, the inner FR signal, the liq uid crystal
flowing mutually signal. A segment, common output corrugated example are shown in figure 2.
1-9-2)Display Data Latch-Circuit
The display data l atch circuit is the latc h which stores the disp lay data of 132 x 2 bits which are addres sed by the
Z-address counter and are output from the display data RAM to the LCD drive circuit every 1 comm on 1 period
temporarily. Data in the display data RAM is changed and not hel d because displa y turn to Positive / Negative ( In
case of Black & W hite display ),displa ying on / off, Static Drive O n / Off instructions ar e controls data in this latc h
circuit.
1-9-3)Gray Scale / Black & White Control Circuit
A Gray Scale control c ircuit chooses the gr ay scale lev el which was s et b y the co mmand ins truction from the gra y
scale data of 264 b its which latc hed with the displa y data latc h circuit a nd is out put for LCD drive out put Sn. A Black
& White displa y control cir cuit chooses layer which was set by the com mand instruction from the 264 bit Black &
White data which latched with the display data latch circuit and is output for LCD drive output Sn.
1-9-4)Z-Counter, Signal Genelate of Display Data Latch Circuit
It generates a latch s ignal to the clock(CL) to Z-counter and to the dis play data latch circuit . It synchronizes with
the internal displa y clock and the line addr ess of the display dat a RAM occurs, and the d isplay data of 132 x 2 bits
synchronizes with the displa y clock, latch es by the display dat a latch cir cuit and i s output b y the gra y scale contr ol /
Black & White disp la y control c ircuit. T he read out t o the disp la y data LCD dr ive c irc uit is i ndepen dent tota lly with t he
access to the display data RAM from the CPU.
1-9-5)Display Timing Genelate Circuit
The display timing occ urrence circuit generates th e internal timing of the displ ay system by the master clock and
the internal FR signal. As f or it, th e in tern a l FR s ig nal and th e LCD f lo win g mutually signal mak e the dr ive c o rr ugati on
of the 2 frame alternating current drive or the n-line inverting drive method occur to the LCD Driving circuit.
1-9-7)Common Timing Genegation
The common timing is generated by display clock CL ( refer to Fig. )
① 2 frame alternating current drive mode
159 160 1 2 3 4 5 6 7 8158 159 160 1 2 3 4 5 6 7
CL
FR
C0
C1
RAM DATA
Sn
② n-line inverting drive mode
159 160 1 2 3 4 5 6 7 8158 159 160 1 2 3 4 5 6 7
CL
FR
C0
C1
RAM DATA
Sn
Fig.2 Waveform of Display Timing
NJU6682
Vdd
V1
V4
V5
Vdd
V1
V4
V5
Vdd
V2
V3
V5
Vdd
V1
V4
V5
Vdd
V1
V4
V5
Vdd
V2
V3
V5
NJU6682
1-9-8)Oscillation Circuits
The Oscillation C irc uit is a l ow p ower CR osc illator incor porating with a Resistor and a Capacitor . it gener at es cloc ks
for display timing signal source and the clock for step up circuits for LCD driving. The oscillation circuit output
frequency is divided as display clock CL.
Table 3
Duty
Divide
Duty
Divide
Duty
Divide
1-9-9)Power Supply Circuits
Internal Power Suppl y Circuit gener ates voltage for LCD driving. The po wer supply circuits consists of Step Up
Circuits ( 2 tim es to 7 times ), Regu lator Circ uits, and Voltage F ollowers. T he internal Po wer Supply is des igned for
small size LCD panel, therefore it is not suitable for the large size LCD panel application, please supply the external.
The suitable value of the capacitors connecting to the V1 to V5 term inals and the s tep up circ uit, and the feedback
resistors for V5 op erational amplifier dep end on the LCD panel. A nd the power consum ption with the LCD panel is
depending on the display pattern. Please evaluate with actual LCD module.
The operation of Internal Power Supply Circuits is controlled by the Internal Power Supply Control Instruction.
Examples for application circuits of the internal Power Supply
①None of the internal power supply functions ②All of the internal power supply functions.
③Some of the internal power supply functions ④Some of the internal power supply functions.
( Voltage Regulator, Voltage Follower ) ( Voltage Follower )