JRC NJU6679CL Datasheet

NJU6679NJU6679

PRELIMINARYPRELIMINARY

128-common x 132-segment128-common x 132-segment

BIT MAP LCD DRIVER BIT MAP LCD DRIVER

GENERAL DESCRIPTION GENERAL DESCRIPTION

The NJU6679 is a bit map LCD driver to display graphics or charac-The NJU6679 is a bit map LCD driver to display graphics or characters. It contains 25,344 bits display data RAM, microprocessor inter-ters. It contains 25,344 bits display data RAM, microprocessor interface circuits, instruction decoder, 132-segment and 128-common driv-face circuits, instruction decoder, 132-segment and 128-common drivers.ers. The bit image display data is transferred to the display data RAM byThe bit image display data is transferred to the display data RAM by serial or 8-bit parallel interface.serial or 8-bit parallel interface. The NJU6679 displays 128 x 132 dots graphics or 8-character 8-lineThe NJU6679 displays 128 x 132 dots graphics or 8-character 8-line by 16 x 16 dots character.by 16 x 16 dots character. It oscillates by built-in OSC circuit without any external components.It oscillates by built-in OSC circuit without any external components. Furthermore, the NJU6679 features Partial Display Function whichFurthermore, the NJU6679 features Partial Display Function which creates up to 2 blocks of active display area and optimizes duty cyclecreates up to 2 blocks of active display area and optimizes duty cycle ratio. This function sets optimum boosted voltage by the combinationratio. This function sets optimum boosted voltage by the combination with both of programmable 6-time voltage booster circuit and 201-with both of programmable 6-time voltage booster circuit and 201step electrical variable resistor. As result, it reduces the operating cur-step electrical variable resistor. As result, it reduces the operating current.rent. The operating voltage from 2.4V to 3.6V and low operating current areThe operating voltage from 2.4V to 3.6V and low operating current are useful for small size battery operating items.useful for small size battery operating items.

FEATURES FEATURES

Direct Correspondence between Display Data RAM and LCD Pixel Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM - 25,344 bits (1.5 times over than display size) Display Data RAM - 25,344 bits (1.5 times over than display size) 236 LCD Drivers - 128-common and 132-segment 236 LCD Drivers - 128-common and 132-segment Direct Microprocessor Interface for both of 68 and 80 type MPU Direct Microprocessor Interface for both of 68 and 80 type MPU Serial Interface Serial Interface Partial Display Function Partial Display Function ((2 blocks of active display area and automatic 2 blocks of active display area and automatic duty cycle ratio selection)duty cycle ratio selection) Easy Vertical Scroll by the variable start line address and over size display data RAM Easy Vertical Scroll by the variable start line address and over size display data RAM Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12 bias Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12 bias Common Driver Order Assignment by mask option Common Driver Order Assignment by mask option

Version Version CC00 to C to C127127(Pin name)(Pin name) NJU6679ANJU6679A ComCom00 to Com to Com127127 NJU6679BNJU6679B ComCom127127 to Com to Com00

Useful Instruction Set Useful Instruction Set Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set, Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set, Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read, Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read, All On/Off, Voltage Booster Circuits Multiple Select(Maximum 6-time), n-Line Inverse, All On/Off, Voltage Booster Circuits Multiple Select(Maximum 6-time), n-Line Inverse, Read Modify Write, Power Saving, ADC Select, etc. Read Modify Write, Power Saving, ADC Select, etc.

Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(6-time Maximum), Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(6-time Maximum), Regulator, Voltage Follower x 4 Regulator, Voltage Follower x 4

Precision Electrical Variable Resistance Precision Electrical Variable Resistance Low Power Consumption Low Power Consumption Operating Voltage Operating Voltage --- 2.4V to 3.6V --- 2.4V to 3.6V LCD Driving Voltage LCD Driving Voltage --- 6.0V to 18V --- 6.0V to 18V Package Outline Package Outline --- COF / TCP / Bumped Chip --- COF / TCP / Bumped Chip C-MOS Technology C-MOS Technology

PACKAGE OUTLINE PACKAGE OUTLINE

NJU6679CLNJU6679CL

JUL.10.2000JUL.10.2000 Ver. 2.1 Ver. 2.1

PAD LOCATION PAD LOCATION

NJU6679NJU6679

DUMMY19 DUMMY18 DUMMY17 DUMMY16 DUMMY15 DUMMY14 DUMMY13 DUMMY12 V

VR V

C5 V

OUT

RD WR A0 CS OSC

OSC

RES SEL68 P/S V

DUMMY11 DUMMY10 DUMMY9 DUMMY8 DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1

DUMMY0

C C

C S

46 47

63 0

131

127

111

110

109

Chip CenterChip Center : X=0um,Y=0um: X=0um,Y=0um Chip SizeChip Size : X=10.31mm,Y=3.13mm: X=10.31mm,Y=3.13mm Chip ThicknessChip Thickness : 675um : 675um ++ 30um 30um Bump SizeBump Size : 45um x 83um: 45um x 83um Pad pitchPad pitch : 60um(Min): 60um(Min) Bump HeightBump Height : 15um TYP.: 15um TYP. Bump MaterialBump Material : Au: Au

NJU6679NJU6679

TERMINAL DESCRIPTION TERMINAL DESCRIPTION Chip Size 10.31 x 3.13mm (Chip Center X=0um,Y=0um)Chip Size 10.31 x 3.13mm (Chip Center X=0um,Y=0um)

PAD No. Terminal X= um Y= um PAD No. Terminal X= um Y= um

1 DUMMY0 -4884 -1405 51 V2 2792 -1405 2 DUMMY1 -4132 -1405 52 V1 2862 -1405 3 DUMMY2 -4062 -1405 53 VDD 2932 -1405 4 DUMMY3 -3992 -1405 54 DUMMY12 3315 -1405 5 DUMMY4 -3922 -1405 55 DUMMY13 3385 -1405 6 DUMMY5 -3852 -1405 56 DUMMY14 3455 -1405 7 DUMMY6 -3782 -1405 57 DUMMY15 3525 -1405 8 DUMMY7 -3712 -1405 58 DUMMY16 3595 -1405 9 DUMMY8 -3642 -1405 59 DUMMY17 3665 -1405

10 DUMMY9 -3572 -1405 60 DUMMY18 3735 -1405

11 DUMMY10 -3502 -1405 61 DUMMY19 4884 -1405 12 DUMMY11 -3432 -1405 62 C0 4995 -1416 13 VDD -3270 -1405 63 C1 4995 -1356 14 P/S -3104 -1405 64 C2 4995 -1296 15 SEL86 -2884 -1405 65 C3 4995 -1236 16 RES -2648 -1405 66 C4 4995 -1176 17 VSS -2490 -1405 67 C5 4995 -1116 18 T2 -2333 -1405 68 C6 4995 -1056 19 T1 -2098 -1405 69 C7 4995 -996 20 OSC1 -1877 -1405 70 C8 4995 -936

21 OSC2 -1641 -1405 71 C9 4995 -876 22 CS -1420 -1405 72 C10 4995 -816 23 A0 -1184 -1405 73 C11 4995 -756 24 WR -954 -1405 74 C12 4995 -696 25 RD -717 -1405 75 C13 4995 -636 26 D0 -481 -1405 76 C14 4995 -576 27 D1 -260 -1405 77 C15 4995 -516 28 D2 -40 -1405 78 C16 4995 -456 29 D3 180 -1405 79 C17 4995 -396 30 D4 400 -1405 80 C18 4995 -336

31 D5 621 -1405 81 C19 4995 -276 32 D6(SCL) 841 -1405 82 C20 4995 -216 33 D7(SI) 1061 -1405 83 C21 4995 -156 34 VSS 1222 -1405 84 C22 4995 -96 35 VOUT 1398 -1405 85 C23 4995 -36 36 C5 37 C5 38 C4 39 C4 40 C3 41 C3 42 C2 43 C2 44 C1 45 C1 46 VDD 2168 -1405 96 C34 4995 624 47 VR 2327 -1405 97 C35 4995 684 48 V5 2582 -1405 98 C36 4995 744 49 V4 2652 -1405 99 C37 4995 804 50 V3 2722 -1405 100 C38 4995 864

1468 -1405 86 C24 4995 24 1538 -1405 87 C25 4995 84 1608 -1405 88 C26 4995 144 1678 -1405 89 C27 4995 204 1748 -1405 90 C28 4995 264 1818 -1405 91 C29 4995 324 1888 -1405 92 C30 4995 384 1958 -1405 93 C31 4995 444 2028 -1405 94 C32 4995 504 2098 -1405 95 C33 4995 564

NJU6679NJU6679

PAD No. Terminal X= um Y= um PAD No. Terminal X= um Y= um

101 C39 4995 924 151 S25 2430 1405 102 C40 4995 984 152 S26 2370 1405 103 C 41 4995 1044 153 S27 2310 1405 104 C42 4995 1104 154 S28 2250 1405 105 C 106 C44 4995 1224 156 S30 2130 1405 107 C45 4995 1284 157 S31 2070 1405 108 C46 5010 1405 158 S32 2010 1405 109 C47 4950 1405 159 S33 1950 1405 110 C48 4890 1405 160 S34 1890 1405

111 C49 4830 1405 161 S35 1830 1405 112 C50 4770 1405 162 S36 1770 1405 113 C 51 4710 1405 163 S37 1710 1405 114 C52 4650 1405 164 S38 1650 1405 115 C 116 C54 4530 1405 166 S40 1530 1405 117 C55 4470 1405 167 S41 1470 1405 118 C56 4410 1405 168 S42 1410 1405 119 C57 4350 1405 169 S43 1350 1405 120 C58 4290 1405 170 S44 1290 1405

121 C59 4230 1405 171 S45 1230 1405 122 C60 4170 1405 172 S46 1170 1405 123 C 61 4110 1405 173 S47 1110 1405 124 C62 4050 1405 174 S48 1050 1405 125 C63 3990 1405 175 S49 990 1405 126 S0 3930 1405 176 S50 930 1405 127 S1 3870 1405 177 S51 870 1405 128 S2 3810 1405 178 S52 810 1405 129 S3 3750 1405 179 S53 750 1405 130 S4 3690 1405 180 S54 690 1405

131 S5 3630 1405 181 S55 630 1405 132 S6 3570 1405 182 S56 570 1405 133 S7 3510 1405 183 S57 510 1405 134 S8 3450 1405 184 S58 450 1405 135 S9 3390 1405 185 S59 390 1405 136 S10 3330 1405 186 S60 330 1405 137 S11 3270 1405 187 S61 270 1405 138 S12 3210 1405 188 S62 210 1405 139 S13 3150 1405 189 S63 150 1405 140 S14 3090 1405 190 S64 90 1405

141 S15 3030 1405 191 S65 30 1405 142 S16 2970 1405 192 S66 -30 1405 143 S17 2910 1405 193 S67 -90 1405 144 S18 2850 1405 194 S68 -150 1405 145 S19 2790 1405 195 S69 -210 1405 146 S20 2730 1405 196 S70 -270 1405 147 S21 2670 1405 197 S71 -330 1405 148 S22 2610 1405 198 S72 -390 1405 149 S23 2550 1405 199 S73 -450 1405 150 S24 2490 1405 200 S74 -510 1405

4995 1164 155 S

4590 1405 165 S

2190 1405

1590 1405

NJU6679NJU6679

PAD No. Terminal X= um Y= um PAD No. Terminal X= um Y= um

201 S75 -570 1405 251 S125 -3570 1405

202 S76 -630 1405 252 S126 -3630 1405

203 S77 -690 1405 253 S127 -3690 1405

204 S78 -750 1405 254 S128 -3750 1405

205 S79 -810 1405 255 S129 -3810 1405

206 S80 -870 1405 256 S130 -3870 1405

207 S81 -930 1405 257 S131 -3930 1405

208 S82 -990 1405 258 C127 -3990 1405

209 S83 -1050 1405 259 C126 -4050 1405

210 S84 -1110 1405 260 C125 -4110 1405

211 S85 -1170 1405 261 C124 -4170 1405 212 S86 -1230 1405 262 C123 -4230 1405 213 S87 -1290 1405 263 C122 -4290 1405 214 S88 -1350 1405 264 C121 -4350 1405 215 S89 -1410 1405 265 C120 -4410 1405 216 S90 -1470 1405 266 C119 -4470 1405 217 S91 -1530 1405 267 C118 -4530 1405 218 S92 -1590 1405 268 C117 -4590 1405 219 S93 -1650 1405 269 C116 -4650 1405 220 S94 -1710 1405 270 C115 -4710 1405 221 S95 -1770 1405 271 C114 -4770 1405 222 S96 -1830 1405 272 C113 -4830 1405 223 S97 -1890 1405 273 C112 -4890 1405 224 S98 -1950 1405 274 C111 -4950 1405 225 S99 -2010 1405 275 C110 -5010 1405 226 S100 -2070 1405 276 C109 -4995 1284 227 S101 -2130 1405 277 C108 -4995 1224 228 S102 -2190 1405 278 C107 -4995 1164 229 S103 -2250 1405 279 C106 -4995 1104 230 S104 -2310 1405 280 C105 -4995 1044 231 S105 -2370 1405 281 C104 -4995 984 232 S106 -2430 1405 282 C103 -4995 924 233 S107 -2490 1405 283 C102 -4995 864 234 S108 -2550 1405 284 C101 -4995 804 235 S109 -2610 1405 285 C100 -4995 744 236 S110 -2670 1405 286 C99 -4995 684 237 S111 -2730 1405 287 C98 -4995 624 238 S112 -2790 1405 288 C97 -4995 564 239 S113 -2850 1405 289 C96 -4995 504 240 S114 -2910 1405 290 C95 -4995 444 241 S115 -2970 1405 291 C94 -4995 384 242 S116 -3030 1405 292 C93 -4995 324 243 S117 -3090 1405 293 C92 -4995 264 244 S118 -3150 1405 294 C91 -4995 204 245 S119 -3210 1405 295 C90 -4995 144 246 S120 -3270 1405 296 C89 -4995 84 247 S121 -3330 1405 297 C88 -4995 24 248 S122 -3390 1405 298 C87 -4995 -36 249 S123 -3450 1405 299 C86 -4995 -96 250 S124 -3510 1405 300 C85 -4995 -156

PAD No. Terminal X= um Y= um

301 C84 -4995 -216

302 C83 -4995 -276 303 C82 -4995 -336 304 C81 -4995 -396 305 C80 -4995 -456 306 C 307 C78 -4995 -576 308 C77 -4995 -636 309 C76 -4995 -696 310 C

311 C74 -4995 -816

312 C73 -4995 -876 313 C72 -4995 -936 314 C 315 C70 -4995 -1056 316 C69 -4995 -1116 317 C68 -4995 -1176 318 C67 -4995 -1236 319 C66 -4995 -1296 320 C65 -4995 -1356

321 C64 -4995 -1416

-4995 -516

-4995 -756

-4995 -996

NJU6679NJU6679

BLOCK DIAGRAM BLOCK DIAGRAM

NJU6679NJU6679

V1to V

T1,T

C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5-

D r i v e r

Voltage

R e g i s t e r

Generator

C O M

S h i f t

S E G

D r i v e r

131

127

C O M

D r i v e r

S h i f t

R e g i s t e r

COMSEG

Timing

Generator

D i s p l a y D a t a L a t c h

Display Data RAM

192 x 132

Output Assignment

Row Address Decoder

Line Address Decoder

Start Line Register

L i n e C o u n t e r

R egi s t er

I / O B u f f e r

P a g e A d dre s s

Instruct ionDecoder

I n t e r n a l B u s

R e s e t

RES

Culumn Address Decoder

Culumn Address Counter

Culumn Address Register

M u l t i p l e x e r

S t a t u s

M P U I n t e r f a c e

B F

B u s H o l d e r

SEL68

P/S

Display

Timing

Generator

OSC.

D0to D7(SI,S CL)

OSC1 OSC2

TERMINAL DESCRIPTION TERMINAL DESCRIPTION

No. Symbol I/O F u n c t i o n 1,40 VDD

Power

VDD=+3V 5,22 VSS GND VSS=0V 39

38 37 36 35

V1 V2 V3 V V5

Power

LCD Driving Voltage Supplying Terminal. When the internal voltage booster is

not used, supply each level of LCD driving voltage from outside with following

relation.

VDD>V1>V2>V3>V4>V5

When the internal power supply is on, the internal circuits generate and supply

following LCD bias voltage from V1 to V4 terminals.

Bias V1 V2 V3 V4 1/4Bias V5+3/4VLCD V5+2/4VLCD V5+2/4VLCD V5+1/4VLCD 1/5Bias V5+4/5VLCD V5+3/5VLCD V5+2/5VLCD V5+1/5VLCD 1/6Bias V5+5/6VLCD V5+4/6VLCD V5+2/6VLCD V5+1/6VLCD 1/7Bias V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD 1/8Bias V5+7/8VLCD V5+6/8VLCD V5+2/8VLCD V5+1/8VLCD 1/9Bias V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD

1/10Bias V5+9/10VLCD V5+8/10VLCD V5+2/10VLCD V5+1/10VLCD 1/11Bias V5+10/11VLCD V5+9/11VLCD V5+2/11VLCD V5+1/11VLCD 1/12Bias V5+11/12VLCD V5+10/12V

LCD

V5+2/12VLCD V5+1/12VLCD

NJU6679NJU6679

(VLCD=VDD-V5)

33,32, 31,30, 29,28, 27,26, 25,24

C1+,C1 C2+,C2 C3+,C3 C4+,C4 C5+,C5

O Step up capacitor connecting terminals.

Voltage booster circuit (Maximum 6-time)

23 VOUT O Step up voltage output terminal. Connect the step up capacitor between this

terminal and VSS.

34 VR I Voltage adjust terminal. V5 level is adjusted by external bleeder resistance

connecting between VDD and V5 terminal.

7 6

14 to 21 D0 to

T T2

(SI) (SCL)

I LCD bias voltage control terminals. ( *:Don't Care)

T 1 T 2

L * Available Available Available H L Not Avail. Available Available H H Not Avail. Not Avail. Available

Voltage

booster Cir.

Voltage Adj. V/F Cir.

I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.

P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input terminal. Data from SI is loaded at the rising edge of SCL and latched as the parallel data at 8th rising edge of SCL.

11 A0 I Connect to the Address bus of MPU. The data on the D 0 to D7 is

distinguished between Display data and Instruction by status of A0.

A0 H L

Distin. Display Data Instruction

4 RES I Reset terminal. When the RES terminal goes to "L", the initialization is

performed. Reset operation is executing during "L" state of RES.

10 CS I Chip select terminal. Data Input/Output are available during CS ="L".

No Symbol I/O F u n c t i o n

13 RD(E) I <In case of 80 Type MPU>

RD signal of 80 type MPU input terminal. Active "L" During this signal is "L" , D0 to D7 terminals are output. <In case of 68 Type MPU> Enable signal of 68 type MPU input terminal. Active "H"

12 WR(R-

I <In case of 80 Type MPU>

Connect to the 80 type MPU WR signal. Actie "L". The data on the data bus input syncronizing the rise edge of this signal. <In case of 68 Type MPU> The read/write control signal of 68 type MPU input terminal.

R/W H L

State Read Write

3 SEL68 I MPU interface type selection terminal.

SEL68 H L

State 68 Type 80 Type

NJU6679NJU6679

2 P/S I serial or parallel interface selection terminal.

P/S "H" CS A D0 to D7 RD,WR -

"L" CS A0 SI(D7) Write Only SCL(D6)

Chip Select Data/Command

Data

RAM data and status read operation do not work in mode of the serial interface.

In case of the serial interface (P/S="L"),RD and WR must be fixed "H" or "L", and D0 to D5 are high impedance.

8 9

41 to 104 C0 to

OSC1 OSC2

C63

I System clock input terminal for Maker testing.(This terminal should be Open)

For external clock operation, the clock shoud be input to OSC1 terminal.

O LCD driving signal output terminals.

Segmet output terminals:S 0 to S131 Common output terminals:C 0 to C127

Segment output terminal The following output voltages are selected by the combination of FR and data in the RAM.(non of the n-line inverse functions)

Output Voltage

Normal Reverse

105 to 236

toS131

RAM Data

H VDD V2

L V5 V3

H V

L V3 V5

Read/Write serial Clock

237 to 300

C64 to C127

Common output terminal The following output voltages are selected by the combination of FR and status of common.

Scan data FR Output Voltage

H V5

L VDD

H V1

L V4

NJU6679NJU6679

Functional Description Functional Description

(1) Description for each blocks(1) Description for each blocks

(1-1) Busy Flag (BF)(1-1) Busy Flag (BF) While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the statusWhile the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status read are inhibited .read are inhibited . The busy flag goes to “1” from DThe busy flag goes to “1” from D77 terminal when status read instruction is executed. terminal when status read instruction is executed. When enough cycle time over than tWhen enough cycle time over than tCYCCYC indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no need to check the busy flag for reduction of the MPU loads.need to check the busy flag for reduction of the MPU loads.

(1-2)Display Start Line Register(1-2)Display Start Line Register The Display start Line Register is a pointer register which indicates the address in the Display Data RAM The Display start Line Register is a pointer register which indicates the address in the Display Data RAM corresponding with COM corresponding with COM00(normally it display the top line in the LCD Panel). This register also operates for(normally it display the top line in the LCD Panel). This register also operates for vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the display start address of the Display Data RAM represented in 8-bit to this register. display start address of the Display Data RAM represented in 8-bit to this register.

(1-3) Line Counter(1-3) Line Counter The Line Counter generates the line address of display data RAM by the count up operation synchronizing theThe Line Counter generates the line address of display data RAM by the count up operation synchronizing the common cycle after the reset operation at the status change of internal FR signal.common cycle after the reset operation at the status change of internal FR signal.

(1-4) Column Address Counter(1-4) Column Address Counter The column address counter is 8-bit pre-settable counter addressing the column address of display data RAMThe column address counter is 8-bit pre-settable counter addressing the column address of display data RAM as shown in Fig. 1. It is incremented (+1) up to (84)as shown in Fig. 1. It is incremented (+1) up to (84)HH by the Display Data Read/Write instruction execution. by the Display Data Read/Write instruction execution. It stops the count up operation at (84)It stops the count up operation at (84)HH, and it does not count up non existing address area over than (84), and it does not count up non existing address area over than (84)HH by by the count lock function. This count lock is released by new column address set.the count lock function. This count lock is released by new column address set. The column address counter is independent of the Page Register.The column address counter is independent of the Page Register. By the Address Inverse Instruction, the column address decoder inverse the column address of Display DataBy the Address Inverse Instruction, the column address decoder inverse the column address of Display Data RAM corresponding to the Segment Driver.RAM corresponding to the Segment Driver.

(1-5) Page Register(1-5) Page Register The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accessesThe page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses the data with the page change, the page address set instruction is required.the data with the page change, the page address set instruction is required.

(1-6) Display Data RAM(1-6) Display Data RAM Display Data RAM is the bit map RAM consisting of 25,344 bits to memorize the display data corresponding toDisplay Data RAM is the bit map RAM consisting of 25,344 bits to memorize the display data corresponding to each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCDeach pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD panel and controls the display by following bit data.panel and controls the display by following bit data.

When Normal Display : On="1" , Off="0"When Normal Display : On="1" , Off="0"

When Inverse Display : On="0" , Off="1"When Inverse Display : On="0" , Off="1" The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these dataThe Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data are set into the Display Data Latch.are set into the Display Data Latch. The access operation from MPU to the display data RAM and the data output from the display data RAM areThe access operation from MPU to the display data RAM and the data output from the display data RAM are so controlled to operate independently that the data rewriting does not influence with any malfunctions to theso controlled to operate independently that the data rewriting does not influence with any malfunctions to the display.The relation between column address and segment output can inverse by the Address Inverse Instruc-display.The relation between column address and segment output can inverse by the Address Inverse Instruction ADC as shown in Fig.1.tion ADC as shown in Fig.1.

(1-7) Common Driver Assignment(1-7) Common Driver Assignment The scanning order can be assigned by mask option as shown on Table 1.The scanning order can be assigned by mask option as shown on Table 1.

Table 1Table 1

COM Outputs Terminals

PAD No.

Pin name

Ver.A COM0 COM63 COM127 COM64 Ver.B COM127 COM64 COM0 COM63

62 125 258 321

C 0 C 63 C 127 C 64

Page Address DATA Display Pattern

D1 01

D2 02

D4,D3,D2,D1,D0

(0,0,0,0,0)

D3 03 D4 04 D5 05 D6 06 D7 07 D0

D1 09

D2 0A

D4,D3,D2,D1,D0

(0,0,0,0,1)

D3 0B D4 0C D5 0D D6 0E D7 0F Cn Out D0

D1 11 C1

D4,D3,D2,D1,D0

(0,0,0,1,0)

D2 12 C2 D3 13 C3 D4 14 C4 D5 15 C5 D6 16 C6 D7 17 C7 D0

D1 19 C9

: : : :

D6 86 C118 D7 87 C119 D0

D1 89 C121

D2 8A C122

D4,D3,D2,D1,D0

(1,0,0,0,1)

D3 8B C123 D4 8C C124

Pege 17

D5 8D C125 D6 8E C126 D7 8F C127 D0

D1 91

D2 92

D4,D3,D2,D1,D0

(1,0,0,1,0)

D3 93 D4 94

Pege 18

D5 95 D6 96 D7 97 D0

D1 99

: : : :

D6 B6 D7 B7 D0

D1 B9

D2 BA

D4,D3,D2,D1,D0

(1,0,1,1,1)

D3 BB D4 BC

Pege 23

D5 BD D6 BE D7 BF

| | | | | | | | | | | | | | | | | | | |

Column

Addre-

D 0="0"

A D C

D 0="1"

Segment Output 0 1 2 3 4 5 6 7 8 9

00 01 02 03 04 05 06 07 08 09 83 82 81 80

7F 7E 7D 7C 7B 7A

Fig.1 Correspondence with Display Data RAM AddressFig.1 Correspondence with Display Data RAM Address

Pege 0

Pege 1

Pege 2

: : : :

7C 7D

7A 7B 09 08 07 06 05 04 03 02 01 00

122 123 124 125 126 127 128 129 130 131

7E 7F 80 81 82 83

NJU6679NJU6679

For example the

Line

Address

Display start line is 10H

10 C0

18 C8

: : : :

88 C120

: : : :

NJU6679NJU6679

(1-8) Reset Circuit(1-8) Reset Circuit Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.

Initialization Initialization

11 Display OffDisplay Off 22 Normal Display (Non-inverse display)Normal Display (Non-inverse display) 33 ADC Select : Normal (ADC Instruction DADC Select : Normal (ADC Instruction D00 =”0”) =”0”) 44 Read Modify Write Mode OffRead Modify Write Mode Off 55 Internal Power supply (Voltage Booster) circuits OffInternal Power supply (Voltage Booster) circuits Off 66 Static Drive OffStatic Drive Off 77 Driver Output OffDriver Output Off 88 Clear the serial interface registerClear the serial interface register

99 Set the address(00)Set the address(00)HH to the Column Address Counter to the Column Address Counter 10 10 Set the 1st Line in the Display Start Line Register.page (00)Set the 1st Line in the Display Start Line Register.page (00)H H to the Page Address Registerto the Page Address Register 11 11 Set the page “0” to the Page Address RegisterSet the page “0” to the Page Address Register 12 12 Set the EVR register to (FF)Set the EVR register to (FF)HH 13 13 Set the All display(1/128 duty)Set the All display(1/128 duty) 14 14 Set the Bias select(1/12 Bias)Set the Bias select(1/12 Bias) 15 15 Set the 6-Time Voltage BoosterSet the 6-Time Voltage Booster 16 16 Set the n line turn over register (0)Set the n line turn over register (0)HH

The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean timeThe RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L"with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L" level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operationlevel input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation goes to normal.goes to normal. When the internal LCD power supply is not used, the external LCD power supply into the NJU6679 must beWhen the internal LCD power supply is not used, the external LCD power supply into the NJU6679 must be turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, theturned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the oscillation circuit and the output terminal conditions (Doscillation circuit and the output terminal conditions (D00 to D to D77) are not influenced. The initialization must be) are not influenced. The initialization must be performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The resetperformed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset Instruction performs the initialization procedures from No.9 to No.16 as shown in above.Instruction performs the initialization procedures from No.9 to No.16 as shown in above.

Note) The noise into the RES terminal should be eliminated to avoid the error on the application with theNote) The noise into the RES terminal should be eliminated to avoid the error on the application with the careful design.careful design.

(1-9) LCD Driving(1-9) LCD Driving (a) LCD Driving Circuits(a) LCD Driving Circuits

LCD driving circuits are consisted of 260 multiplexers which operate as 132 Segment drivers and 128 Com-LCD driving circuits are consisted of 260 multiplexers which operate as 132 Segment drivers and 128 Common drivers. 128 Common drivers with the shift register scan the common display signal. The combination ofmon drivers. 128 Common drivers with the shift register scan the common display signal. The combination of the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wavethe Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave form is shown in the Fig. 7.form is shown in the Fig. 7.

(b) Display Data Latch Circuits(b) Display Data Latch Circuits Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a commonDisplay Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inversecycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the DisplayON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display Data RAM is not changed.Data RAM is not changed.

(c) Line Counter and Latch signal of Latch Circuits(c) Line Counter and Latch signal of Latch Circuits The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clockThe clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock (CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display(CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD drivingdata are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access bycircuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the MPU.the MPU.

(d) Display Timing Generator(d) Display Timing Generator Display Timing Generator generates the timing signal for the display system by combination of the masterDisplay Timing Generator generates the timing signal for the display system by combination of the master clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generateclock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.

NJU6679NJU6679

(e)Common Timing Generation(e)Common Timing Generation The common timing is generated by display clock. The common timing is generated by display clock.

-Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0) -Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0)

127128 1 2 3 4 5 6 7 8

C L

C 0

125126 127 128 1 2 3 4 5

AM DATA

Fig.2 Fig.2

-Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6) -Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6)

127128 1 2 3 4 5 6 7 8

C 0

125126 127 128 1 2 3 4 5

R AMDATA

Fig.3 Fig.3

NJU6679NJU6679

(f) Oscillation Circuit(f) Oscillation Circuit The Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generatesThe Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generates clocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency isclocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency is divided as shown in below for display clock CL.divided as shown in below for display clock CL.

-The relation between duty and divide -The relation between duty and divide

Duty

Divide 1/64 1/32 1/21 1/16 1/12 1/10 1/9 1/8 1/7 1/6 1/5 1/4

(g) Power Supply Circuit(g) Power Supply Circuit Internal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power SupplyInternal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power Supply Circuit consists of Voltage Booster (6-Time maximum) Circuits, Regulator Circuits, and Voltage Followers.Circuit consists of Voltage Booster (6-Time maximum) Circuits, Regulator Circuits, and Voltage Followers. The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large sizeThe internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size LCD panel application. If the contrast is not good in the large size LCD panel application, please supply theLCD panel application. If the contrast is not good in the large size LCD panel application, please supply the external.external. The suitable values of the capacitors connecting to the VThe suitable values of the capacitors connecting to the V11 to V to V55 terminals and the voltage booster circuit, and terminals and the voltage booster circuit, and the feedback resistors for Vthe feedback resistors for V55 operational amplifier depend on the LCD panel. And the power consumption with operational amplifier depend on the LCD panel. And the power consumption with the LCD panel is depending on the display pattern. Please evaluate with actual LCD module.the LCD panel is depending on the display pattern. Please evaluate with actual LCD module. The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction.The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulatorWhen the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of Vcircuits, voltage follower circuits are turned off. In this time, the bias voltage of V11, V, V22, V, V33, V, V44, and V, and V55 for the for the LCD should be supplied from outside, terminals C1LCD should be supplied from outside, terminals C1++, C1, C1--, C2, C2++, C2, C2--,C3,C3++, C3, C3--, C4, C4++, C4, C4--, C5, C5++, C5, C5-- and VR should and VR should be open. The status of internal power supply is selected by Tbe open. The status of internal power supply is selected by T11 and T and T22 terminal. Furthermore the external terminal. Furthermore the external power supply operates with some of internal power supply function.power supply operates with some of internal power supply function.

1/8 1/16 1/24 1/32 1/40 1/48 1/56 1/64 1/72 1/80 1/88 1/96

1/104 1/112 1/120 1/128

T1 T2

L L/H ON ON ON H L OFF ON ON VOUT Open H H OFF OFF ON V5,VOUT Open Open

When (TWhen (T11, T, T22)=(H, L), C1)=(H, L), C1++, C1, C1--, C2, C2++, C2, C2--,C3,C3++, C3, C3--, C4, C4++, C4, C4--, C5, C5++, C5, C5-- terminals for voltage booster circuits are terminals for voltage booster circuits are open because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the Vopen because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUTOUT terminal terminal should be supplied from outside.should be supplied from outside. When (TWhen (T11, T, T22)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster circuits and Voltage adjust circuits do not operate.circuits and Voltage adjust circuits do not operate.

Voltage Booster

Voltage Adj. Buffer(V/F) Ext.Pow Supply

C1+,C1- to

C5+,C5-

VR Term.

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