JRC NJU6678CL Datasheet

NJU6678NJU6678

PRELIMINARYPRELIMINARY

104-common x 132-segment104-common x 132-segment

BIT MAP LCD DRIVER BIT MAP LCD DRIVER

GENERAL DESCRIPTION GENERAL DESCRIPTION

The NJU6678 is a bit map LCD driver to display graphics or charac-The NJU6678 is a bit map LCD driver to display graphics or characters. It contains 21,120 bits display data RAM, microprocessor inter-ters. It contains 21,120 bits display data RAM, microprocessor interface circuits, instruction decoder, 132-segment and 104-common driv-face circuits, instruction decoder, 132-segment and 104-common drivers.ers. The bit image display data is transferred to the display data RAM byThe bit image display data is transferred to the display data RAM by serial or 8-bit parallel interface.serial or 8-bit parallel interface. The NJU6678 displays 104 x 132 dots graphics or 8-character 6-lineThe NJU6678 displays 104 x 132 dots graphics or 8-character 6-line by 16 x 16 dots character.by 16 x 16 dots character. It oscillates by built-in OSC circuit without any external components.It oscillates by built-in OSC circuit without any external components. Furthermore, the NJU6678 features Partial Display Function whichFurthermore, the NJU6678 features Partial Display Function which creates up to 2 blocks of active display area and optimizes duty cyclecreates up to 2 blocks of active display area and optimizes duty cycle ratio. This function sets optimum boosted voltage by the combinationratio. This function sets optimum boosted voltage by the combination with both of programmable 5-time voltage booster circuit and 201-with both of programmable 5-time voltage booster circuit and 201step electrical variable resistor. As result, it reduces the operating cur-step electrical variable resistor. As result, it reduces the operating current.rent. The operating voltage from 2.5V to 3.3V and low operating current areThe operating voltage from 2.5V to 3.3V and low operating current are useful for small size battery operating items.useful for small size battery operating items.

FEATURES FEATURES

Direct Correspondence between Display Data RAM and LCD Pixel Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM - 21,120 bits (1.5 times over than display size) Display Data RAM - 21,120 bits (1.5 times over than display size) 236 LCD Drivers - 104-common and 132-segment 236 LCD Drivers - 104-common and 132-segment Direct Microprocessor Interface for both of 68 and 80 type MPU Direct Microprocessor Interface for both of 68 and 80 type MPU Serial Interface Serial Interface Partial Display Function Partial Display Function ((2 blocks of active display area and automatic 2 blocks of active display area and automatic duty cycle ratio selection)duty cycle ratio selection) Easy Vertical Scroll by the variable start line address and over size display data RAM Easy Vertical Scroll by the variable start line address and over size display data RAM Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias Common Driver Order Assignment by mask option Common Driver Order Assignment by mask option

Version Version CC00 to C to C103103(Pin name)(Pin name) NJU6678ANJU6678A ComCom00 to Com to Com103103 NJU6678BNJU6678B ComCom103103 to Com to Com00

Useful Instruction Set Useful Instruction Set Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set, Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set, Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read, Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read, All On/Off, Voltage Booster Circuits Multiple Select(Maximum 5-time), n-Line Inverse, All On/Off, Voltage Booster Circuits Multiple Select(Maximum 5-time), n-Line Inverse, Read Modify Write, Power Saving, ADC Select, etc. Read Modify Write, Power Saving, ADC Select, etc.

Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum), Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum), Regulator, Voltage Follower x 4 Regulator, Voltage Follower x 4

Precision Electrical Variable Resistance Precision Electrical Variable Resistance Low Power Consumption Low Power Consumption Operating Voltage Operating Voltage --- 2.5V to 3.3V --- 2.5V to 3.3V LCD Driving Voltage LCD Driving Voltage --- 6.0V to 17V --- 6.0V to 17V Package Outline Package Outline --- COF / TCP / Bumped Chip --- COF / TCP / Bumped Chip C-MOS Technology C-MOS Technology

PACKAGE OUTLINE PACKAGE OUTLINE

NJU6678CLNJU6678CL

Mar.2000Mar.2000 Ver.2.1 Ver.2.1

PAD LOCATION PAD LOCATION

S10 3

S10 2

NJU6678NJU6678

S28

S29

104

105

130

131

103

102

5 1

5 0

D UM MY3D UM MY5D UM MY6D UM MY

D UM MY0D UM MY1D UM MY2D UM MY

CEL68

P/S

D D

T1T

RES

OSC2

OSC1

D0D

W R

D5D4D3

D7 (SI)

D6 (SCL)

S S

OU T

-C4-C4+

C2-C2+C1

V5VR

V1V

V2V

D D

Chip CenterChip Center : X=0um,Y=0um: X=0um,Y=0um Chip SizeChip Size : X=5.36mm,Y=5.31mm: X=5.36mm,Y=5.31mm Chip ThicknessChip Thickness : 675um : 675um ++ 30um 30um Bump SizeBump Size : 45um x 83um: 45um x 83um Pad pitchPad pitch : 60um(Min): 60um(Min) Bump HeightBump Height : 15um TYP.: 15um TYP. Bump MaterialBump Material : Au: Au

NJU6678NJU6678

TERMINAL DESCRIPTION TERMINAL DESCRIPTION Chip Size 5.36 x 5.31mm (Chip Center X=0um,Y=0um)Chip Size 5.36 x 5.31mm (Chip Center X=0um,Y=0um)

PAD No. Terminal X= um Y= um PAD No. Terminal X= um Y= um

1 DUMMY0 -2250 -2497 51 C4 2523 -2130 2 DUMMY1 -2190 -2497 52 C5 2523 -2070 3 DUMMY2 -2130 -2497 53 C6 2523 -2010 4 DUMMY3 -2070 -2497 54 C7 2523 -1950 5 DUMMY4 -2010 -2497 55 C8 2523 -1890 6 DUMMY5 -1950 -2497 56 C9 2523 -1830 7 DUMMY6 -1890 -2497 57 C10 2523 -1770 8 DUMMY7 -1830 -2497 58 C11 2523 -1710 9 VDD -1747 -2497 59 C12 2523 -1650

10 P/S -1666 -2497 60 C13 2523 -1590

11 CEL68 -1596 -2497 61 C14 2523 -1530 12 RES -1487 -2497 62 C15 2523 -1470 13 VSS -1417 -2497 63 C16 2523 -1410 14 T 2 -1347 -2497 64 C17 2523 -1350 15 T1 -1238 -2497 65 C18 2523 -1290 16 OSC 1 -1168 -2497 66 C19 2523 -1230 17 OSC2 -1049 -2497 67 C 20 2523 -1170 18 CS -979 -2497 68 C 21 2523 -1110 19 A0 -861 -2497 69 C22 2523 -1050 20 WR -791 -2497 70 C23 2523 -990 21 RD -667 -2497 71 C 24 2523 -930 22 D0 -510 -2497 72 C25 2523 -870 23 D1 -289 -2497 73 C26 2523 -810 24 D2 -69 -2497 74 C27 2523 -750 25 D3 152 -2497 75 C28 2523 -690 26 D4 372 -2497 76 C29 2523 -630 27 D5 592 -2497 77 C30 2523 -570 28 D6(SCL) 813 -2497 78 C31 2523 -510 29 D7(SI) 1033 -2497 79 C 32 2523 -450 30 VSS 1191 -2497 80 C33 2523 -390 31 V OUT 1261 -2497 81 C 34 2523 -330 32 C4 33 C4 34 C3 35 C3 36 C2 37 C2 38 C1 39 C1

40 VR 1891 -2497 90 C43 2523 210

41 V5 1961 -2497 91 C44 2523 270

42 V4 2031 -2497 92 C45 2523 330 43 V3 2101 -2497 93 C46 2523 390 44 V2 2171 -2497 94 C47 2523 450 45 V1 2241 -2497 95 C48 2523 510 46 VDD 2311 -2497 96 C49 2523 570 47 C0 2523 -2370 97 C50 2523 630 48 C1 2523 -2310 98 C51 2523 690 49 C2 2523 -2250 99 S 0 2523 750

50 C3 2523 -2190 100 S1 2523 810

1331 -2497 82 C35 2523 -270 1401 -2497 83 C36 2523 -210 1471 -2497 84 C37 2523 -150 1541 -2497 85 C38 2523 -90

1611 -2497 86 C39 2523 -30 1681 -2497 87 C40 2523 30 1751 -2497 88 C41 2523 90 1821 -2497 89 C42 2523 150

NJU6678NJU6678

PAD No. Terminal X= um Y= um PAD No. Terminal X= um Y= um

101 S 2 2523 870 151 S 52 810 2497 102 S 3 2523 930 152 S 53 750 2497 103 S 4 2523 990 153 S 54 690 2497 104 S 5 2523 1050 154 S 55 630 2497 105 S 6 2523 1110 155 S 56 570 2497 106 S 7 2523 1170 156 S 57 510 2497 107 S 108 S 9 2523 1290 158 S 59 390 2497 109 S 10 2523 1350 159 S 60 330 2497

110 S 11 2523 1410 160 S 61 270 2497 111 S 12 2523 1470 161 S 62 210 2497 112 S 13 2523 1530 162 S 63 150 2497 113 S 14 2523 1590 163 S 64 90 2497 114 S 15 2523 1650 164 S 65 30 2497 115 S 16 2523 1710 165 S 66 -30 2497 116 S 17 2523 1770 166 S 67 -90 2497 117 S 18 2523 1830 167 S 68 -150 2497 118 S 19 2523 1890 168 S 69 -210 2497

119 S 20 2523 1950 169 S 70 -270 2497 120 S 21 2523 2010 170 S 71 -330 2497 121 S 22 2523 2070 171 S 72 -390 2497 122 S 23 2523 2130 172 S 73 -450 2497 123 S 24 2523 2190 173 S 74 -510 2497 124 S 25 2523 2250 174 S 75 -570 2497 125 S 26 2523 2310 175 S 76 -630 2497 126 S 27 2523 2370 176 S 77 -690 2497 127 S 28 2250 2497 177 S 78 -750 2497 128 S 29 2190 2497 178 S 79 -810 2497 129 S 30 2130 2497 179 S 80 -870 2497 130 S 31 2070 2497 180 S 81 -930 2497 131 S 32 2010 2497 181 S 82 -990 2497 132 S 33 1950 2497 182 S 83 -1050 2497 133 S 34 1890 2497 183 S 84 -1110 2497 134 S 35 1830 2497 184 S 85 -1170 2497 135 S 36 1770 2497 185 S 86 -1230 2497 136 S 37 1710 2497 186 S 87 -1290 2497 137 S 38 1650 2497 187 S 88 -1350 2497 138 S 39 1590 2497 188 S 89 -1410 2497 139 S 40 1530 2497 189 S 90 -1470 2497 140 S 41 1470 2497 190 S 91 -1530 2497 141 S 42 1410 2497 191 S 92 -1590 2497 142 S 43 1350 2497 192 S 93 -1650 2497 143 S 44 1290 2497 193 S 94 -1710 2497 144 S 45 1230 2497 194 S 95 -1770 2497 145 S 46 1170 2497 195 S 96 -1830 2497 146 S 47 1110 2497 196 S 97 -1890 2497 147 S 48 1050 2497 197 S 98 -1950 2497 148 S 49 990 2497 198 S 99 -2010 2497 149 S 50 930 2497 199 S 100 -2070 2497 150 S 51 870 2497 200 S 101 -2130 2497

2523 1230 157 S

450 2497

NJU6678NJU6678

PAD No. Terminal X= um Y= um PAD No. Terminal X= um Y= um

201 S 102 -2190 2497 251 C 83 -2524 -510 202 S 103 -2250 2497 252 C 82 -2524 -570 203 S 104 -2524 2370 253 C 81 -2524 -630 204 S 105 -2524 2310 254 C 80 -2524 -690 205 S 106 -2524 2250 255 C 79 -2524 -750 206 S 107 -2524 2190 256 C 78 -2524 -810 207 S 108 -2524 2130 257 C 77 -2524 -870 208 S 109 -2524 2070 258 C 76 -2524 -930 209 S 110 -2524 2010 259 C 75 -2524 -990 210 S 111 -2524 1950 260 C 74 -2524 -1050

211 S 112 -2524 1890 261 C 73 -2524 -1110 212 S 113 -2524 1830 262 C 72 -2524 -1170 213 S 114 -2524 1770 263 C 71 -2524 -1230 214 S 115 -2524 1710 264 C 70 -2524 -1290 215 S 116 -2524 1650 265 C 69 -2524 -1350 216 S 117 -2524 1590 266 C 68 -2524 -1410 217 S 118 -2524 1530 267 C 67 -2524 -1470 218 S 119 -2524 1470 268 C 66 -2524 -1530 219 S 120 -2524 1410 269 C 65 -2524 -1590 220 S 121 -2524 1350 270 C 64 -2524 -1650 221 S 122 -2524 1290 271 C 63 -2524 -1710 222 S 123 -2524 1230 272 C 62 -2524 -1770 223 S 124 -2524 1170 273 C 61 -2524 -1830 224 S 125 -2524 1110 274 C 60 -2524 -1890 225 S 126 -2524 1050 275 C 59 -2524 -1950 226 S 127 -2524 990 276 C 58 -2524 -2010 227 S 128 -2524 930 277 C 57 -2524 -2070 228 S 129 -2524 870 278 C 56 -2524 -2130 229 S 130 -2524 810 279 C 55 -2524 -2190 230 S 131 -2524 750 280 C 54 -2524 -2250 231 C 103 -2524 690 281 C 53 -2524 -2310 232 C 102 -2524 630 282 C 52 -2524 -2370 233 C 101 -2524 570 234 C 100 -2524 510 235 C 99 -2524 450 236 C 98 -2524 390 237 C 97 -2524 330 238 C 96 -2524 270 239 C 95 -2524 210 240 C 94 -2524 150 241 C 93 -2524 90 242 C 92 -2524 30 243 C 91 -2524 -30 244 C 90 -2524 -90 245 C 89 -2524 -150 246 C 88 -2524 -210 247 C 87 -2524 -270 248 C 86 -2524 -330 249 C 85 -2524 -390 250 C 84 -2524 -450

BLOCK DIAGRAM BLOCK DIAGRAM

NJU6678NJU6678

V1toV

T1,T

C1+

C1-

C2+

C2-

C3+

C3-

C4+

C4-

D r i v e r

Voltage

Generator

RegisterPa ge Addres s

R e g i s t e r

Output Assignment

Row Addr ess Decoder

C O M

S h i f t

D i s p l a y Da t a La t c h

S E G

D r i v e r

Display Data RAM

160 x 132

131

103

C O M

D r i v e r

S h i f t

R e g i s t e r

COM SEG

Timing

Generator

Start Line Regis ter

Line Address Decoder

L i n e C o u n t e r

I / O B u f f e r

InstructionDecoder

I n t e r n a l B u s

R e s e t

RES

Culumn Address Decoder

Culumn Address Counter

Culumn Address Register

M u l t i p l e x e r

S t a t u s

M P U I n t e r f a c e

B F

B u s H o l d e r

CEL68

P/S

Display

Timing

Generator

OSC.

D0toD7(SI,SCL)

OSC1 OSC2

TERMINAL DESCRIPTION TERMINAL DESCRIPTION

No. Symbol I/O F u n c t i o n

1 to 8

9,46 VDD

DUMMY0

DUMMY7

Dummy Terminals. These terminals are insulated.

Power

VDD=+3V

13,30 VSS GND VSS=0V

45 44 43 42 41

V1 V2 V3 V4 V5

Power

LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not used, supply each level of LCD driving voltage from outside with following relation. VDD>V1>V2>V3>V4>V5 When the internal power supply is on, the internal circuits generate and supply following LCD bias voltage from V1 to V4 terminals.

Bias V 1 V 2 V 3 V 4

1/4Bias V 5+3/4VLCD V5+2/4VLCD V5+2/4VLCD V5 +1/4VLCD 1/5Bias 1/6Bias 1/7Bias 1/8Bias V 5+7/8VLCD V5+6/8VLCD V5+2/8VLCD V5 +1/8VLCD 1/9Bias V 5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5 +1/9VLCD

1/10Bias V 5+9/10V LCD V5 +8/10VLCD V5 +2/10VLCD V5 +1/10VLCD

1/11 Bias V5+10/11VLCD V5+9/11V LCD V5+2/11VLCD V5+1/11VLCD

V 5+4/5VLCD V5+3/5VLCD V5+2/5VLCD V5 +1/5VLCD V 5+5/6VLCD V5+4/6VLCD V5+2/6VLCD V5 +1/6VLCD V 5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5 +1/7VLCD

NJU6678NJU6678

(VLCD=VDD-V5)

38,39 36,37 34,35 32,33

C1+,C1 C2+,C2 C3+,C3 C4+,C4

O Step up capacitor connecting terminals.

Voltage booster circuit (Maximum 5-time)

31 VOUT O Step up voltage output terminal. Connect the step up capacitor between this

terminal and VSS .

40 VR I Voltage adjust terminal. V5 level is adjusted by external bleeder resistance

connecting between VDD and V5 terminal.

15 14

22 to 29 D0 to

T1 T2

(SI) (SCL)

I LCD bias voltage control terminals. ( *:Don't Care)

T 1 T 2

L * Available Available Available H L Not Avail. Available Available H H Not Avail. Not Avail. Available

Voltage

booster Cir.

Voltage Adj. V/F Cir.

I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.

P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input terminal. Data from SI is loaded at the rising edge of SCL and latched as the parallel data at 8th rising edge of SCL.

19 A0 I Connect to the Address bus of MPU. The data on the D 0 to D7 is

distinguished between Display data and Instruction by status of A0.

A0 H L

Distin. Display Data Instruction

12 RES I Reset terminal. When the RES terminal goes to "L", the initialization is

performed. Reset operation is executing during "L" state of RES.

18 CS I Chip select terminal. Data Input/Output are available during CS ="L".

No Symbol I/O F u n c t i o n

NJU6678NJU6678

21 RD(E) I <In case of 80 Type MPU>

RD signal of 80 type MPU input terminal. Active "L" During this signal is "L" , D0 to D7 terminals are output. <In case of 68 Type MPU> Enable signal of 68 type MPU input terminal. Active "H"

20 WR(RW) I <In case of 80 Type MPU>

Connect to the 80 type MPU WR signal. Actie "L". The data on the data bus input syncronizing the rise edge of this signal. <In case of 68 Type MPU> The read/write control signal of 68 type MPU input terminal.

R/W H L

State Read Write

11 CEL68 I MPU interface type selection terminal.

CEL68 H L

State 68 Type 80 Type

10 P/S I serial or parallel interface selection terminal.

P/S

"H" CS A D 0 to D 7 RD,WR -

"L" CS A0 SI(D7) Write Only SCL(D6)

RAM data and status read operation do not work in mode of the serial interface.

Chip Select Data/Command

Data

Read/Write serial Clock

16 17

98 C

OSC1 OSC2

0 to C51

99 to 230 S0 to S131 O

282 to 231 C52 to

C103

In case of the serial interface (P/S="L"),RD and WR must be fixed "H" or "L", and D0 to D5 are high impedance.

I System clock input terminal for Maker testing.(This terminal should be Open)

For external clock operation, the clock shoud be input to OSC1 terminal.

O LCD driving signal output terminals.

Segmet output terminals:S 0 to S131 Common output terminals:C 0 to C103

Segment output terminal The following output voltages are selected by the combination of FR and data in the RAM.(non of the n-line inverse functions)

RAM

Data

H V DD V 2

L V 5 V 3

H V 2 V DD

L V 3 V 5

Output Voltage

Normal Reverse

Common output terminal The following output voltages are selected by the combination of FR and status of common.

Scan data FR Output Voltage

H V 5

L VDD

H V 1

L V 4

NJU6678NJU6678

Functional Description Functional Description

(1) Description for each blocks(1) Description for each blocks

(1-1) Busy Flag (BF)(1-1) Busy Flag (BF) While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the statusWhile the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status read are inhibited .read are inhibited . The busy flag goes to “1” from DThe busy flag goes to “1” from D77 terminal when status read instruction is executed. terminal when status read instruction is executed. When enough cycle time over than tWhen enough cycle time over than tCYCCYC indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no indicated in “ BUS TIMING CHARACTERISTICS” is ensured, no need to check the busy flag for reduction of the MPU loads.need to check the busy flag for reduction of the MPU loads.

(1-2)Display Start Line Register(1-2)Display Start Line Register The Display start Line Register is a pointer register which indicates the address in the Display Data RAM The Display start Line Register is a pointer register which indicates the address in the Display Data RAM corresponding with COM corresponding with COM00(normally it display the top line in the LCD Panel). This register also operates for(normally it display the top line in the LCD Panel). This register also operates for vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the display start address of the Display Data RAM represented in 8-bit to this register. display start address of the Display Data RAM represented in 8-bit to this register.

(1-3) Line Counter(1-3) Line Counter The Line Counter generates the line address of display data RAM by the count up operation synchronizing theThe Line Counter generates the line address of display data RAM by the count up operation synchronizing the common cycle after the reset operation at the status change of internal FR signal.common cycle after the reset operation at the status change of internal FR signal.

(1-4) Column Address Counter(1-4) Column Address Counter The column address counter is 8-bit pre-settable counter addressing the column address of display data RAMThe column address counter is 8-bit pre-settable counter addressing the column address of display data RAM as shown in Fig. 1. It is incremented (+1) up to (84)as shown in Fig. 1. It is incremented (+1) up to (84)HH by the Display Data Read/Write instruction execution. by the Display Data Read/Write instruction execution. It stops the count up operation at (84)It stops the count up operation at (84)HH, and it does not count up non existing address area over than (84), and it does not count up non existing address area over than (84)HH by by the count lock function. This count lock is released by new column address set.the count lock function. This count lock is released by new column address set. The column address counter is independent of the Page Register.The column address counter is independent of the Page Register. By the Address Inverse Instruction, the column address decoder inverse the column address of Display DataBy the Address Inverse Instruction, the column address decoder inverse the column address of Display Data RAM corresponding to the Segment Driver.RAM corresponding to the Segment Driver.

(1-5) Page Register(1-5) Page Register The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accessesThe page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses the data with the page change, the page address set instruction is required.the data with the page change, the page address set instruction is required.

(1-6) Display Data RAM(1-6) Display Data RAM Display Data RAM is the bit map RAM consisting of 21,120 bits to memorize the display data corresponding toDisplay Data RAM is the bit map RAM consisting of 21,120 bits to memorize the display data corresponding to each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCDeach pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD panel and controls the display by following bit data.panel and controls the display by following bit data.

When Normal Display : On="1" , Off="0"When Normal Display : On="1" , Off="0"

When Inverse Display : On="0" , Off="1"When Inverse Display : On="0" , Off="1" The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these dataThe Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data are set into the Display Data Latch.are set into the Display Data Latch. The access operation from MPU to the display data RAM and the data output from the display data RAM areThe access operation from MPU to the display data RAM and the data output from the display data RAM are so controlled to operate independently that the data rewriting does not influence with any malfunctions to theso controlled to operate independently that the data rewriting does not influence with any malfunctions to the display.The relation between column address and segment output can inverse by the Address Inverse Instruc-display.The relation between column address and segment output can inverse by the Address Inverse Instruction ADC as shown in Fig.1.tion ADC as shown in Fig.1.

(1-7) Common Driver Assignment(1-7) Common Driver Assignment The scanning order can be assigned by mask option as shown on Table 1.The scanning order can be assigned by mask option as shown on Table 1.

Table 1Table 1

COM Outputs Terminals

PAD No.

Pin name

Ver.A COM0 COM51 COM103 COM52 Ver.B COM103 COM52 COM0 COM51

47 98 231 282 C0 C 51 C 103 C52

Page Address DATA Display Pattern

D0 D1 01

D4,D3,D2,D1,D0

(0,0,0,0,0)

D4,D3,D2,D1,D0

(0,0,0,0,1)

D4,D3,D2,D1,D0

(0,0,0,1,0)

: : : :

D4,D3,D2,D1,D0

(0,1,1,1,0)

D4,D3,D2,D1,D0

(0,1,1,1,1)

: : : :

D4,D3,D2,D1,D0

(1,0,0,1,1)

Column

Address

Segment Output

D2 02 D3 03 D4 04 D5 05 D6 06 D7 07 D0 D1 09 D2 0A D3 0B D4 0C D5 0D D6 0E D7 0F Cn Out D0 D1 11 C1 D2 12 C2 D3 13 C3 D4 14 C4 D5 15 C5 D6 16 C6 D7 17 C7 D0 D1 19 C9

: : :

: D6 6E C94 D7 6F C65 D0 D1 71 C97 D2 72 C98 D3 73 C99 D4 74 C100 D5 75 C101 D6 76 C102 D7 77 C103 D0 D1 79 D2 7A D3 7B D4 7C D5 7D D6 7E D7 7F D0 D1 81

: D6 96 D7 97 D0 D1 99 D2 9A D3 9B D4 9C D5 9D D6 9E D7 9F

| | | | | | | | | | | | | | | | | | | |

D 0="0" 00 01 02 03 04 05 06 07 08 09 7A 7B 7C 7D 7E 7F 80 81 82 83 D 0="1" 83 82 81 80 7F 7E 7D 7C 7B 7A 09 08 07 06 05 04 03 02 01 00

0 1 2 3 4 5 6 7 8 9

Pege 0

Pege 1

Pege 2

: : : :

Pege 14

Pege 15

: : : :

Pege 19

Fig.1 Correspondence with Display Data RAM AddressFig.1 Correspondence with Display Data RAM Address

122 123 124 125 126 127 128 129 130 131

NJU6678NJU6678

For example the

Line

Address

Display start line is 10 H

10 C0

18 C8

: : : :

70 C96

: : : :

NJU6678NJU6678

(1-8) Reset Circuit(1-8) Reset Circuit Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.

Initialization Initialization

11 Display OffDisplay Off 22 Normal Display (Non-inverse display)Normal Display (Non-inverse display) 33 ADC Select : Normal (ADC Instruction DADC Select : Normal (ADC Instruction D00 =”0”) =”0”) 44 Read Modify Write Mode OffRead Modify Write Mode Off 55 Internal Power supply (Voltage Booster) circuits OffInternal Power supply (Voltage Booster) circuits Off 66 Static Drive OffStatic Drive Off 77 Driver Output OffDriver Output Off 88 Clear the serial interface registerClear the serial interface register

99 Set the address(00)Set the address(00)HH to the Column Address Counter to the Column Address Counter 10 10 Set the 1st Line in the Display Start Line Register.page (00)Set the 1st Line in the Display Start Line Register.page (00)H H to the Page Address Registerto the Page Address Register 11 11 Set the page “0” to the Page Address RegisterSet the page “0” to the Page Address Register 12 12 Set the EVR register to (FF)Set the EVR register to (FF)HH 13 13 Set the All display(1/104 duty)Set the All display(1/104 duty) 14 14 Set the Bias select(1/11 Bias)Set the Bias select(1/11 Bias) 15 15 Set the 5-Time Voltage BoosterSet the 5-Time Voltage Booster 16 16 Set the n line turn over register (0)Set the n line turn over register (0)HH

The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean timeThe RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L"with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L" level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operationlevel input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation goes to normal.goes to normal. When the internal LCD power supply is not used, the external LCD power supply into the NJU6678 must beWhen the internal LCD power supply is not used, the external LCD power supply into the NJU6678 must be turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, theturned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the oscillation circuit and the output terminal conditions (Doscillation circuit and the output terminal conditions (D00 to D to D77) are not influenced. The initialization must be) are not influenced. The initialization must be performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The resetperformed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset Instruction performs the initialization procedures from No.8 to No.16 as shown in above.Instruction performs the initialization procedures from No.8 to No.16 as shown in above.

Note) The noise into the RES terminal should be eliminated to avoid the error on the application with theNote) The noise into the RES terminal should be eliminated to avoid the error on the application with the careful design.careful design.

(1-9) LCD Driving(1-9) LCD Driving (a) LCD Driving Circuits(a) LCD Driving Circuits

LCD driving circuits are consisted of 236 multiplexers which operate as 132 Segment drivers and 104 Com-LCD driving circuits are consisted of 236 multiplexers which operate as 132 Segment drivers and 104 Common drivers. 104 Common drivers with the shift register scan the common display signal. The combination ofmon drivers. 104 Common drivers with the shift register scan the common display signal. The combination of the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wavethe Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave form is shown in the Fig. 7.form is shown in the Fig. 7.

(b) Display Data Latch Circuits(b) Display Data Latch Circuits Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a commonDisplay Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inversecycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the DisplayON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display Data RAM is not changed.Data RAM is not changed.

(c) Line Counter and Latch signal of Latch Circuits(c) Line Counter and Latch signal of Latch Circuits The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clockThe clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock (CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display(CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD drivingdata are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access bycircuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the MPU.the MPU.

(d) Display Timing Generator(d) Display Timing Generator Display Timing Generator generates the timing signal for the display system by combination of the masterDisplay Timing Generator generates the timing signal for the display system by combination of the master clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generateclock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.

NJU6678NJU6678

(e)Common Timing Generation(e)Common Timing Generation The common timing is generated by display clock. The common timing is generated by display clock.

-Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0) -Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0)

103104 1 2 3 4 5 6 7 8

101102 103 104 1 2 3 4 5

AMDATA

Fig.2 Fig.2

-Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6) -Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6)

103104 1 2 3 4 5 6 7 8 101102 103 104 1 2 3 4 5

RAMDATA

Fig.3 Fig.3

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(f) Oscillation Circuit(f) Oscillation Circuit The Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generatesThe Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generates clocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency isclocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency is divided as shown in below for display clock CL.divided as shown in below for display clock CL.

-The relation between duty and divide -The relation between duty and divide

Duty 1/8 1/16 1/24 1/32 1/40 1/48,56 1/64,72 1/80,88 1/96,104

Divide 1/50 1/25 1/16 1/12 1/10 1/8 1/6 1/5 1/4

(g) Power Supply Circuit(g) Power Supply Circuit Internal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power SupplyInternal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power Supply Circuit consists of Voltage Booster (5-Time maximum) Circuits, Regulator Circuits, and Voltage Followers.Circuit consists of Voltage Booster (5-Time maximum) Circuits, Regulator Circuits, and Voltage Followers. The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large sizeThe internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size LCD panel application. If the contrast is not good in the large size LCD panel application, please supply theLCD panel application. If the contrast is not good in the large size LCD panel application, please supply the external.external. The suitable values of the capacitors connecting to the VThe suitable values of the capacitors connecting to the V11 to V to V55 terminals and the voltage booster circuit, and terminals and the voltage booster circuit, and the feedback resistors for Vthe feedback resistors for V55 operational amplifier depend on the LCD panel. And the power consumption with operational amplifier depend on the LCD panel. And the power consumption with the LCD panel is depending on the display pattern. Please evaluate with actual LCD module.the LCD panel is depending on the display pattern. Please evaluate with actual LCD module. The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction.The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulatorWhen the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of Vcircuits, voltage follower circuits are turned off. In this time, the bias voltage of V11, V, V22, V, V33, V, V44, and V, and V55 for the for the LCD should be supplied from outside, terminals C1LCD should be supplied from outside, terminals C1++, C1, C1--, C2, C2++, C2, C2--, and VR should be open. The status of, and VR should be open. The status of internal power supply is selected by Tinternal power supply is selected by T11 and T and T22 terminal. Furthermore the external power supply operates with terminal. Furthermore the external power supply operates with some of internal power supply function.some of internal power supply function.

T1 T2

L L/H ON ON ON H L OFF ON ON VOUT Open H H OFF OFF ON V5,VOUT Open Open

When (TWhen (T11, T, T22)=(H, L), C1)=(H, L), C1++, C1, C1--, C2, C2++, C2, C2--,C3,C3++, C3, C3--, C4, C4++, C4, C4-- terminals for voltage booster circuits are open terminals for voltage booster circuits are open because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the Vbecause the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUTOUT terminal terminal should be supplied from outside.should be supplied from outside. When (TWhen (T11, T, T22)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster circuits and Voltage adjust circuits do not operate.circuits and Voltage adjust circuits do not operate.

Voltage

Booster

Voltage Adj. Buffer(V/F) Ext.Pow Supply

C1+,C1- to

C4+,C

VR Term.

Power Supply applicationsPower Supply applications

(1)External power supply operation.(1)External power supply operation. (2)Internal power supply operation.(2)Internal power supply operation.

(Voltage Booster, Voltage Adj., Buffer(V/F)) (Voltage Booster, Voltage Adj., Buffer(V/F)) Internal power supply ON (instruction) (T Internal power supply ON (instruction) (T1,1,TT22)=(L,L))=(L,L)

OUT

DDVR

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(3)External power supply operation with(3)External power supply operation with Voltage Adjustment,3 Buffer(V/F) Voltage Adjustment,3 Buffer(V/F) Internal power supply ON (Instruction) (T Internal power supply ON (Instruction) (T11,T,T22) = (H,L)) = (H,L)

OUT

DDVR

(4)External power supply operation adjusted(4)External power supply operation adjusted Voltage to V5. Voltage to V5. Internal power supply (Instruction) (T Internal power supply (Instruction) (T11,T,T22) =(H,H)) =(H,H)

OUT

: These switches should be open during the power save mode. : These switches should be open during the power save mode.

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