JRC NJU39610FM2, NJU39610D2 Datasheet

MICROSTEPPING MOTOR CONTROLLER WITH DUAL DAC

■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE

NJU39610 is a dual 7-bit+sign, Digital-to-Analog Converter (DAC) especially developed to be used together with the NJM3771, Precision Stepper Motor driver in micro-stepping applications. The NJU39610 has a set of input registers connected to an 8-bit data port for easy interfacing directly to a microprocessor. The NJU39610 is well suited for highspeed micro-stepping application.

NJU39610D2 NJU39610FM2

■ FEATURES

• Analog control voltages from 3 V down to 0.0 V

• High-speed microprocessor interface

NJU39610

• Automatic fast/slow current decay control

• Full-scale error ±1 LSB

• Fast conversion speed 3 µs

• Matches NJM3771

• Packages DIP22/PLCC28

■ BLOCK DIAGRAM

D7 - D0

RESET

POR

DA- Data 1

Level 1

Level 2

DA- Data 2

Digit Comp

Ref

NJU39610

D / A

Sign

Figure 1. Block Diagram

■ PIN CONFIGURATIONS

NJU39610

Sign

CD V

D7 D6 D5 D4 D3

ref

NJU

39610D2

Reset DA

Sign CD

CS A1

A0 D0 D1 D2

N/C

Reset

N/C V DA N/C

ref

Sign

432

39610FM2

12131415161718

Sign

NJU

282726

N/C

Figure 2. Pin configurations

■ PIN DESCRIPTION

Refer to figure 2.

DIP PLCC Symbol Description

19V 210DA1Digital-to-Analog 1, voltage output. Output between 0.0 V and VR - 1 LSB. 3 12 Sign

Ref

413CD1Current Decay 1, TTL/CMOS level. The signal is automatically generated when 514VDDVoltage Drain-Drain, logic supply voltage. Normally +5 V.

6 15 WR Write, TTL/CMOS level, input for writing to internal registers. 7 16 D7 Data 7, TTL/CMOS level, input to set data bit 7 in data word.

8 17 D6 Data 6, TTL/CMOS level, input to set data bit 6 in data word. 9 19 D5 Data 5, TTL/CMOS level, input to set data bit 5 in data word. 10 20 D4 Data 4, TTL/CMOS level, input to set data bit 4 in data word. 11 21 D3 Data 3, TTL/CMOS level, input to set data bit 3 in data word. 12 23 D2 Data 2, TTL/CMOS level, input to set data bit 2 in data word. 13 24 D1 Data 1, TTL/CMOS level, input to set data bit 1 in data word. 14 25 D0 Data 0, TTL/CMOS level, input to set data bit 0 in data word. 15 27 A0 Address 0, TTL/CMOS level, input to select data transfer,

16 28 A1 Address 1, TTL/CMOS level, input to select data transfer. A1 selects between normal 17 1 CS Chip Select, TTL/CMOS level, input to select chip and activate data transfer 18 2 V 19 3 CD 20 4 Sign 21 6 DA

22 7 Reset Reset, digital input resetting internal registers.

5 8 11 N/C Not Connected 18 22 26

Voltage reference supply pin, 2.5 V nominal (3.0 V maximum) Sign 1, TTL/CMOS level. To be connected directly to NJM3771 Phase input.

Databit D7 is transfered non inverted from NJU39610 data input. decay level is programmed. LOW level = fast current decay.

Data is clocked into flip flops on positive edge.

A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH). D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH). from data inputs. LOW level = chip is selected.

Voltage Source-Source. Ground pin, 0 V reference for all signals and measurements unless otherwise noted. Current Decay 2, TTL/CMOS level. The signal is automatically generated when decay level is programmed. LOW level = fast current decay . Sign 2. TTL/CMOS level. To be connected directly to NJM3771 sign input. Data bit D7 is transfered non-inverted from NJU39610 data input. Digital-to-Analog 2, voltage output. Output between 0.0 V and V

HIGH level = Reset, V

≥ 3.5 V = HIGH level. Pulled low internally.

Res

- 1 LSB.

ref

NJU39610

■ DEFINITION OF TERMS Resolution

Resolution is defined as the reciprocal of the number of discrete steps in the DAC output. It is directly related to the number of switches or bits within the DAC. For example, NJU39610 has 27, or 128, output levels and therefor has 7 bits resolution. Remember that this is not equal to the number of microsteps available.

Linearity Error

Linearity error is the maximum deviation from a straight line passing through the end points of the DAC transfer characteristic. It is measured after adjusting for zero and full scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted.

Power Supply Sensitivity

Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output

Settling Time

Full-scale current settling time requires zero-to-full-scale or full-scale-to-zero output change. Settling time is the time required from a code transition until the DAC output reaches within ±1/2LSB of the final output value.

Full-scale ErrorFull-scale error is a measure of the output error between an ideal DAC and the actual device output.

Differential Non-linearity

The difference between any two consecutive codes in the transfer curve from the theoretical 1LSB, is differential non-linearity

Monotonic

If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 7-bit DAC which is monotonic to 7 bits simply means that increasing digital input codes will produce an increasing analog output. NJU39610 is monotonic to 7 bits.

■ FUNCTIONAL DESCRIPTION

Each DAC channel contains two registers, a digital comparator, a flip flop, and a D/A converter. A block diagram is shown on the first page. One of the registers stores the current level, below which, fast current decay is initiated. The status of the CD outputs determines a fast or slow current decay to be used in the driver.

The digital comparator compares each new value with the previous one and the value for the preset level for fast current decay. If the new value is strictly lower than both of the others, a fast current decay condition exists. The flip flop sets the CD output. The CD output is updated each time a new value is loaded into the D/A register. The fast current decay signals are used by the driver circuit, NJM3771, to change the current control scheme of the output stages. This is to avoid motor current dragging which occurs at high stepping rates and during the negative current slopes, as illustrated in figure 9. Eight different levels for initiation of fast current decay can be selected.

The sign outputs generate the phase shifts, i.e., they reverse the current direction in the phase windings.

Output

More than 2 bits

Negative difference

Output

Less than 2 bits

Positive difference

Output

Actual

Offset error

Gain error

Correct

Endpoint non-linearity

Input

Figure 3. Errors in D/A conversion. Differential non-linearity of more than 1 bit, output is non-monotonic.

Input

Figure 4. Errors in D/A conversion. Differential non-linearity of less than 1 bit, output is monotonic.

Full scale

Input

Figure 5. Errors in D/A conversion. Non-linearity, gain and offset errors.

NJU39610

Data Bus Interface

NJU39610 is designed to be compatible with 8-bit microprocessors such as the 6800, 6801, 6803, 6808, 6809, 8051, 8085, Z80 and other popular types and their 16/32 bit counter parts in 8 bit data mode. The data bus interface consists of 8 data bits, write signal, chip select, and two address pins. All inputs are TTL-compatible (except reset). The two address pins control data transfer to the four internal D-type registers. Data is transferred according to figure 10 and on the positive edge of the write signal.

Current Direction, Sign1 & Sign

These bits are transferred from D7 when writing in the respective DA register. A0 and A1 must be set according to the data transfer table in figure 10.

Current Decay, CD1 & CD

CD1 and CD2 are two active low signals (LOW = fast current decay). CD1 is active if the previous value of DA-Data1 is strictly larger than the new value of DA-Data1 and the value of the level register LEVEL1 (L61 … L41) is strictly larger than the new value of DA-Data1. CD1 is updated every time a new value is loaded into DA-Data1. The logic definition of CD1 is:

CD1 = NOT{[(D6 … D0) < (Q61 … Q01)] AND[(D6 …D4) < (L61 … L41)]} Where (D6 … D0) is the new value being sent to DA-Data1 and (Q61 … Q01) is DA-Data1’s old value. (L61 … L41) are

the three bits for setting the current decay level at LEVEL1.

The logic definition of CD2 is analog to CD1: CD2 = NOT{[(D6 … D0) < (Q62 … Q02)] AND[(D6 …D4) < (L62 … L42)]} Where (L62 … L42) is the level programmed in channel 2’s level register. (D6 … D0) and (Q62 … Q02) are the new and

old values of DA-Data2.

The two level registers, LEVEL1 and LEVEL2, consist of three flip flops each and they are compared against the three most significant bits of the DA-Data value, sign bit excluded.

T [mNm]

I [mA]

max

nom

min

DA output [V]

Current dragging

I [mA]

Figure 6a. Assuming that torque is proportional to the current in resp. winding it is possible to draw figure 8b.

CS A0 A1 Data Transfer 0 0 0 D7 —> Sign1, (D6—D0) —> (Q61—Q01), New value —> CD1 0 0 1 (D6—D4) —> (L61—L41) 0 1 0 D7 —> Sign2, (D6—D0) —> (Q62—Q02), New value —> CD2 0 1 1 (D6—D4) —> (L62—L42) 1 X X No Transfer

Figure 8. Table showing how data is transfered inside NJU39610.

T [mNm]

Figure 6b. An example of accessible positions with a given torque deviation/fullstep. Note that 1:st µstep sets highest resolution. Data points are exaggerated for illustration purpose. TNom = code 127.

Time

Figure 7. Motor current dragging at high step rates and current decay influence. Fast current decay will make it possible for the current to follow the ideal sine curve. Output shown without sign shift.

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