Output Power: 500W RMS x 1 channels @ 4 ohms; ≤1% THD + N
(14.4V supply) 500W RMS x 1 channels @ 2 ohms; ≤1% THD + N
Signal-to-noise ratio: 80dBA (reference 1W into 4 ohms)
106dBA (reference rated power into 4 ohms)
Total Peak power: 500W
Frequency response: 20Hz – 270Hz (–3dB)
THD+N 1KHz LPF=22KHz < 1.0 % (rated power @ 4 ohms)
Input Impedance 10kΩ (Hi2 = 120)
Maximum input signal: 20.0V
Maximum sensitivity: 100mV
Bass Boost @ 80Hz 10dB
DC Offset <50mV
Idle Current @ 4 ohms <1.5A
Max Current Draw ≤45A
Remote Operating Voltage 5-16VDC
Turn-on delay time 1 sec
Circuit Protection
Dimensions: 7-3/16" x 8-1/4" x 2-3/4" 183mm x 210mm x 70mm
Fuse: 2 x 40A
JBL continually strives to update and improve existing products, as well as create new ones. The specifications and details in
this and related JBL publications are therefore subject to change without notice.
Temp (85±5C), Short circuit, Operating voltage range (9-16V)
Page 3
15
14
NOPART NUMBERDESCRIPTIONQTY
2
MS-A5001
157.12.MS-A10040
257.12.TINY4R1000
1
11
3
4241-59.11.MS-A50010
TOP FOAM PACKAGING
BOTTOM FOAM PACKAGING
SNOW BOX-TOP
SNOW BOX-BOTTON
PLASTIC BAG
OUTER CARTON
GIFT BOX
1
1
1
1
12
MASTER CARTON
5240-58.11.MS-A50010
6
756.13.TINY1R5000
3
8
956.18.TINY1R5001
10
11272-38.112.TINY2
12
visit www.jbl.com
13
1465.1.2R5201
1565.1.04201
CARTON BOX
DESICCANT
SERIAL LABEL
GIFT LABEL
CARTON LABEL
CE LABEL
SETUP CD
OWNER'S MANUAL
CD
MANUAL
PLASTIC BAG
2.5mm ALLEN WRENCH
4.0 mm ALLEN WRENCH
1
1
2
1
1
1
1
1
2
16
13
RCA to bare wire Adapters
1626.121.112101
6
17
56.15.MSA50010
RCA(BLACK) TACK
LABEL
4
1
2
17
4
7
10
Automotive amplifier DC14.4V 80A
FCC ID: TN5MSA5001AS
IC: 6132C-MSA5001AS
This device complies with part 15 of the
FCC Rules. Operation is subject to the
following two conditions:
(1) This device may not cause harmful
interference, and
(2) this device must accept any interference
received, including interference that may
cause undesired operation.
Harman consumer,Inc
Made in China
MADE IN CHINA
5
9
TINY
2010.06.24
8
MP-10D5-0076
Page 4
1
2
Input
1
2
1
2
I
nput
O
utput
Lo
Hi
Hi2
I
nput
L
e
3
MS-A5001
1
3
2
4
1
Lo Hi Hi2
1
InputOutput
3
2
Level
Input
1
2
6
40 A
2X40A
40 A
5
9
8
10
11
8
1 x 80A
+
-
10
11
Page 5
4
MS-A5001
1
4
9
5
2
6
3
7
8
10
11
Page 6
5
MS-A5001
NOTE: Although some typical connections and
®
controls are shown, JBL
MS Series amplifiers
include many features and digital controls not
found on conventional car audio amplifiers.
Also, the setup (or testing) procedure for MS
Series amplifiers is different (more
complicated) from that of conventional car
audio amplifiers.
Details can be found in the MS-A5001 owner’s
manual, which can be downloaded here:
• Combined control pin for switching regulators 1 and 3
• Separate control pins for switching regulator 4 and the
power switch
• Supply voltage range from −18 to +50 V
• Low quiescent current in standby mode (when
regulators 1, 3 and 4 andpower switchare switchedoff
and ignition input is low)
• Hold outputfor low VP(regulators 1, 3 and 4 andpower
switch off)
• Hold output when one of regulators 1 and 3 and/or 4 is
out of regulation
• Hold output for foldback mode of power switch and
regulators 1, 3 and 4
• Hold output for load dump and temperature protection
• Reset (push-pull output stage) for regulator 2 and hold
output (open-collector output)
• Adjustable reset delay time
• High supply voltage ripple rejection
• Backup capacitor for regulator 2
• One independent ignition buffer (active HIGH).
Protections
• Reverse polarity safe (down to −18 V without high
reverse current)
• Able to withstand voltages up to 18 V at the outputs
(supply line may be short-circuited)
• ESD protection on all pins
• Thermal protections
• Load dump protection
• Foldback current limit protection for regulators 1, 2, 3
• Delayed second current limit protection for the power
• The regulator outputs and the power switch are
GENERAL DESCRIPTION
The TDA3681is a multiple output voltageregulator with a
power switch andanignition buffer. Itis intended foruse in
car radioswith orwithout amicrocontroller. The TDA3681
contains the following:
• Four fixed voltage regulators with a foldback current
• Regulators 3 and 4 have a second supply pin that can
• A power switch with protection, operated by a control
• Reset and hold outputs that can be used to interface
• Both supply pins can withstand load dump pulses and
• Regulator 2, which is in regulation at a backup voltage
• A provisionforthe use ofa reserve supplycapacitorthat
• An ignition input Schmitt trigger with push-pull output
TDA3681
and 4
switch (at short-circuit)
DC short-circuit safe to ground and supply (VP).
protection (regulators 1, 2, 3 and 4). Regulator2, which
is intended to supply a microcontroller, also operates
during load dump and thermal shutdown
be connected to a lower supply voltage (>6.5 V) to
reduce the power dissipation
input
with themicrocontroller; the reset signal canbe used to
call up the microcontroller
negative supply voltages
above 6.5 V
will hold enough energy for regulator 2 (5 V continuous)
to allow a microcontroller to prepare for loss of voltage
stage.
ORDERING INFORMATION
TYPE
NUMBER
TDA3681JDBS17Pplastic DIL-bent-SIL power package; 17 leads (lead length 7.7 mm)SOT243-3
TDA3681JRDBS17Pplastic DIL-bent-SIL (special bent) power package; 17 leads
TDA3681THHSOP20plastic, heatsink small outline package; 20 leads; low stand-off heightSOT418-2
NAMEDESCRIPTIONVERSION
(lead length 12mm)
PACKAGE
SOT475-1
Page 30
29
MS-A5001
Philips SemiconductorsProduct specification
Multiple voltage regulator with switch and
ignition buffer
handbook, full pagewidth
V
P1
ENSW
V
EN4
HEATTAB
n.c.
n.c.
P2
(14.4 V)
14
8
20
6
11
15
18
POWER SWITCH
&
BACKUP SWITCH
BACKUP CONTROL
&
&
TEMPERATURE
LOAD DUMP
PROTECTION
REGULATOR 2
REGULATOR 4
REGULATOR 3
16
13
12
1
19
(14 V/
3 A)
(14 V/
100 mA)
(5 V/
300 mA)
(3.3 V/
1 A)
(5 V/
1400 mA)
TDA3681
SW
BU
REG2
REG4
REG3
EN1/3
C
RES
IGN
TDA3681TH
(8.5 V/
600 mA)
7
&
OR
5
IN
2
IGNITION BUFFER
REGULATOR 1
+
&
10
GND
17
MGU353
REG1
9
4
3
HOLD
RES
IGN
OUT
Fig.2 Block diagram of TDA3681TH.
Page 31
30
MS-A5001
Philips SemiconductorsProduct specification
Multiple voltage regulator with switch and
ignition buffer
Pin description of TDA3681TH
SYMBOLPINDESCRIPTION
REG41regulator 4 output
IGN
IN
IGN
OUT
RES4reset output (active LOW)
C
RES
EN46enable input for regulator 4
EN1/37enable input for regulators 1 and 3
ENSW8enable input for power switch
HOLD9hold output (active LOW)
GND10ground
HEATTAB11heat tab connection; note 1
REG212regulator 2 output
BU13backup switch output
V
1. The pin is used for final test purposes. In the
application it should be connected directly to ground.
Page 32
31
MS-A5001
MC9S08GT16A/GT8A Features
8-Bit HCS08 Central Processor Unit (CPU)
•40-MHz HCS08 CPU
•HC08 instruction set with added BGND instruction
•Support for up to 32 interrupt/reset sources
Memory Options
•FLASH read/program/erase down to 1.8 V
•Up to 16K FLASH; up to 2K RAM
Power-Saving Modes
•Three very low power stop modes
•Reduced power wait mode
•Very low power real time interrupt for use in run,
wait, and stop
Clock Source Options
•Clock sources to internal hardware frequency
locked-loop (FLL): internal, external, crystal, or
resonator
•Internal clock with ±0.2% trimming resolution and
±0.5% deviation across voltage or across
temperature
System Protection
•Software selectable pullups on ports when used as
input
•Internal pullup on RESET and IRQ pin to reduce
customer system cost
•Up to 38 general-purpose input/output (I/O) pins,
plus one output-only pin, depending on package
selection
Development Support
•Background debugging system
•Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
•On-chip, in-circuit emulation (ICE) debug module
with real-time bus capture. On-chip ICE debug
module containing two comparators andnine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data.
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
Figure 1-1. MC9S08GT16A/GT8A Block Diagram
Page 34
33
MS-A5001
Device Overview
Table 1-2 lists the functional versions of the on-chip modules.
Table 1-2. Block Versions
ModuleVersion
Analog-to-Digital Converter (ATD)3
Internal Clock Generator (ICG)4
Inter-Integrated Circuit (IIC)1
Keyboard Interrupt (KBI)1
Serial Communications Interface (SCI)1
Serial Peripheral Interface (SPI)3
Timer Pulse-Width Modulator (TPM)2
Central Processing Unit (CPU)2
1.2System Clock Distribution
SYSTEM
CONTROL
ICGERCLK
FFE
ICG
ICGOUT
ICGLCLK*
* ICGLCLK is the alternate BDC clock source for the MC9S08GT16A/GT8A.
LOGIC
RTI
÷2
FIXED FREQ CLOCK (XCLK)
÷2
CPU
BUSCLK
BDC
Figure 1-2. System Clock Distribution Diagram
TPM1TPM2IICSCI1SCI2SPI
COP
ATD
ATD has min and max
frequency requirements.
See Chapter 14, “Ana-
log-to-Digital Converter
(S08ATDV3)”
and Appendix A, “Electrical
Characteristics.”
RAMFLASH
FLASH has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics”.
Page 35
34
MS-A5001
Chapter 2
Pins and Connections
2.1Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
2.2Device Pin Assignment
DDAD
RESET
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PTC3/SCL
PTC4
PTC5
PTC6
PTE0/TxD1
PTE1/RxD1
IRQ
11
PTG2/EXTAL
44
1
2
3
4
5
6
7
8
9
10
12
PTG1/XTAL
PTG0/BKGD/MS
43
42
13
14
SSAD
V
41
15
V
40
16
PTA6/KBIP6
PTA7/KBIP7
39
38
17
18
19
PTA4/KBIP4
PTA5/KBIP5
37
36
20
PTA2/KBIP2
PTA3/KBIP3
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PTA1/KBIP1
PTA0/KBIP0
V
REFL
V
REFH
PTB7/ADP7
PTB6/ADP6
PTB5/ADP5
PTB4/ADP4
PTB3/ADP3
PTB2/ADP2
PTB1/ADP1
Freescale Semiconductor
SS
SS
PTE2/
PTE3/MISO
PTE4/MOSI
PTE5/SPSCK
DD
V
V
PTB0/ADP0
PTD1/TPM1CH1
PTD0/TPM1CLK/TPM1CH0
PTD4/TPM2CH1
PTD3/TPM2CLK/TPM2CH0
Figure 2-2. MC9S08GT16A/GT8A in 44-Pin QFP Package
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Page 36
35
MS-A5001
2.3Recommended System Connections
Pins and Connections
Figure 2-5 shows pin connections that are common to almost all MC9S08GT16A application systems. A
more detailed discussion of system connections follows.
SYSTEM
POWER
BACKGROUND HEADER
V
DD
OPTIONAL
MANUAL
RESET
V
+
3 V
C
BLK
10 µF
BKGD/MS
+
ASYNCHRONOUS
INTERRUPT
INPUT
DD
C
BY
0.1 µF
V
DD
4.7 kΩ–10 kΩ
0.1 µF
V
DD
4.7 kΩ–10 kΩ
0.1 µF
C
BYAD
0.1 µF
V
V
V
V
V
V
V
REFH
DDAD
SSAD
REFL
DD
SS
SS
MC9S08GT16A
NOTE4
RESET
NOTE 3
IRQ
NOTE 3
PORT
A
PORT
B
PORT
C
PTA0/KBIP0
PTA1/KBIP1
PTA2/KBIP2
PTA3/KBIP3
PTA4/KBIP4
PTA5/KBIP5
PTA6/KBIP6
PTA7/KBIP7
PTB0/ADP0
PTB1/ADP1
PTB2/ADP2
PTB3/ADP3
PTB4/ADP4
PTB5/ADP5
PTB6/ADP6
PTB7/ADP7
PTC0/TxD2
PTC1/RxD2
PTC2/SDA
PTC3/SCL
PTC4
PTC5
PTC6
PTC7
I/O AND
PERIPHERAL
INTERFACE TO
APPLICATION
SYSTEM
PTG0/BKDG/MS
PTG1/XTAL
PTG2/EXTAL
PTG3
NOTE 1
C1
X1
R
F
C2
R
S
XTAL
EXTAL
NOTES:
1. Not required if using the internal oscillator option.
2. The 48-pin QFN has 2 V
3. RC filters on
RESET and IRQ are recommended for EMC-sensitive applications and systems.
ULTRA LOW-POWER 50-mA LOW-DROPOUT LINEAR REGULATORS
SLVS210C – JUNE 1999 – REVISED SEPTEMBER 1999
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2
4
5
DBV PACKAGE
(TOP VIEW)
1
IN
GND
EN
OUT
NC/FB
TA – Free-Air Temperature – °C
15
22
TPS77033
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
Ground Current – Aµ
VI = 4.3 V
CO = 4.7 µF
–400–2020140–604080 100 12060
21
20
19
18
17
16
IO = 0 mA
IO = 50 mA
D
50-mA Low-Dropout Regulator
D
Available in 1.2-V, 1.5-V, 1.8-V, 2.5-V, 2.7-V,
2.8-V, 3.0-V, 3.3-V, and 5-V Fixed-Output and
Adjustable Versions
D
Only 17 µA Quiescent Current at 50 mA
D
1 µA Quiescent Current in Standby Mode
D
Dropout Voltage Typically 35 mV @ 50mA
D
Over Current Limitation
D
–40°C to 125°C Operating Junction
T emperature Range
D
5-Pin SOT-23 (DBV) Package
description
The TPS770xx family of low-dropout (LDO) voltage regulators offers the benefits of low dropout voltage, ultra
low-power operation, and miniaturized packaging. These regulators feature low dropout voltages and ultra low
quiescent current compared to conventional LDO regulators. Offered in a 5-terminal small outline
integrated-circuit SOT-23 package, the TPS770xx series devices are ideal for micropower operations and
where board space is at a premium.
A combination of new circuit design and process innovation has enabled the usual PNP pass transistor to be
replaced by a PMOS pass element. Because the PMOS pass element behaves as a low-value resistor, the
dropout voltage is very low — typically 35 mV at 50 mA of load current (TPS77050) — and is directly proportional
to the load current. Since the PMOS pass element is a voltage-driven device, the quiescent current is ultra low
(28 µA maximum) and is stable over the entire range of output load current (0 mA to 50 mA).
Intended for use in portable systems such as
laptops and cellular phones, the ultra low-dropout
voltage feature and ultra low-power operation
result in a significant increase in system battery
operating life.
The TPS770xx also features a logic-enabled
sleep mode to shut down the regulator, reducing
quiescent current to 1 µA typical at T
J
= 25°C. The
TPS770xx is offered in 1.2-V, 1.5-V, 1.8-V, 2.5-V,
2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5-V fixed-voltage
versions and in a variable version (programmable
over the range of 1.2 V to 5.5 V).
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
36
MS-A5001
Page 38
Data Sheet
26185.201
6276
16-BIT SERIAL-INPUT, CONSTANTCURRENT LATCHED LED DRIVER
Always order by complete part number, e.g., A6276EA .
The A6276EA and A6276ELW are specifically designed for LEDdisplay applications. Each BiCMOS device includes a 16-bit CMOS
shift register, accompanying data latches, and 16 npn constant-current
sink drivers. Except for package style and allowable package power
dissipation, the two devices are identical.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is determined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. Similar 8-bit devices are available as the
A6275EA and A6275ELW.
Two package styles are provided for through-hole DIP (suffix A) or
surface-mount SOIC (suffix LW). Under normal applications, a copper
lead frame and low logic-power dissipation allow the dual in-line
package to sink maximum rated current through all outputs continuously over the operating temperature range (90 mA, 0.75 V drop,
+85°C). Both devices are also available for operation over the standard
temperature range of -20°C to +85°C. To order, change the suffix
letter ‘E’ to ‘S’.
Note that the A6276EA (DIP) and the A6276ELW
(SOIC) are electrically identical and share a
common terminal number assignment.
A6276ELW
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD...................... 7.0 V
Output Voltage Range,
V
O
............................ -0.5 V to +17 V
Output Current, IO........................ 90 mA
Ground Current, I
GND
............... 1475 mA
Input Voltage Range,
V
I
.................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
P
D
..................................... See Graph
Operating Temperature Range,
T
A
............................. -40°C to +85°C
Storage Temperature Range,
T
S
........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
FEATURES
■ To 90 mA Constant-Current Outputs
■ Under-Voltage Lockout
■ Low-Power CMOS Logic and Latches
■ High Data Input Rate
■ Functional Replacement for TB62706BN/BF
GROUND
REGISTER
LATCHES
1
2
3
817
18
19
20
21
23
4
5
6
7
22
24
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCKCK
V
DD
OE
OUT
1
OUT
2
OUT
0
OUT
12
OUT
14
OUT
13
OUT
3
OUT
15
R
EXT
I
REGULATOR
L
O
12
9
10
11
OUT
5
OUT
6
OUT
4
OUT
7
13
14
15
16
Dwg. PP-029-11
OUT
8
OUT
10
OUT
9
OUT
11
37
MS-A5001
Page 39
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
5075100125150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °C
2.0
1.5
1.0
25
Dwg. GP-022-3
24-LEAD SOIC, R
θJA
= 75°C/W
24-PIN DIP, R
θJA
= 50°C/W
FUNCTIONAL BLOCK DIAGRAM
MOS
BIPOLAR
GROUND
LATCH
ENABLE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
LOGIC
SUPPLY
R
EXT
OUT0OUT
1
Dwg. FP-013-3
OUT
2
OUT
N
I
REGULATOR
O
UVLO
38
MS-A5001
Page 40
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
3
CLOCK and SERIAL DATA INSERIAL DATA OUT
LATCH ENABLEOUTPUT ENABLE (active low)
Dwg. EP-010-6
IN
V
DD
Dwg. EP-010-7
IN
V
DD
Dwg. EP-010-5
IN
V
DD
Dwg. EP-063-1
V
DD
OUT
TRUTH TABLE
Serial Shift Register ContentsSerialLatchLatch ContentsOutputOutput Contents
DataClockDataEnableEnable
Input Input I
1I2I3
...I
N-1IN
OutputInputI1I2I3...I
N-1IN
InputI1I2I3... I
N-1
I
N
HHR
1R2
...R
N-2RN-1
R
N-1
LLR
1R2
...R
N-2RN-1
R
N-1
XR
1R2R3
...R
N-1RN
R
N
XXX...X XX LR1R2R3...R
N-1 RN
P1P2P3...P
N-1PN
P
N
HP1P2P3...P
N-1 PN
LP1P2P3... P
N-1 PN
XXX...X X HH H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
39
MS-A5001
Page 41
MIC2981/2982Micrel, Inc.
MIC2981/2982
High-Voltage High-Current Source Driver Array
General
The MIC2981/82 is an 8-channel, high-voltage, high-current
source driver array ideal for switching high-power loads from
logic-level TTL, CMOS, or PMOS control signals.
These drivers can manage multiple loads of up to 50V and
500mA, limited only by package power dissipation.
Micrel’s MIC2981/82 features inputs compatible with 5V TTL
and 5V to 15V CMOS or PMOS logic outputs. Micrel’s
dual-marked device replaces either UDN2981 or UDN2982
devices.
The MIC2981/82 is available in the 18-pin plastic DIP and
18-lead wide SOP package. Both devices operate in the
industrial temperature range.
MIC2981BN**MIC2981/82BNMIC2981/82YN–40ºC to +85ºC18-pin DIP
MIC2982BN**MIC2981/82BNMIC2981/82YN–40ºC to +85ºC18-pin DIP
MIC2981BWM**MIC2981/82BWMMIC2981/82YWM–40ºC to +85ºC18-pin wide SOP
MIC2982BWM**MIC2981/82BWMMIC2981/82YWM–40ºC to +85ºC18-pin wide SOP
*Order entry P/N.
**Orders for MIC2981BN or MIC2982BN will be filled with dual-marked MIC2981/82BN.
**Orders for MIC2981YN or MIC2982YN will be filled with dual-marked MIC2981/82YN.
**Orders for MIC2981BWM or MIC2982BWM will be filled with dual-marked MIC2981/82BWM.
**Orders for MIC2981YWM or MIC2982YWM will be filled with dual-marked MIC2981/82YWM.
40
MS-A5001
Page 42
MIC2981/2982Micrel, Inc.
Pin Configuration
2IN2OUT217
3IN3OUT316
4IN4OUT415
5IN5OUT514
6IN6OUT613
7IN7OUT712
1IN1OUT118
8IN8OUT811
9V
S
GND10
18-Pin DIP (N)
18-Pin Wide SOP (WM)
Pin No.Pin No.Pin NamePin Function
1–8IN1–IN8Input 1 through Input 8: Base drive to driver input transistor.
9V
S
Supply Input
10GNDGround
11–18OUT8–OUT1Output 8 through Output 1: Emitter of Darlington driver output.
Pin Description
41
MS-A5001
Page 43
42
MS-A5001
Philips SemiconductorsProduct specification
3-to-8 line decoder/demultiplexer74HC/HCT238
FEATURES
• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active HIGH mutually exclusive outputs
• Output capability: standard
• ICC category: MSI
provide 8 mutually exclusive active HIGH outputs
(Y0 to Y7).
The “238” features three enable inputs: two active LOW
(
E1 and E2) and one active HIGH (E3). Every output will be
LOW unless
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
The “238” can be used as an eight output demultiplexer by
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The “238” is identical to the “138” but has non-inverting
outputs.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A
, A1, A2) and when enabled,
0
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOLPARAMETERCONDITIONS
t
PHL/ tPLH
C
I
C
PD
propagation delayCL= 15 pF; VCC=5 V
A
to Y
n
n
E
to Y
3
n
En to Y
n
input capacitance3.53.5pF
power dissipation capacitance per packagenotes 1 and 27276pF
E1 and E2 are LOW and E3 is HIGH.
TYPICAL
UNIT
HCHCT
1418ns
1620ns
1721ns
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
outputs
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset movie nighttime listening mode
– Preset TV channel/commercial AGC mode
– 5.1, 2.1 bass management configurations
– AM frequency automatic output PWM
frequency shifting
– 8 preset crossover filters
! Individual channel and master soft/hard mute
! Automatic zero-detect and invalid input mute
! Automatic invalid input detect mute
®
! Advanced PopFree operation
! Advanced AM interference frequency
TQFP64
switching and noise suppression modes
2
! I
S output channel mapping function
! Independent channel volume and DSP bypass
! Channel mapping of any input to any
processing/DDX
! DC blocking selectable high-pass filter
! Selectable per-channel DDX
®
channel
®
damped ternary
or binary PWM output
! Max power correction for lower full-power THD
! Variable per channel DDX
! 192 kHz internal processing sample rate, 24-bit
®
o
utput delay control
to 36-bit precision
Description
The STA309A is a single chip solution for digital
audio processing and control in multi-channel
applications. It provides output capabilities for
®
(direct digital amplification). In conjunction
DDX
with a DDX
quality, high-efficiency, all digital amplification.
The device is extremely versatile, allowing for
input of most digital formats including 6.1/7.1channel and 192 kHz, 24-bit DVD-audio,
DSD/SACD. In 5.1 application the additional 2
channels can be used for audio line-out or
headphone drive. In speaker mode, with 8
channel outputs in parallel, the STA309A can
deliver more than 1 W.
Table 1.Device summary
STA309ATQFP64
®
power device, it provides high-
Order codePackage
September 2007 Rev 11/67
www.st.com
67
Page 49
(
)
48
MS-A5001
STA309ABlock diagram
1 Block diagram
Figure 1.Block diagram
LRCKI
BICKI
SDI12
SDI34
SDI56
SDI78
PLLB
SERIAL
CHANNEL
MAPPING
PLL
XTI
SA
DATA
IN
SYSTEM TIMING
CKOUT
VARIABLE
OVER-
SAMPLING
Figure 2.Channel signal flow
6 Inputs
From DSD
DSD
Conversion
Interp_Rate
SCL
SDA
I2C
SYSTEM
CONTROL
POWER
DOWN
PWDN
MVO
TREBLE,
BASS, EQ
BIQUADS
EAPD
OVERSAMPLING
VOLUME
LIMITING
VARIABLE
DOWN-
SAMPLING
DDX
SERIAL
DATA
OUT
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKO
BICKO
SDO12
SDO34
SDO56
SDO78
8 Inputs
From I2S
From
Mix#1
Engine
Or
Previous
Channel
Biq ua d # 1 0
Output
(CxBLP)
PreScale
Hard Set to
-18dB when
AutoMode EQ
(AMEQ)
1x,2x,4x
Interp
Distortion
Compensation
High - Pa s s
Filte r
User Progammable
Biquad #1 when
High-Pass Bypassed
(HPB)
DSDE
Mapping/
Mix #1
Biq ua ds
B/ T
Mix #2
Vol um e
Limiter
NSC_ConPWM
Biq ua d#2Biquad#3Biquad#4Biqu a d#5Biquad#6Biquad#7Biquad
Hard Set Coeffecients when AutoMode EQ
(AMEQ)
Hard Set
Coeffec ients when
Aut oM od e
Bass Management
Cross over
(AMBMXE)
Hard Set
Coeffec ients when
DeEmphasis
Enable d
(DEMP)
9/67
2x
Interp
DDX
Output
To
Mix#2
Treble
Engine
Bas s
#8
User Prog rammable
Biquads #9 and #10
When Tone Bypass ed
(CxTCB)
Page 50
49
MS-A5001
Pin connectionsSTA309A
2 Pin connections
Figure 3.Pin connection (top view)
VDD
SDO_34
SDO_12
LRCKONCBICKO
GND
VDD
EAPD
OUT1_A
OUT8_B
OUT8_A
OUT1_B
OUT7_B
OUT7_A
48
OUT2_A
47
OUT2_B
46
NC
45
GND
44
VDD
43
OUT3_A
42
OUT3_B
41
OUT4_A
40
OUT4_B
39
OUT5_A
38
OUT5_B
37
NC
36
GND
35
VDD
34
OUT6_A
33
OUT6_B
STA308APINCON
MVO
GND
VDD
GND
SDI_78
SDI_56
SDI_34
SDI_12
LRCKI
BICKI
VDD
GND
RESET
PLLB
NC
NC
SDO_78
PWDN
63
64
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17 18 19 20 21
SA
SDA
GND61NC62SDO_56
60
59 58 57 56545553 52 51 50 49
22 23 24 25 26
SCL
XTI
FILTER_PLL
NC
GNDA
VDDA
NC
CKOUT
271128 29 30 31 32
VDD
GND
Table 2.Pin description
PinTypeNameDescription
15-V tolerant TTL input buffer MVO/DSD_CLK
65-V tolerant TTL input buffer SDI_78/DSD_6
75-V tolerant TTL input buffer SDI_56/DSD_5
85-V tolerant TTL input buffer SDI_34/DSD_4
95-V tolerant TTL input buffer SDI_12/DSD_3
105-V tolerant TTL input buffer LRCKI/DSD_2
115-V tolerant TTL input buffer BICKI/DSD_1
15
16
5-V tolerant TTL schmitt
trigger input buffer
CMOS input buffer with
pull-down
RESETGlobal reset
PLL_BYPASSBypass phase locked loop
Master volume override/
DSD input clock
Input serial data channels 7 & 8/
DSD input channel 6
Input serial data channels 5 & 6/
DSD input channel 5
Input serial data channels 3 & 4/
DSD input channel 4
Input serial data channels 1 & 2/
DSD input channel 3
BADD0 Series,BACC0 Series,
BADD0W Series,BACC0W Series
Block Diagrams
BACC0WFP/ BADD0WHFP/ BACC0WT(V5)/ BADD0WT
Vref
GND
Fin
Driver
(TO252-5
HRP5)
Vcc
R2
TSDOCP
OVP
R1
12
CTL Vcc N.C. OUT N.C.
(TO252-5)
GND
Fig.25
4
3
(TO220FP-5,-5(V5),HRP5)
5
CC0T/ BACC0FP/ BADD0T
BA
GND
(TO252-3)
Fin
Vref
Driver
Vcc
R2
TSDOCP
OVP
R1
1
Vcc N.C. OUT
2
(TO252-3)
GND
(TO220FP-3)
3
Fig.26
Input / Output Equivalent Circuit Diagrams
BADD0 Series
<
><
Vcc
CTL
2k
39k
31k
Fig.27Fig.28
BA50DD0WHFP
TOP VIEW
FIN
TO252-5
TOP VIEW
1 2 3 4 5 1 2 3 4 5
TO220FP-5 TO220FP-5
TOP VIEW
FIN
2 3
1
TO252-3
Vcc
10k
R2
R1
1 2 3 4 5
HRP5
TOP VIEW
V5
TOP VIEW
2 3 1
TO220FP-3
BACC0 Series
CTL
OUT
Technical Note
PIN No.Pin NameFunction
1 CTL Output voltage ON/OFF control
2 Vcc Power supply voltage input
3 N.C/GND Unconnected terminal/GND*1
4 OUT Voltage output
5 N.C Unconnected terminal
Fin GND GND*2
2 Only for TO252-5 and HRP5
1 TO252-5 is N.C.,and TO220FP-5,-5(V5),and HRP5 are GND
PIN No.Pin Name Function
1 Vcc Power supply voltage input
2 N.C/GND Unconnected terminal/GND*1
3 OUT Voltage output
Fin GND GND *2
1 TO252-3 is N.C.,and TO-220FP-3,is GND
2 Only for TO252-3 and HRP5
>
Vcc
25k
25k
R2
R1
OUT
Page 54
53
MS-A5001
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
Single chip 2.4 GHz Transceiver
Q5)
)($785(6$33/,&$7,216
•
True single chip GFSK transceiver in a small
24-pin package (QFN24 5x5mm)
•
Data rate 0 to1Mbps• Wireless data communication
•
Only 2 external components• Alarm and security systems
• Multi channel operation
• 125 channels
• Channel switching time <200µs.
• Support frequency hopping
•
Data slicer / clock recovery of data• Telemetry
•
Address and CRC computation• Intelligent sports equipment
•
DuoCeiver™ for simultaneous dual receiver
topology
•
ShockBurst™ mode for ultra-low power
operation and relaxed MCU performance
• Power supply range: 1.9 to 3.6 V
• Low supply current (TX), typical 10.5mA peak
@ -5dBm output power
• Low supply current (RX), typical 18mA peak in
receive mode
• 100% RF tested
• No need for external SAW filter
• World wide use
• Wireless mouse, keyboard, joystick
•
Keyless entry
• Home automation
• Home automation
• Surveillance
• Automotive
•
Industrial sensors
•
Toys
*(1(5$/'(6&5,37,21
nRF2401 is a single-chip radio transceiver for the world wide 2.4 - 2.5 GHz ISM
band. The transceiver consists of a fully integrated frequency synthesizer, a power
amplifier, a crystal oscillator and a modulator. Output power and frequency channels
are easily programmable by use of the 3-wire serial interfac e. Current consumption i s
very low, only 10.5mA at an output power of -5dBm and 18mA in receive mode.
Built-in Power Down modes makes power saving easily realizable.
48,&.5()(5(1&('$7$
3DUDPHWHU9DOXH8QLW
Minimum supply voltage1.9V
Maximum output power0dBm
Maximum data rate1000kbps
Supply current in transmit @ -5dBm output power10.5mA
Supply current in receive mode18mA
Temperature range-40 to +85
Sensitivity-90dBm
Supply current in Power Down mode1
Table 1 nRF2401 quick reference data
° C
µΑ
Page 55
54
MS-A5001
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
7\SH1XPEHU'HVFULSWLRQ9HUVLRQ
NRF2401 IC24 pin QFN 5x5A
NRF2401-EVKITEvaluation kit (2 test PCB, 2 configuration PCB, SW)1.0
Table 2 nRF2401 ordering information
%/2&.',$*5$0
Data
Channel 2
Data
Channel 1
3-wire
interface
PWR_UP
VSS=0V
CE
DR2
DOUT2
CLK2
DR1
DATA
CLK1
CS
DuoCeiver
ShockBurst
DEMOD
Recovery,
DataSlicer
Code/Decode
TM
TM
Clock
ADDR
Decode
CRC
FIFO
In/Out
GFSK
Filter
DVDD
VSS=3V
VDD=3V
IF BPF
VSS=0V
VDD=3V
Frequency
Synthesiser
VSS=0V
LNA
VSS=0V
PA
VSS=0V
XC1
XC2
VSS_PA=0V
VDD_PS=1.8V
ANT1
400
IREF
Ω
22k
Ω
ANT2
Figure 1 nRF2401 with external components.
Page 56
55
MS-A5001
PRODUCT SPECIFICATION
Q5)6LQJOH&KLS*+]5DGLR7UDQVFHLYHU
3,1)81&7,216
3LQ1DPH3LQIXQFWLRQ'HVFULSWLRQ
1CEDigital InputChip Enable Activates RX or TX mode
2DR2Digital OutputRX Data Ready at Data Channel 2 (ShockBurst™ only)
3CLK2Digital I/OClock Output/Input for RX Data Channel 2
4DOUT2Digital OutputRX Data Channel 2
5CSDigital InputChip Select Activates Configuration Mode
6DR1Digital OutputRX Data Ready at Data Channel 1 (ShockBurst™ only)
7CLK1Digital I/OClock Input (TX) & Output/Input (RX) for Data Channel 1
3-wire interface
8DATADigital I/ORX Data Channel 1/TX Data Input/ 3-wire interface
9DVDDPowerPositive Digital Supply output for decoupling purposes
10VSSPowerGround (0V)
11XC2Analog OutputCrystal Pin 2
12XC1Analog InputCrystal Pin 1
13VDD_PAPower OutputPower Supply (+1.8V) to Power Amplifier
14ANT1RFAntenna interface 1
15ANT2RFAntenna interface 2
16VSS_PAPowerGround (0V)
17VDDPowerPower Supply (+3V DC)
18VSSPowerGround (0V)
19IREFAnalog InputReference current
20VSSPowerGround (0V)
21VDDPowerPower Supply (+3V DC)
22VSSPowerGround (0V)
23PWR_UPDigital InputPower Up
24VDDPowerPower Supply (+3V DC)
3,1$66,*10(17
CE
DR2
CLK2
DOUT2
CS
DR1
1
2
3
4
5
6
Table 3 nRF2401 pin function
VDDVSS
PWR_UP
24
2322
VDD
21
Q5)
QFN24 5x5
VSS
IREF
2019
18
17
16
15
14
13
VSS
VDD
VSS_PA
ANT2
ANT1
VDD_PA
CLK1
DATA
987
DVDD
VSS
10
1112
XC2XC1
Figure 2. nRF2401 pin assignment (top view) for a QFN24 5x5 package.
Page 57
ASAHI KASEI [AK5384]
MS0225-E-00 2003/05
- 1 -
GENERAL DESCRIPTION
The AK5384 is a 4-channel A/D Converter with wide sampling rate of 8kHz ∼ 96kHz and is suitable for
Multi-channel audio system. The AK5384 achieves high accuracy and low cost by using Enhanced dual
bit ∆Σ techniques. The AK5384 supports master mode and TDM format. Therefore, the AK5384 is
suitable for multi-channel audio system.
FEATURES
ο 4-Channel ∆Σ ADC
ο
Differential Inputs
ο
Digital HPF for DC-Offset Cancel
ο S/(N+D): 100dB@5V for 48kHz
ο
DR: 107dB@5V for 48kHz
ο
S/N: 107dB@5V for 48kHz
ο Sampling Rate Ranging from 8kHz to 96kHz
ο
Master Clock:
256fs/384fs/512fs/768fs (∼ 48kHz)
256fs/384fs (∼ 96kHz)
ο
TTL Digital Input Level
ο
Output format: 24bit MSB justified, I2S or TDM
ο
Cascade TDM Interface
ο
Master & Slave Mode
ο
Overflow Flag
ο Power Supply: 4.75 to 5.25V
ο
Power Supply for output buffer: 3.0 to 5.25V
ο Ta = −40 ∼ 85°C
ο
28pin VSOP
∆
Σ
Modulator
LIN1-
LRCK
BICK
SDTO1
VCOM
Clock Divider
A
VSS
AVDD
Decimation
Filter
Audio
Interface
Voltage Reference
D
VSS
DVDD
PDN
LIN1+
∆
Σ
Modulator
RIN1-
Decimation
Filter
RIN1+
∆
Σ
Modulator
LIN2-
Decimation
Filter
LIN2+
∆
Σ
Modulator
RIN2-
Decimation
Filter
RIN2+
SDTO2
DIF
TDM0
M/S
MCLK
CKS
TDMIN
TDM1
TVDD
OVF
107dB 24-Bit 96kHz 4-
Channel ADC
AK5384
56
MS-A5001
Page 58
ASAHI KASEI [AK5384]
MS0225-E-00 2003/05
- 2 -
ν
Ordering Guide
AK5384VF −40 ∼ +85°C 28pin VSOP (0.65mm pitch)
AKD5384 Evaluation Board for AK5384
ν
Pin Layout
RIN2+
RIN2-
AVSS
AVDD
LIN2+
LIN2-
TEST
VCOM
TDM1
TDM0
TDMIN
MCLK
OVF
DIF
Top View
8
7
6
5
4
3
2
1
21
22
23
24
25
26
27
28
RIN1+
RIN1-
PDN
CKS
M/S
LIN1-
LIN1+
9
10
11
12
13
14
18
19
20
TVDD
15
16
17
LRCK
BICK
SDTO2
DVDD
DVSS
SDTO1
57
MS-A5001
Page 59
ASAHI KASEI [AK5384]
MS0225-E-00 2003/05
- 3 -
PIN/FUNCTION
No.
Pin Name I/O Function
1 LIN2+ I ADC2 Lch Positive Analog Input Pin
2
LIN2−
I ADC2 Lch Negative Analog Input Pin
3 RIN2+ I ADC2 Rch Positive Analog Input Pin
4
RIN2−
I ADC2 Rch Negative Analog Input Pin
5 TEST I Test Pin (Connected to AVSS)
6 VCOM O
Common Voltage Output Pin, AVDD/2
Normally connected to AVSS with a 0.1µF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2µF.
7 AVSS - Analog Ground Pin
8 AVDD -
12 TDMIN I TDM Data Input Pin
13 MCLK I Master Clock Input Pin
14 OVF O
Analog Input Overflow Detect Pin
This pin goes to “H” if one of four analog inputs overflows.
15 LRCK I/O
Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
16 BICK I/O
Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
17 SDTO2 O
ADC2 Audio Serial Data Output Pin
“L” Output at Power-down mode.
18 SDTO1 O
ADC1 Audio Serial Data Output Pin
“L” Output at Power-down mode.
19 TVDD -
Output Buffer Power Supply Pin, 3.0 ∼ 5.25V
20 DVDD -
Digital Power Supply Pin, 4.75 ∼ 5.25V
21 DVSS - Digital Ground Pin
22 PDN I
Power-Down Mode Pin
When “L”, the circuit is in power-down mode.
The AK5384 should always be reset upon power-up.
23 CKS I
Master Clock Select Pin
“L” : 256fs, “H” : 512fs
This pin is enabled in Master Mode.
24 M/S I
Master / Slave Mode Pin
“L” : Slave Mode, “H” : Master Mode
25
RIN1−
I ADC1 Rch Negative Analog Input Pin
26 RIN1+ I ADC1 Rch Positive Analog Input Pin
27
LIN1−
I ADC1 Lch Negative Analog Input Pin
28 LIN1+ I ADC1 Lch Positive Analog Input Pin
Note: All digital input pins should not be left floating.
58
MS-A5001
Page 60
ASAHI KASEI [AK4382A]
MS0071-E-01 2002/2
- 1 -
GENERAL DESCRIPTION
The AK4382A offers the perfect mix for cost and performance based audio systems. Using AKM's multi
bit architecture for its modulator the AK4382A delivers a wide dynamic range while preserving linearity
for improved THD+N performance. The AK4382A has full differential SCF outputs, removing the need
for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit
word length and 192kHz sampling rate make this part ideal for a wide range of applications including
DVD-Audio. The AK4382A is offered in a space saving 16pin TSSOP package.
FEATURES
ο
Sampling Rate Ranging from 8kHz to 192kHz
ο
128 times Oversampling (Normal Speed Mode)
ο
64 times Oversampling (Double Speed Mode)
ο 32 times Oversampling (Quad Speed Mode)
ο
24-Bit 8 times FIR Digital Filter
ο
On chip SCF
ο Digital de-emphasis for 32k, 44.1k and 48kHz sampling
ο
Soft mute
ο
Digital Attenuator (256 steps)
ο I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
ο
Master clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode)
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power-Down Mode Pin
When at “L”, the AK4382A is in the power-down mode and is held in reset.
The AK4382A should always be reset upon power-up.
6 CSN I Chip Select Pin
7 CCLK I Control Data Input Pin
8 CDTI I Control Data Input Pin in serial mode
9 AOUTR- O Rch Negative Analog Output Pin
10 AOUTR+ O Rch Positive Analog Output Pin
11 AOUTL- O Lch Negative Analog Output Pin
12 AOUTL+ O Lch Positive Analog Output Pin
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 DZFR O Rch Data Zero Input Detect Pin
16 DZFL O Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
60
MS-A5001
Page 62
61
MS-A5001
Datasheet No – PD97381
March 5, 2009
IRS20957S
Protected Digital Audio Driver
Features
•Floating PWM input enables easy half bridge
implementation
•Programmable bidirectional over-current protection with
self-reset function
•Programmable preset dead-time for improved THD
performances
• High noise immunity
• ±100V ratings deliver up to 500W in output power
• 3.3 V/ 5 V logic compatible input
• Operates up to 800kHz
Typical Applications
• Home theatre systems
• Mini component stereo systems
• Powered speaker systems
• General purpose audio power amplifiers
Product Summary
Topology Half-Bridge
V
OFFSET (max)
IO+ & I
Selectable deadtime 15/25/35/80ns
Ton & toff (typical) 95ns & 80ns
OC protection delay 500ns (max)
Shutdown
propagation delay
(typical) 1.0 A & 1.2 A
O-
+/- 100 V
250ns (max)
Package
Typical Connection Diagram
Note: Please refer to Lead Assignments for correct pin configuration. This diagram shows
electrical connections only.
, VCCDrain-Source Voltage, Power Supply Voltage25V
V
GSS
, VIGate-Source Voltage, V
IN
8V
ID, I
O
Drain/Output Current - Continuous0.22A
0.5
P
D
Maximum Power Dissipation0.35W
TJ,T
STG
Operating and Storage Temperature Range-55 to 150°C
ESDElectrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6.0 kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient 357°C/W
25 V, 0.22 A continuous, 0.5 A Peak.
R
DS(ON)
= 5 Ω @ V
GS
= 2.7 V
R
DS(ON)
= 4 Ω @ V
GS
= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.06V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors with one DMOS
FET.
This N-Channel logic level enhancement mode field effect
transistor is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for digital transistors. Since
bias resistors are not required, this one N-channel FET can
replace several different digital transistors, with different bias
resistor values.