Jameco Electronics Rabbit 3000, Rabbit 2000 User Manual
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Rabbit 3000® Microprocessor
User’s Manual
019–0108 • 040731–O
Rabbit 3000 Microprocessor User’s Manual
Part Number 019-0108 • 040731–O • Printed in U .S.A.
©2002–2004 Rabbit Semiconductor • All rights reserved.
Rabbit Semiconductor reserves the right to make changes and
improvements to its products without providing n otice.
T r ade mark s
Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semi conduct or.
Dynamic C is a registered trademark of Z-World, Inc.
Rabbit Semiconductor
2932 Spafford S treet
Davis, California 95616-6800
USA
Telephone: (530) 757-8400
Fax: (530) 757-8402
www.rabbitsemiconductor.com
Rabbit 3000 Microprocessor
TABLE OF CONTENTS
Chapter 1. Introduction 1
1.1 Features and Specifications Rabbit 3000..............................................................................................2
1.2 Summary of Rabbit 3000 Advantages..................................................................................................6
1.3 Differences Rabbit 3000 vs. Rabbit 2000.............................................................................................7
Chapter 2. Rabbit 3000 Design Features 9
2.1 The Rabbit 8-bit Processor vs. Other Processors................................................................................10
2.2 Overview of On-Chip Peripherals and Features.................................................................................11
2.2.1 5 V Tolerant Inputs .............................. ...... .................................. ..... ...... ...................................11
2.2.2 Serial Ports .................................................................................................................................11
2.2.3 System Clock .............................................................................................................................12
2.2.4 32.768 kHz Oscillator Input .......................................................................................................12
2.2.5 Parallel I/O .................................................................................................................................13
2.2.6 Slave Port ...................................................................................................................................14
2.2.7 Auxiliary I/O Bus .......................................................................................................................15
2.2.8 Timers ........................................................................................................................................15
2.2.9 Input Capture Channels ..............................................................................................................16
2.2.10 Quadrature Encoder Inputs ......................................................................................................17
2.2.11 Pulse Width Modulation Outputs .............................................................................................17
2.2.12 Spread Spectrum Clock ............................................................................................................18
2.2.13 Separate Core and I/O Power Pins ...........................................................................................18
2.3 Design Standards................................................................................................................................18
2.3.1 Programming Port ......................................................................................................................18
2.3.2 Standard BIOS ...........................................................................................................................19
2.4 Dynamic C Support for the Rabbit.....................................................................................................19
Chapter 3. Details on Rabbit Microprocessor Features 21
3.1 Processor Registers.............................................................................................................................21
3.2 Memory Mapping...............................................................................................................................23
3.2.1 Extended Code Space .................................................................................................................26
3.2.2 Separate I and D Space - Extending Data Memory ...................................................................27
3.2.3 Using the Stack Segment for Data Storage ................................................................................29
3.2.4 Practical Memory Considerations ..............................................................................................30
3.3 Instruction Set Outline........................................................................................................................32
3.3.1 Load Immediate Data to a Register ............................................................................................33
3.3.2 Load or Store Data from or to a Constant Address ....................................................................33
3.3.3 Load or Store Data Using an Index Register .............................................................................34
3.3.4 Register-to-Register Move .........................................................................................................35
3.3.5 Register Exchanges ....................................................................................................................35
3.3.6 Push and Pop Instructions ..........................................................................................................36
3.3.7 16-bit Arithmetic and Logical Ops ............................................................................................36
3.3.8 Input/Output Instructions ...........................................................................................................39
3.4 How to Do It in Assembly Language—Tips and Tricks....................................................................40
3.4.1 Zero HL in 4 Clocks ...................................................................................................................40
3.4.2 Exchanges Not Directly Implemented .......................................................................................40
3.4.3 Manipulation of Boolean Variables ...........................................................................................40
3.4.4 Comparisons of Integers ............................................................................................................41
3.4.5 Atomic Moves from Memory to I/O Space ...............................................................................43
User’s Manual
3.5 Interrupt Structure..............................................................................................................................44
3.5.1 Interrupt Priority ........................................................................................................................ 44
3.5.2 Multiple External Interrupting Devices .....................................................................................46
3.5.3 Privileged Instructions, Critical Sections and Semaphores ....................................................... 46
3.5.4 Critical Sections ......................................................................................................................... 47
3.5.5 Semaphores Using Bit B,(HL) ..................................................................................................47
3.5.6 Computed Long Calls and Jumps ..............................................................................................48
Chapter 4. Rabbit Capabilities 49
4.1 Precisely Timed Output Pulses ..........................................................................................................49
4.1.1 Pulse Width Modulation to Reduce Relay Power .....................................................................50
4.2 Open-Drain Outputs Used for Key Scan............................................................................................51
4.3 Cold Boot...........................................................................................................................................52
4.4 The Slave Port....................................................................................................................................53
4.4.1 Slave Rabbit As A Protocol UART ...........................................................................................54
Chapter 5. Pin Assignments and Functions 55
5.1 LQFP Package....................................................................................................................................56
5.1.1 Pinout .........................................................................................................................................56
5.1.2 Mechanical Dimensions and Land Pattern ................................................................................57
5.2 Ball Grid Array Package...................................................................................................................59
5.2.1 Pinout .........................................................................................................................................59
5.2.2 Mechanical Dimensions and Land Pattern ................................................................................60
5.3 Rabbit Pin Descriptions......................................................................................................................62
5.4 Bus Timing.........................................................................................................................................64
5.5 Description of Pins with Alternate Functions....................................................................................65
5.6 DC Characteristics..............................................................................................................................68
5.7 I/O Buffer Sourcing and Sinking Limit..............................................................................................69
Chapter 6. Rabbit Internal I/O Registers 71
6.1 Default Values for all the Peripheral Contro l Registers..................... ................................................73
Chapter 7. Miscellaneous Functions 79
7.1 Processor Identification......................................................................................................................79
7.2 Rabbit Oscillators and Clocks............................................................................................................80
7.3 Clock Doubler....................................................................................................................................83
7.4 Clock Spectrum Spreader...................................................................................................................86
7.5 Chip Select Options for Low Power ..................................................................................................87
7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN..........................................................................90
7.7 Time/Date Clock (Real-Time Clock).................................................................................................91
7.8 Watchdog Timer.................................................................................................................................93
7.9 System Reset......................................................................................................................................95
7.10 Rabbit Interrupt Structure.................................................................................................................97
7.10.1 External Interrupts ...................................................................................................................99
7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 ..........................................................100
7.11 Bootstrap Operation.......................................................................................................................101
7.12 Pulse Width Modulator ....................................... ...... .....................................................................103
7.13 Input Capture..................................................................................................................................105
7.14 Quadrature Decoder.......................................................................................................................110
Chapter 8. Memory Interface and Mapping 115
8.1 Interface for Static Memory Chips...................................................................................................115
8.2 Memory Mapping Overview............................................................................................................117
8.3 Memory-Mapping Unit....................................................................................................................117
8.4 Memory Interface Unit.....................................................................................................................119
Rabbit 3000 Microprocessor
8.5 Memory Bank Control Registers......................................................................................................120
8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable) .....................................................121
8.6 Allocation of Extended Code and Data............................................................................................123
8.7 Instruction and Data Space Support..................................................................................................124
8.8 How the Compiler Compiles to Memory .........................................................................................127
Chapter 9. Parallel Ports 129
9.1 Parallel Port A...................................................................................................................................130
9.2 Parallel Port B...................................................................................................................................131
9.3 Parallel Port C...................................................................................................................................132
9.4 Parallel Port D...................................................................................................................................133
9.5 Parallel Port E...................................................................................................................................137
9.6 Parallel Port F ...................................................................................................................................140
9.6.1 Using Parallel Port A and Parallel Port F ................................................................................141
9.7 Parallel Port G...................................................................................................................................143
Chapter 10. I/O Bank Control Registers 145
Chapter 1 1. Timers 149
11.1 Timer A...........................................................................................................................................150
11.1.1 Timer A I/O Registers ............................................................................................................151
11.1.2 Practical Use of Timer A .......................................................................................................155
11.2 Timer B...........................................................................................................................................156
11.2.1 Using Timer B ........................................................................................................................159
Chapter 12. Rabbit Serial Ports 161
12.1 Serial Port Register Layout..................................................... ...... ...... ............................................164
12.2 Serial Port Registers.......................................... ..... .........................................................................166
12.3 Serial Port Interrupt ............................................... ...... ...... .............................................................179
12.4 Transmit Serial Data Timing ..........................................................................................................180
12.5 Receive Serial Data Timing............................................................................................................181
12.6 Clocked Serial Ports........................................................................................................................182
12.7 Clocked Serial Timing....................................................................................................................185
12.7.1 Clocked Serial Timing With Internal Clock ..........................................................................185
12.7.2 Clocked Serial Timing with External Clock ..........................................................................185
12.8 Synchronous Communications on Ports E and F............................................................................187
12.9 Serial Port Software Suggestions....................................................................................................192
12.9.1 Controlling an RS-485 Driver and Receiver ..........................................................................193
12.9.2 Transmitting Dummy Characters ...........................................................................................193
12.9.3 Transmitting and Detecting a Break ......................................................................................194
12.9.4 Using A Serial Port to Generate a Periodic Interrupt .............................................................194
12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes .......................................194
12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters ...............................................................195
12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters ...............................................................195
12.9.8 Supporting 9th Bit Communication Protocols .......................................................................196
12.9.9 Rabbit-Only Master/Slave Protocol .......................................................................................196
12.9.10 Data Framing/Modbus .............................................................................................. ...........196
Chapter 13. Rabbit Slave Port 199
13.1 Hardware Design of Slave Port Interconnection ............................................................................204
13.2 Slave Port Registers........................................................................................................................204
13.3 Applications and Communications Proto cols for Slaves................................................................206
13.3.1 Slave Applications .................................................................................................................206
13.3.2 Master-Slave Messaging Protocol .........................................................................................207
User’s Manual
Chapter 14. Rabbit 3000 Clocks 209
14.1 Low-Power Design.........................................................................................................................210
Chapter 15. EMI Control 211
15.1 Power Supply Connections and Board Layout ..............................................................................2 12
15.2 Using the Clock Spectrum Spreader..............................................................................................212
Chapter 16. AC Timing Specifications 215
16.1 Memory Access Time.................................................................................................................... 215
16.2 I/O Access Time.............................................................................................................................223
16.3 Further Discussion of Bus and Clock Timing................................................................................225
16.4 Maximum Clock Speeds................................................................................................................227
16.5 Power and Current Consumption...................................................................................................2 29
16.6 Current Consumption Mechanisms..................... .................................. ...... ...... .............................232
16.7 Sleepy Mode Current Consumption...............................................................................................233
16.8 Memory Current Consumption ......................................................................................................234
16.9 Battery-Backed Clock Current Consumption ................................................................................235
16.10 Reduced-Power External Main Oscillator....................................................................................236
Chapter 17. Rabbit BIOS and Virtual Driver 237
17.1 The BIOS........................................................................................................................................237
17.1.1 BIOS Services .......................................................................................................................237
17.1.2 BIOS Assumptions ................................................................................................................238
17.2 Virtual Driver.................................................................................................................................238
17.2.1 Periodic Interrupt ...................................................................................................................238
17.2.2 Watchdog Timer Support ......................................................................................................238
Chapter 18. Other Rabbit Software 241
18.1 Power Management Support..........................................................................................................241
18.2 Reading and Writing I/O Registers................................................................................................ 242
18.2.1 Using Assembly Language ....................................................................................................242
18.2.2 Using Library Functions ........................................................................................................242
18.3 Shadow Registers...................................................... ...... ...............................................................243
18.3.1 Updating Shadow Registers ..................................................................................................243
18.3.2 Interrupt While Updating Registers .......................................................................................243
18.3.3 Write-only Registers Without Shadow Registers ..................................................................244
18.4 Timer and Clock Usage..................................................................................................................244
Chapter 19. Rabbit Instructions 247
19.1 Load Immediate Data.....................................................................................................................250
19.2 Load & Store to Immediate Address..............................................................................................250
19.3 8-bit Indexed Load and Store.......................................... ...............................................................250
19.4 16-bit Indexed Loads and Stores....................................................................................................250
19.5 16-bit Load and Store 20-bit Address ............................................................................................251
19.6 Register to Register Moves............................................................................................................251
19.7 Exchange Instructions........ ..... ...... .................................. ..... ...... ....................................................252
19.8 Stack Manipulation Instructions.....................................................................................................252
19.9 16-bit Arithmetic and Logical Ops.................................................................................................252
19.10 8-bit Arithmetic and Logical Ops.................................................................................................2 53
19.11 8-bit Bit Set, Reset and Test.........................................................................................................254
19.12 8-bit Increment and Decrement....................................................................................................254
19.13 8-bit Fast A Register Operations..................................................................................................255
19.14 8-bit Shifts and Rotates................................................................................................................255
19.15 Instruction Prefixes ......................................................................................................................256
Rabbit 3000 Microprocessor
19.16 Block Move Instructions...............................................................................................................256
19.17 Control Instructions - Jumps and Calls.........................................................................................257
19.18 Miscellaneous Instructions ...........................................................................................................257
19.19 Privileged Instructions..................................................................................................................258
Chapter 20. Differences Rabbit vs. Z80/Z180 Instructions 259
Chapter 21. Instructions in Alphabetical Order With Binary Encoding 261
Appendix A. The Rabbit Programming Port 269
A.1 Use of the Programming Port as a Diagnostic/Setup Port................................... ...... ...... ................270
A.2 Alternate Programming Port............................................................................................................270
A.3 Suggested Rabbit Crystal Frequencies.............................................................................................271
Appendix B. Rabbit 3000 Revisions 273
B.1 Discussion of Fixes and Improvements ...........................................................................................276
B.1.1 Rabbit Internal I/O Registers ...................................................................................................277
B.1.2 Peripheral and ISR Address ....................................................................................................280
B.1.3 Revision-Level ID Register .....................................................................................................282
B.1.4 System/User Mode ..................................................................................................................283
B.1.5 Memory Protection ..................................................................................................................284
B.1.6 Stack Protection .......................................................................................................................289
B.1.7 RAM Segment Relocation .......................................................................................................291
B.1.8 Secondary Watchdog Timer ....................................................................................................292
B.1.9 New Opcodes ..........................................................................................................................293
B.1.10 Expanded I/O Memory Addressing .......................................................................................295
B.1.11 External I/O Improvements ...................................................................................................296
B.1.12 Short Chip Select Timing for Writes .....................................................................................297
B.1.13 Pulse Width Modulator Improvements .................................................................................311
B.1.14 Quadrature Decoder Improvements ......................................................................................314
B.2 Pins with Alternate Functions..........................................................................................................316
Appendix C. System/User Mode 317
C.1 System/User Mode Opcodes............................................................................................................318
C.2 System/User Mode Registers...........................................................................................................319
C.3 Interrupts..........................................................................................................................................321
C.3.1 Peripheral Interrupt Prioritization ...........................................................................................322
C.4 Using the System/User Mode...........................................................................................................324
C.4.1 Memory Protection Only .........................................................................................................324
C.4.2 Mixed System/User Mode Operation ......................................................................................325
C.4.3 Complete Operating System ....................................................................................................326
Appendix D. Rabbit 3000A Internal I/O Registers 327
Notice to Users 335
Index 337
User’s Manual
Rabbit 3000 Microprocessor
1. INTRODUCTION
Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in
small and medium-scale controllers. The first microprocessor was the Rabbit 2000. The
second microprocessor, now available, is the Rabbit 3000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small
controllers. The Rabbit shares a similar architecture and a high degree of compatibility
with these microprocessors, but it is a vast improvement.
The Rabbit 3000 has been designed in close cooperation with Z-World, Inc., a long-time
manufacturer of low-cost single-board computers. Z-World’s products are supported by an
innovative C-language development system (Dynamic C). Z-World is providing the software development tools for the Rabbit 3000.
The Rabbit 3000 is easy to use. Hardware and software interfaces are as uncluttered and
are as foolproof as possible. The Rabbit has outstanding computation speed for a microprocessor with an 8-bit bus. This is because the Z80-derived instruction set is very compact, and the timing of the memory interface allows higher clock speeds for a given
memory speed.
Microprocessor hardware and software development is easy for Rabbit users. In-circuit
emulators are not needed and will not be missed by the Rabbit developer. Software development is accomplished by connecting a simple interface cable from a PC serial port to the
Rabbit-based target system or by performing software development and debugging over a
network or the Internet using interfaces and tools provided by Rabbit Semiconductor.
User’s Manual 1
1.1 Features and Specifications Rabbit 3000
• 128-pin LQFP package. Operating voltage 1.8 V to 3.6 V . Clock speed to 54+ MHz. All
specifications are given for both industrial and commercial temperature and voltage
ranges. Rabbit microprocessors are low-cost.
• Industrial specifications are for 3.3 V ±10% and a temperature range from -40°C to
+85°C. Modified commercial specifications are for a voltage variation of 5% and a
temperature range from -40°C to 70°C.
• 1-megabyte code-data space allows C programs with 50,000+ lines of code. The
extended Z80-style instruction set is C-friendly, with short and fast opcodes for the
most important C operations.
• Four levels of interrupt priority make a fast interrupt response practical for critical
applications. The maximum time to the first instruction of an interrupt routine is about
0.5 µs at a clock speed of 50 MHz.
• Access to I/O devices is accomplished by using memory access instructions with an I/O
prefix. Access to I/O devices is thus faster and easier compared to processors with a
distinct and narrow I/O instruction set. As an option the auxiliary I/O bus can be
enabled to use separate pins for address and data, allowing the I/O bus to have a greater
physical extent with less EMI and less conflict with the requirements of the fast memory bus.(Further described below.)
• Hardware design is simple. Up to six static memory chips (such as RAM and flash
memory) connect directly to the microprocessor with no glue logic. A memory-access
time of 55 ns suffices to support up to a 30 MHz clock with no wait states; with a 30 ns
memory-access time, a clock speed of up to 50 MHz is possible with no wait states.
Most I/O devices may be connected without glue logic.
The memory read cycle is two clocks long. The write cycle is 3 clocks long. A clean
memory and I/O cycle completely avoid the possibility of bus fights. Peripheral I/O
devices can usually be interfaced in a glueless fashion using the common /IORD and
/IOWR strobes in addition to the user-configurable IO strobes on Parallel Port E. The
Parallel Port E pins can be configured as I/O read, write, read/write, or c hip select when
they are used as I/O strobes.
• EMI reduction features reduce EMI levels by as much as 25 dB compared to other similar microprocessors. Separate power pins for the on-chip I/O buffers prevent high-frequency noise generated in the processor core from propagating to the signal output
pins. A built-in clock spectrum spreader reduces electromagnetic interference and facilitates passing EMI tests to prove compliance with government regulatory requirements.
As a consequence, the designer of a Rabbit-3000-based system can be assured of passing FCC or CE EMI tests as long as minimal design precautions are followed.
• The Rabbit may be cold-booted via a serial port or the parallel access slave port. This
means that flash program memory may be soldered in unprogrammed, and can be
reprogrammed at any time without any assumption of an existing program or BIOS.
2 Rabbit 3000 Microprocessor
A Rabbit that is slaved to a master processor can operate entirely with volatile RAM,
depending on the master for a cold program boot.
• There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer synchronized, which permits precisely timed edges and pulses to be generated under combined hardware and software control. Pulse-width modulation outputs are implemented
in addition to the timer-synchronization feature (see below).
• Four pulse width modulated (PWM) outputs are implemented by special hardware. The
repetition frequency and the duty cycle c an be vari ed over a wide range . The resolution
of the duty cycle is 1 part in 1024.
• There are six serial ports. All six serial ports can operate asynchronously in a variety of
commonly used operating modes. Four of the six ports (designated A, B, C, D) support
clocked serial communications suitab le for interfacing with “SPI” devices and various
similar devices such as A/D converters and me mori es t ha t use a cl oc ked ser ial pr ot oc ol .
Two of the ports, E and F, support HDLC/SDLC sy nch ro no us com mun ica ti on . Th es e
ports have a 4-byte FIFO and can operate at a high data rate. Ports E and F also have a
digital phase-locked loop for clock recovery, and support popular data-encoding methods. High data rates are supported by all six serial ports. The asynchronous ports also
support the 9th bit networ k schem e as well as infr ared transm issi on usin g the IRD A protocol. The IRDA protocol is also supported in SDLC format by the two ports that support SDLC.
• A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a
master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of
communication. Independent strobes and interrupts are used to control the slave port in
both directions. Only a Rabbit and a RAM chip are needed to construct a complete
slave system, if the clock and reset control are shared with the master processor
• There is an option to enable an auxiliary I/O bus that is separate from the memory bus.
The auxiliary I/O bus toggles only on I/O instructions. It reduces EMI and speeds the
operation of the memory bus, which only has to connect to memory chips when the
auxiliary I/O bus is used to connect I/O devices. This important feature makes memory
design easy and allows a more relaxed approach to interfacing I/O devices.
• The built-in battery-backable time/date clock uses an external 32.768 kHz crystal oscillator. The suggested model circuit for the external oscillator utilizes a single “tiny
logic” active component. The time/date clock can be used to provide periodic interrupts
every 488 µs. Typical battery current consumption is about 3 µA.
• Numerous timers and counters can be used to generate interrupts, baud rate clocks, and
timing for pulse generation.
• T wo input-capture channels can be used to measure the width of pulses or to record the
times at which a series of events take place. Each capture channel has a 16-bit counter
and can take input from one or two pins selected from any of 16 pins.
• Two quadrature decoder units accept input from incremental optical shaft encoders.
These units can be used to track the motion of a rotating shaft or similar device.
User’s Manual 3
• A built-in clock doubler allows ½-frequency crystals to be used.
• The built-in main clock oscillator uses an external crystal or a c eramic resonator. Typical
crystal or resonator frequencies are in the range of 1.8 MHz to 30 MHz. Since precision
timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator
with ½ percent error is generally satisfactory. The clock can be doubled or divided down
to modify speed and power dynamically . The I/O clock, which clocks the serial ports, is
divided separately so as not to affect baud rates and timers when the processor clock is
divided or multiplied. For ultra low power operation, the processor clock can be driven
from the separate 32.768 kHz oscillator and the main oscillator can be powered down.
This allows the processor to operate at approximately between 20 and 100 µA and still
execute instructions at the rate of up to 10,000 instructions per second. The 32.768 kHz
clock can also be divided by 2, 4, 8 or 16 to reduce power . This “sleepy mode” is a powerful alternative to sleep modes of operation used by other processors.
• Processor current requirement is approximately 65 mA at 30 MHz and 3.3 V. The current is proportional to voltage and clock speed—at 1.8 V and 3.84 MHz the current
would be about 5 mA, and at 1 MHz the current is reduced to about 1 mA.
• To allow extreme low power operation there are options to reduce the duty cycle of
memories when running at low clock speeds by only enabling the chip select for a brief
period, long enough to complete a read. This greatly reduces the power used by flash
memory when operating at low clock speeds.
• The excellent floating-point performance is due to a tightly coded library and powerful
processing capability. F or example, a 50 MHz clock takes 7 µs for a floating add, 7 µs
for a multiply, and 20 µs for a square root. In comparison, a 386EX processor running
with an 8-bit bus at 25 MHz and using Borland C is about 20 times slower.
• There is a built-in watchdog timer.
• The standard 10-pin programming port eliminates the need for in-circuit emulators. A
very simple 10-pin connector can be used to download and debug software using
Z-W orld’ s Dynamic C and a simp le connection to a PC serial port. The incremental cost
of the programming port is extremely small.
Figure 1-1 shows a block diagram of the Rabbit.
4 Rabbit 3000 Microprocessor
/RESET
RESOUT
/IOWR
/IORD
/BUFEN
SMODE0
SMODE1
STATUS
/WDTOUT
CLK
D[7:0]
A[19:0]
XTALA1
XTALA2
CLK32K
ID[7:0]
IA[5:0]
I[7:0]
INT0A, INT1A
INT0B, INT1B
Data
Buffer
Address
Buffer
Spectrum
Spreader
Fast
Oscillator
32.768 kHz
Clock Input
External I/O
Chip Interface
External
Interrupts
Memory
Management/
Control
Clock
Doubler
Global Power
Save & Clock
Distribution
Timer A
Timer B
Real-Time
Clock
Watchdog
Timer
Periodic
Interrupt
External Interface
CPU
(8 bits)
ADDRESS BUS
(8 bits)
DATA BUS
Memory Chip
Interface
Parallel Ports
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Serial Port A
Asynch
Synch
Serial
Serial
Asynch
Synch
Bootstrap
Bootstrap
Asynch Serial IrDA
IrDA Bootstrap
Serial Ports
B,C,D
Asynch
Synch
Serial
Serial
Asynch Serial IrDA
Serial Ports
E, F
Asynch
HDLC
Serial
SDLC
Asynch Serial IrDA
HDLC/SDLC IrDA
Pulse Width
Modulation
Quadrature
Decoder
Input
Capture
Slave Port
Slave Interface
Bootstrap Interface
/CS2, /CS1, /CS0
/OE1, /OE0
/WE1, /WE0
PA [7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7:0]
PG[7:0]
TXA, RXA, CLKA,
ATXA, ARXA
TXB, RXB, CLKB,
ATXB, ARXB
TXC, RXC, CLKC
TXD, RXD, CLKD
TXE, RXE
TCLKE, RCLKE
TXF, RXF
TCLKF, RCLKF
PWM[3:0]
QD1A, QD1B
QD2A, QD2B
AQD1A, AQD1B
AQD2A, AQD2B
PC[7,5,3,1]
PD[7,5,3,1]
PF[7,5,3,1]
PG[7,5,3,1]
SD[7:0]
SA[1:0],
/SCS, /SRD, /SWR,
/SLAVEATTN
Figure 1-1. Rabbit 3000 Block Diagram
User’s Manual 5
1.2 Summary of Rabbit 3000 Advantages
• The glueless architecture makes it is easy to design the hardware system.
• There are a lot of serial ports and they can communicate very fast.
• Precision pulse and edge generation is a standard feature.
• EMI is at extremely low levels.
• Interrupts can have multiple priorities.
• Processor speed and power consumption are under program control.
• The ultra low power mode can perform computations and execute logical tests since the
processor continues to execute, albeit at 32 kHz or even as slow as 2 kHz.
• The Rabbit may be used to create an intelligent peripheral or a slave processor. For
example, protocol stacks can be off loaded to a Rabbit slave. The master can be any
processor.
• The Rabbit can be cold-booted so unprogrammed flash memory can be soldered in
place.
• You can write serious software, be it 1,000 or 50,000 lines of C code. The tools are
there and they are low in cost.
• If you know the Z80 or Z180, you know most of the Rabbit.
• A simple 10-pin programming interface replaces in-circuit emulators and PROM pro-
grammers.
• The battery-backable time/date clock is included.
• The standard Rabbit chip is made to industrial temperature and voltage specifications.
• The Rabbit 3000 is backed by extensive software development tools and libraries, espe-
cially in the area of networking and embedded Internet.
6 Rabbit 3000 Microprocessor
1.3 Differences Rabbit 3000 vs. Rabbit 2000
For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rabbit 3000 is contrasted with the Rabbit 2000 in the table below.
Feature Rabbit 3000 Rabbit 2000
Maximum clock speed 54 MHz 30 MHz
Maximum crystal frequency main oscillator (may be
doubled internally)
32.768 kHz crystal oscillator External Internal
Maximum operating voltage 3.6 V 5.5 V
Maximum I/O input voltage 5.5 V 5.5 V
Current consumption 2 mA/MHz @ 3.3 V 4 mA/MHz @5 V
Number of package pins 128 100
16 × 16 × 1.5 mm LQFP
Size of package
Spacing between package pins
Separate power and ground for I/O buffers (EMI
reduction)
Clock Spectrum Spreader (EMI reduction) Yes
Clock Modes 1x, 2x, /2, /3, /4, /6, /8 1x, 2x, /4, /8
0.4 mm (16 mils) LQFP
30 MHz 32 MHz
10 × 10 × 1.2 mm
TFBGA
0.8 mm TFBG A
Yes No
24 × 18 × 3 mm PQFP
0.65 mm (26 mils) PQFP
Rabbit 2000B and
Rabbit 2000C versions.
Sleepy (32 kHz)
Power Down Modes
Low Power Memory Control (Chip Select)
Extended memory timing for high freq. operation Yes No
Number of 8-bit I/O ports 7 5
Auxiliary I/O Data/Address bus Yes None
Number of serial ports 6 4
Serial ports capable of SPI/clocked serial 4 (A, B, C, D) 2 (A, B)
Serial ports capable of SDLC/HDLC 2 (E, F) None
Asynch serial ports with support for IrDA
communications
User’s Manual 7
Ultra-Sleepy
(16, 8, 2 kHz)
Short CS (CLK /4 /6 /8)
Self Timed
(32,16,8,2 kHz)
6None
Sleepy (32 kHz)
None
Feature Rabbit 3000 Rabbit 2000
Serial ports with support for SDLC/HDLC IrDA
communications
2None
Maximum asynchronous baud rate clock speed/8 clock speed/32
Input capture unit 2 None
8 Rabbit 3000 Microprocessor
2. RABBIT 3000 DESIGN FEATURES
The Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly
identical to the immediate predecessor processor, the Rabbit 2000. Both the Rabbit 3000
and the Rabbit 2000 follow in broad outline the instruction set and the register layout of
the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a substantial number of new instructions. Some obsolete or redundant Z180 instructions have
been dropped to make available efficient 1-byte opcodes for important new instructions.
(see Chapter 20, “Differences Rabbit vs. Z80/Z180 Instructions,”.) The advantage of this
evolutionary approach is that users familiar with the Z80 or Z180 can immediately understand Rabbit assembly language. Existing Z80 or Z180 source code can be assembled or
compiled for the Rabbit with minimal changes.
Changing technology has made some features of the Z80/Z180 family obsolete, and these
features have been dropped in the Rabbit. For example, the Rabbit has no special support
for dynamic RAM but it has extensive support for static memory. This is because the price
of static memory has decreased to the point that it has become the preferred choice for
medium-scale embedded systems. The Rabbit has no support for DMA (direct memory
access) because most of the uses for which DMA is traditionally used do not apply to
embedded systems, or they can be accomplished better in other ways, such as fast interrupt routines, external state machines or slave processors.
Our experience in writing C compilers has revealed the shortcomings of the Z80 instruction set for executing the C language. The main problem is the lack of instructions for handling 16-bit words and for accessing data at a computed address, especially when the stack
contains that data. New instructions correct these problems.
Another problem with many 8-bit processors is their slow execution and a lack of numbercrunching ability. Good floating-point arithmetic is an important productivity feature in
smaller systems. It is easy to solve many programming problems if an adequate floatingpoint capability is available. The Rabbit’s improved instruction set provides fast floatingpoint and fast integer math capabilities.
The Rabbit supports four levels of interrupt priorities. This is an important feature that
allows the effective use of fast interrupt routines for real-time tasks.
User’s Manual 9
2.1 The Rabbit 8-bit Processor vs. Other Processors
The Rabbit 3000 processor has been designed with the objective of creating practical systems to solve real world problems in an economical fashion. A cursory comparison of the
Rabbit 3000 compared to other processors with similar capabilities may miss certain Rabbit strong points.
• The Rabbit is a processor that can be used to build a system in which EMI is nearly
absent, even at clock frequencies in excess of 40 MHz. This is due to the split power
supply, the clock doubler, the clock spectrum spreader and the PC board layout advice
(or processor core modules) that we provide. Low EMI is a huge timesaver for the
designer pressed to meet schedules and pass government EMI tests of the final product.
• Execution speed with the Rabbit is usually a pleasant surprise compared to other processors. This is due to the well-chosen and compact instruction set partnered with and
excellent compiler and library. We have many benchmarks, comparing the Rabbit to
186, 386, 8051, Z180 and ez80 families of processors that prove the point.
• The Rabbit memory bus is an exceptionally efficient and very clean design. No external
logic is required to support static memory chips. Battery-backed external memory is
supported by built-in functionality. During reduced-power slow-clock operation the
memory duty cycle can be correspondingly reduced using built-in hardware, resulting
in low power consumption by the memories.
The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles. This
has many advantages compared to a single-clock design, and on closer examination the
advantages of the single-clock system turn out to be most ly chimerical. The advantages
include: easy design to avoid bus fights, clean write cycles with solid data and address
hold times, flexibility to have mem ory output ena ble a cce ss t imes gr eate r tha n ½ of the
bus cycle, and the ability to use an asymmetric clock generated by a clock doubler. The
supposed advantage that single-clock systems have of double-speed bus operation is
not possible with real-world memories unless the memory is backed with fast-cache
RAM.
• The Rabbit 3000 operates at 3.6 V or less, but it has 5 V tolerant inputs and has a second complete bus for I/O operations that is separate from the memory bus. This second
auxiliary bus can be enabled by the application as a designer option. These features
make it easy to design systems that mix 3 V and 5 V components, and avoid the loadi ng
problems and the EMI problems that result if the memory bus is extended to connect
with many I/O devices.
• The Rabbit may be remotely programmed, including complete cold-boot, via a serial
link, Ethernet, or even via a network or the Internet using built in capabilities and/or the
RabbitLink ethernet network accessory device. These capabilities proven and inexpensive to implement.
• The Rabbit 3000 on-chip peripheral complement is huge compared to competitive processors.
10 Rabbit 3000 Microprocessor
The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data
bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a compact instruction set, its performance is as good as many 16-bit processors.
We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occasions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount
of money. Many Rabbit instructions are 1 byte long. In contrast, the minimum instruction
length on most 32-bit RISC processors is 32 bits.
2.2 Overview of On-Chip Peripherals and Features
The on-chip peripherals were chosen based on our experience as to what types of peripheral devices are most useful in small embedded systems. The major on-chip peripherals
are the serial ports, system clock, time/date oscillator, parallel I/O, slave port, motion
encoders, pulse width modulators, pulse measurement, and timers. These and other features are described below.
2.2.1 5 V Tolerant Inputs
The Rabbit 3000 operates on a voltage in the range of 1.8 V to 3.6 V, but most Rabbit 3000
input pins are 5 V tolerant. The exceptions are the power supply pins, and the oscillator
buffer pins. When a 5 V signal is applied to 5 V tolerant pins, they present a high impedance
even if the Rabbit power is off. The 5 V tolerant feature allows 5 V devices that have a
suitable switching threshold to be directly connected to the Rabbit. This includes HCT
family parts operated at 5 V that have an input threshold between 0.8 and 2 V.
NOTE: CMOS devices operated at 5 V that ha ve a t hreshold at 2.5 V are not suitabl e f or
direct connection because the Rabbit outputs do not rise above VDD, which cannot
exceed 3.6 V, and is often specified as 3.3 V. Although a CMOS input with a 2.5 V
threshold may switch at 3.3 V, it will consume excessive current and switch slowly.
In order to translate between 5 V and 3.3 V, HCT family parts powered from 5 V can be
used, and are often the best solution. There is also the “LVT” family of parts that operate
from 2.0 V to 3.3 V, but that have 5 V tolerant inputs and are available from many suppliers. True level-translating parts are available with separate 3.3 V and 5 V supply pins, but
these parts are not usually needed, and have design traps involving power sequencing.
Many charge pump chips that perform DC to DC voltage conversion at low cost have been
introduced in recent years. These are convenient for systems with dual voltage requirements.
2.2.2 Serial Ports
There are six serial ports designated ports A, B, C, D, E, and F. All six serial ports can
operate in an asynchronous mode up to a baud rate equal to the system clock divided by 8.
The asynchronous ports use 7-bit or 8-bit data formats, with or without parity. A 9th bit
address scheme, where an additional bit is set or cleared to mark the first byte of a message, is also supported.
The serial port software driver can tell when the last byte of a message has finished transmitting from the output shift register - correcting an important defect of the Z180. This is
User’s Manual 11
important for RS-485 communication because a half duplex line driver cannot have the
direction of transmission reversed until the last data bit has been sent. In many UARTs,
including those on the Z180, it is difficult to generate an interrupt after the last bit is sent.
A so called address bit can be transmitted as either high or low after the last data bit. The
address bit, if used, is followed by a high stop bit. This facility can be used to transmit 2
stop bits or a parity bit if desired. The ability to directly transmit a high voltage level
address bit was not included in the original revision of the Rabbit 2000 processor.
Serial ports A, B, C and D can be operated in the clocked serial mode. In this mode, a
clock line synchronously clocks the data in or out. Either the Rabbit serial port or the
remote device can supply the clock. When the Rabbit provides the clock, the baud rate can
be up to 1/2 of the system clock frequency. When the clock is provided by another device
the maximum data rate is system clock divided by 6 due to the need to synchronize the
externally supplied clock with the internal clock. The clocked serial mode may be used to
support “SPI” bus devices.
Serial Port A has special features. It can be used to cold-boot the system after reset. Serial
Port A is the normal port that is used for software development under Dynamic C.
All the serial ports have a special timing mode that supports infrared data communications
standards.
2.2.3 System Clock
The main oscillator uses an external crystal with a frequency typically in the range from
1.8 MHz to 26 MHz. The processor clock is derived from the oscillator output by either
doubling the frequency, using the frequency directly, or dividing the frequency by 2, 4, 6
or by 8. The processor clock can also be driven by the 32.768 kHz real-time clock oscillator for very low power operation, in which case the main oscillator can be shut down
under software control.
2.2.4 32.768 kHz Oscillator Input
The 32.768 kHz oscillator input is designed to accept a 32.768 kHz clock. A suggested lowpower clock circuit using “tiny logic” parts is documented and low in cost. The 32.768 kHz
clock is used to drive a battery-backable (there is a separate power pin) internal 48-bit
counter that serves as a real-time clock (RTC). The counter can be set and read by software
and is intended for keeping the date and time. There are enough bits to keep the date for
more than 100 years. The 32.768 kHz oscillator input is also used to drive the watchdog
timer and to generate the baud clock for Serial Port A during the cold-boot sequence.
12 Rabbit 3000 Microprocessor
2.2.5 Parallel I/O
There are 56 parallel input/output lines divided among seven 8-bit ports designated A
through G. Most of the port lines have alternate functions, such as serial data or chip select
strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs.
The output registers are cascaded as shown in Figure 2-1.
Load Data
Load Clock
Tim er Clock
Figure 2-1. Cascaded Output Registers for Pa rallel Ports D and E
Output Port
Stores to the port are loaded in the first-leve l regist er. That register in turn is transferred to
the output register on a selected timer clock. The clock can be selected to be the output of
Timer A1, B1, B2 or the peripheral clock (divided by 2?). The timer signal can also cause
an interrupt that can be used to set up the ne xt bit to be output on the next timer pulse . This
feature can be used to generate precisely controlled pulses whose edges are positioned
with high accuracy in time. Applications include communications signaling, pulse width
modulation and driving stepper motors. (A separate pulse width modulation facility is also
included in the Rabbit 3000.)
External Input
D Q D Q
Filtered Input
peripheral
clock
Figure 2-2. Digital Filtering Input Pins
Input pins to the parallel ports are filtered by cascaded D flip flops as shown in Figure 2-2.
This prevents pulses shorter then the peripheral clock from being recognized, synchronizes external pulses to the internal clock, and avoids problems with meta stability (temporarily indeterminate logical conditions due to marginal set up time with respect to the
clock).
User’s Manual 13
2.2.6 Slave Port
The slave port is designed to allow the Rabbit to be a slave to another processor, which
could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data
port. The master can read any of three registers selected via two select lines that form the
register address and a read strobe that causes the register contents to be output by the port.
These same registers can be written as I/O registers by the Rabbit slave. Three additional
registers transmit data in the opposite direction. They are written by the master by means
of the two select lines and a write strobe.
Figure 2-3 shows the data paths in the slave port.
Rabbit 3000
Master
Processor
Input Register
CPU
Output Registers
Control
Figure 2-3. Slave-Port Data Paths
Slave Interface Registers
The slave Rabbit can read the same registers as I/O registers. When incoming data bits are
written into one of the registers, status bits indi cate whi ch registers have bee n written, and
an optional interrupt can be programmed to take place when the write occurs. When the
slave writes to one of the registers carrying data bits outward, an attention line is enabled
so that the master can detect the data change and be interrupted if desired. One line tells
the master that the slave has read all the incoming data. Another line tells the master that
new outgoing data bits are available and have not yet been read by the master. The slave
port can be used to signal the master to perform tasks using a variety of communication
protocols over the slave port.
14 Rabbit 3000 Microprocessor
2.2.7 Auxiliary I/O Bus
The Rabbit 3000 instruction set supports memory access and I/O access. Memory access
takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a
traditional microprocessor design the same address and data lines are used for both memory and I/O spaces. Sharing address and data lines in this manner of ten force s compr omises
or makes design more complic ated. Gene rally the me mory bus ha s more crit ical timing a nd
less tolerant of additional capacitive loading imposed by sharing it with an I/O bus.
With the Rabbit 3000, the designer has the option of enabling completely separate buses
for I/O and memory. The auxiliary I/O bus uses many of the same pins used by the slave
port, so its operation is mutually exclusive fr om operation of the slave port. Parallel Port A
is used to provide 8 bidirectional data lines. Parallel Port B bits 2:7 provide 6 address
lines, the least significant 6 lines of the 16 lines that define the full I/O space. The auxiliary bus is only active on I/O bus cycles. The address lines remain in the same state
assumed at the end of the previous I/O cycle until another I/O cycle takes place. I/O chip
selects as well as read and write strobes are available at various other pins so that the 64
byte space defined by the 6 address lines may be easily expanded. I/O cycles also execute
in parallel on the main (memory) bus when they take place on the auxiliary bus, so additional address lines can be buffered and provided if needed.
By connecting I/O devices to the auxiliary bus, the fast memory bus is relieved of the
capacitive load that would otherwise slow the memory. For core modules based on the
Rabbit 3000, fewer pins are required to exit the core module since the slave port and the
I/O bus can share the same pins and the memory bus no longer needs to exit the module to
provide I/O capability. Because the I/O bus has less activity and is slower than the memory
bus, it can be run further physi cally without EMI and ground boun ce problems. 5 V signals
can appear on the I/O bus since the Rabbit 3000 inputs are 5 V tolerant. 5 V signals could
easily cause problems on the main bus if non 5 V tolerant 3.3 V memories are connected.
2.2.8 Timers
The Rabbit has several timer systems. The periodic interrup t is driven by the 32. 768 kHz
oscillator divided by 16, g iving an i nterrupt every 4 88 µs if enabled. This is int ended to be
used as a general-purpose clock interrupt. Timer A consists of ten 8-bit countdown and
reload registers that can be cascaded up to two levels deep. Each countdown register can be
set to divide by any number between 1 and 256. The output of six of the timers is used to
provide baud clocks for the serial ports. Any of these registers can also cause interrupts and
clock the timer-sy nchronized parallel outpu t ports. T imer B consists of a 10-bit counter that
can be read but not written. There are two 10-bit match registers and comparators. If the
match register matches the coun ter , a pulse is outpu t. Thus th e timer c an be pro gramm ed to
output a pulse at a predetermined count in the future. This pulse can be used to clock the
timer-synchronized parallel-port output registers as well as cause an interrupt. Timer B is
convenient for creating an event at a precise time in the future under program control.
Figure 2-4 illustrates the Rabbit timers.
User’s Manual 15
perclk
perclk
perclk/2
A1
Timer A System
Serial E
A2
Serial F
A3
Timer A1
perclk/2
perclk/8
Timer B System
A8
A9
A10
10-bit counter
match preload
match preload
Input
Capture
PWM
Quadrature
Decode
10 bits
match reg
match reg
A4
Serial A
Serial B
A5
Serial C
A6
Serial D
A7
compare
Timer_B1
Control Timer
Synchronized
outputs
Timer_B2
Figure 2-4. Rabbit Timers A and B
2.2.9 Input Capture Channels
The input capture channels are used to determine the time at which an event takes place.
An event is signaled by a rising or falling edge (or optionally by either edge) on one of 16
input pins that can be selected as input for either of the two channels. A 16 bit counter is
used to record the time at which the event takes place. The counter is driven by the output
of Timer A8 and can be set to count at a rate ranging from full clock speed to 1/256 the
clock speed.
T wo events are recognized: a start condi tion and a stop condition. The start c ondition may
be used to start counting and the stop condition to stop counting. However the counter
may also run continuously or run until a stop condition is encountered. The start and stop
conditions may also be used to latch the current time at the instant the condition occurs
rather than actually start or stop the counter. The same pin may be used to detect the start
16 Rabbit 3000 Microprocessor
and stop condition, for example a rising edge could be the start condition and a falling
edge the stop condition. However, optionally, the start and stop condition can be input
from separate pins.
The input capture channels can be used to measure the width of fast pulses. This is done
by starting the counter on the first edge of the pulse and capturing the counter value on the
second edge of the pulse. In this case the maximum error in the measurement is approximately 2 periods of the clock used to count the counter. If there is sufficient time between
events for an interrupt to take place the unit can be set up to capture the counter value on
either start or stop conditions or both and cause an interrupt each time the count is captured. In this case the start and stop conditions lose the connection with starting or stopping the counter and simply become capture conditions that may be specified for 2
independent edge detectors. The counter can also be cleared and started under software
control and then have its value captured in response to an input.
If desired the capture counter can synchronized with Timer B outputs used to synchronously load parallel port output registers. This makes it possible to generate an output signal precisely synchronized with an input signal. Usually it will be desired to synchronize
one of the input capture counters with the Timer B counter. The count offset can be measured by outputting a pulse at a precise time using Timer B to set the output time and capturing the same pulse. Once the phase relationship is known between the counters it is then
possible to output pulses a precise time delay after an input pulse is captured, provided
that the time delay is great enough for the interrupt routine to processes the capture event
and set up the output pulse synchronized by Timer B. The minimum time delay needed is
probably less than 10 microseconds if the software is done carefully the clock speed is reasonably high.
2.2.10 Quadrature Encoder Inputs
A quadrature encoder is a common electromechanical device used to track the rotation of
a shaft, or in some cases to track the motion of a linear fo llower. These devices are usually
implemented by the use of a disk or a strip with alternate opaque and transparent bands
that excite dual optical detectors. The output signals are square waves 90 degrees out of
phase also called being in quadrature with each other. By having quadrature signals, the
direction of rotation can be detected by noting which signal leads the other signal.
The Rabbit 3000 has 2 quad rat ur e enco der uni ts . Ea ch un it has 2 inpu t s, one be in g the no rmal input and the other the 90 degree or quadrature input. An 8 bit up down counter counts
encoder steps in the forward and backw ard dire ction. The cou nt can be exte nd ed beyon d 8
bits by an interrupt that takes pl ace each time the count overf lows or und erflows. The external signals are synchronized with an internal clock provided by the output of Timer A10.
2.2.11 Pulse Width Modulation Outputs
The pulse width modulated output generates a train of pulses periodic on a 1024 pulse
frame with a duty cycle that varies from 1/1024 to 1024/1024. There are 4 independent
PWM units. The units are driv en by the out put of Timer A9 which may be used to vary the
User’s Manual 17
length of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into
groups distributed 2 56 counts apart in th e 1024 frame. The puls e width modu lation output s
can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be
used to directly drive devices that have intrinsic filtering such as motors or solenoids.
2.2.12 Spread Spectrum Clock
The main system clock, which is generated by the crystal oscillator or input from an external oscillator, can be modified by a clock spectrum spreader internal to the Rabbit 3000
chip. When the spectrum spreader is engaged, the clock is alternately speeded up and
slowed down, thus spreading the spectrum of the clock harmonics in the frequency
domain. This reduces EMI and improves the results of official radiated-emissions tests
typically by 15–20 dB at critical frequencies. The spectrum spreader has 3 modes of operation: off, normal, and strong. Slightly faster memory access time is required when the
spectrum spreader is used: 2–3 ns for the normal setting when the clock doubler is
enabled, and 6–9 ns for the strong setting when the clock doubler is used. The spreader
slightly influences baud rates and other timings because it introduces clock jitter, but the
effect is usually small enough to be negligible.
2.2.13 Separate Cor e and I/O Power Pins
The silicon die that constitutes the Rabbit 3000 processor is divided in to the core logic and
the I/O ring. The I/O ring located on the 4 edges of the die holds the bonding pads and the
large transistors use d to cre ate the I/ O buffers that drive signals to the external world. The
core section, inside the I/O ring contains the main processor and peripheral logic. The
clock and clock edges in the core are very fast with large transient currents that create a lot
of noise that is communicated to the outside of the package via the power pins. The I/O
buffers have slower switching times and mostly operate at much lower frequencies than
the core logic. The Rabbit has separate power and ground pins for the core and I/O ring.
This allows the designer to feed clean power to the I/O ring filtered to be free of the noise
generated by the core switching. This minimizes high frequency noise that would otherwise appear on output pins driven by buffers in the I/O ring. The result is lower EMI.
2.3 Design Standards
The same functionality can often be accomplished in more than one way with the Rabbit
3000. By publishing design standards, or standard ways to accomplish common objec-
tives, software and hardware support become easier.
Refer to the Rabbit 3000 Microprocessor Designer’ s Handbook for additional information.
2.3.1 Programming Port
Rabbit Semiconductor publishes a specification for a standard programming port (see
Appendix A, “The Rabbit Programming Port”) and provides a converter cable that may be
used to connect a PC serial port to the standard programming interface. The interface is
implemented using a 10-pin connector with two rows of pins on 2 mm centers. The port is
connected to Rabbit Serial Port A, to the startup mode pins on the Rabbit, to the Rabbit
18 Rabbit 3000 Microprocessor
reset pin, and to a programmable output pin that is used to signal the PC that attention is
needed. With proper precautions in design and software, it is possible to use Serial Port A
as both a programming port and as a user-defined serial port, although this will not be necessary in most cases.
Rabbit Semiconductor supports the use of the standard programming port and the standard
programming cable as a diagnostic and setup port to diagnosis problems or set up systems
in the field.
2.3.2 Standard BIOS
Rabbit Semiconductor provides a standard BIOS for the Rabbit. The BIOS is a software
program that manages startup and shutdown, and provides basic services for software running on the Rabbit.
2.4 Dynamic C Support for the Rabbit
Dynamic C is Z-World’s interactive C language development system. Dynamic C runs on
a PC under Windows 32-bit operating systems. Dynamic C provides a combined compiler,
editor, and debugger. The usual method for debugging a target system based on the Rabbit
is to implement the 10-pin programming connector that connects to the PC serial port via a
standard converter cable. Dynamic C libraries contain highly perfected software to control
the Rabbit. These includes drivers, utility and math routines and the debugging BIOS for
Dynamic C.
In addition, the internationally known real-time operating system, uC/OS-II, has been
ported to the Rabbit, and is available with Dynamic C on a license-free, royalty-free basis
for use in Rabbit-based products..
User’s Manual 19
20 Rabbit 3000 Microprocessor
3. DETAILS ON RABBIT
MICROPROCESSOR FEATURES
3.1 Processor Registers
The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure
below shows the register layout. The XPC and IP registers are new. The EIR register is the
same as the Z80 I register, and is used to point to a table of interrupt vectors for the externally generated interrupts. The IIR register occupies the same logical position in the
instruction set as the Z80 R register, but its function is to point to an interrupt vector table
for internally generated interrupts.
A
H
D
B
A'
H '
D '
B '
F
L
E
C
L'
E '
C '
8/16-bit
registers
F '
Alternate Registers
SZ V C
S-sign, Z-zero, V-overflow, C-carry
Bits marked "x" are read/write.
xxx x
F - flag register layout
Figure 3-1. Rabbit Registers
IX
IY
SP
PC
XPC
IP
IIR
EIR
A- 8-bit accumulator
F - flags register
HL- 16-bit accumulator
IX, IY - Index registers/alt accum’s
SP - stack pointer
PC- program counter
XPC - extension of program counter
IIR - internal interrupt register
EIR-external interrupt register
IP - interrupt priority register
User’s Manual 21
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