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CV-M9 GE
Operation Manual
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JAI CV-M9 GE Operation Manual

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GigE Vision
Digital 3CCD Progressive Scan
CV-M9 GE
Operation Manual
Hardware Part
10 April 2007 /GJ
Camera revision:
0
Manual version: 1.0
CV-M9 GE
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- Table of Contents -
1. General......................................................................................................... 3
2. Standard Composition ....................................................................................... 3
3. Main Features ................................................................................................. 3
4. Locations and Functions..................................................................................... 4
5. Pin Assignment................................................................................................ 5
5.1. 12-pin Multi-connector (DC-in/GPIO/Iris Video) .................................................. 5
5.2. Digital Output Connector for Gigabit Ethernet ................................................... 5
6. GPIO (Inputs and outputs ) ................................................................................. 6
6.1. Overview ............................................................................................... 6
6.1.1. LUT ( Look Up Table) .......................................................................... 6
6.1.2. 12bit Counter ...................................................................................6
6.1.3. Pulse Generators (0 to 3) ..................................................................... 6
6.2. Inputs and outputs table............................................................................. 7
6.2.1. Equivalent circuit for TTL 1 and 2 inputs .................................................. 8
6.2.2. Equivalent circuit for LVDS input ............................................................ 8
6.2.3. Equivalent circuit for TTL IN 3 Input ........................................................ 8
6.2.4. Equivalent circuit for TTL OUT 1 and 2 outputs........................................... 9
6.3. Configuring the GPIO module (register settings) ................................................ 9
6.3.1. Signal Selector .................................................................................. 9
6.3.2. xTTL_LVDS Selector............................................................................. 9
6.3.3. 12bit counter .................................................................................. 10
6.3.4. Pulse generator (20 bit x 4) ................................................................ 10
6.4 GPIO programming examples ....................................................................... 12
6.4.1 Trigger Phase Control ......................................................................... 12
6.4.2 Internal Trigger Generator ................................................................... 13
6.4.3 Multi EEN Control with PWC .................................................................. 14
7. GigE Vision Streaming Protocol (GVSP) ................................................................ 15
7.1. Digital Video Output (Bit Allocation) ............................................................ 15
7.2. Bit Allocation (Pixel Format / Pixel Type) ...................................................... 15
7.2.1. GVSP_PIX_BGR10V1_PACKED (32bit) ...................................................... 15
7.2.2. GVSP_PIX_BGR10V2_PACKED (32bit) ...................................................... 15
7.2.3. GVSP_PIX_RGB8_PACKED (24bit)........................................................... 15
8. Functions and Operations ................................................................................. 16
8.1. GigE Vision Standard Interface .................................................................... 16
8.2. Recommended Network Configurations .......................................................... 16
8.2.1 Verified Network Interface Cards (NICs) ................................................... 16
8.3. Basic functions ...................................................................................... 17
8.3.1. White Balance (by gain setting) ............................................................ 17
8.3.2. White balance (by individual R, G and B channel shutter settings)................... 18
8.3.3. Automatic Dynamic shading correction.................................................... 18
8.3.4. Knee function.................................................................................. 19
8.3.5. ROI (Region of Interest) ..................................................................... 19
8.3.6. Electronic Shutter............................................................................ 20
8.3.7. Color bar for test............................................................................. 21
8.3.8. Analogue output for Auto Iris Lens ........................................................ 21
8.4. Sensor Layout and timing .......................................................................... 22
8.4.1. CCD Sensor Layout ........................................................................... 22
8.4.2. Horizontal timing............................................................................. 23
8.4.3. Vertical timing................................................................................ 23
8.4.4. Partial Scanning .............................................................................. 24
8.4.5. Vertical binning............................................................................... 25
8.5. Operation Modes .................................................................................... 27
8.5.1. LVAL synchronous accumulation ........................................................... 27
CV-M9 GE
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8.5.2. LVAL a-synchronous accumulation......................................................... 29
8.5.3. Continuous operation ........................................................................ 30
8.5.4. Edge Pre-select Trigger Mode .............................................................. 30
8.5.5. Pulse Width Control Trigger Mode ......................................................... 32
8.5.6. Sequential Trigger Mode (EPS) ............................................................. 33
8.5.7. Delayed Readout Mode (EPS, PWC)........................................................ 34
8.5.8. Smear-less Mode.............................................................................. 35
8.6. Operation Mode and Functions matrix........................................................... 36
9. Register Map ................................................................................................ 37
10. External Appearance and Dimensions ................................................................. 47
11. Specifications.............................................................................................. 47
11.1. Spectral response .................................................................................. 47
11.2. Specification table ................................................................................. 48
12. Appendix................................................................................................... 49
12.1. Precautions ......................................................................................... 49
12.2. Typical Sensor Characteristics .................................................................. 49
12.3. References.......................................................................................... 50
Index......................................................................................................... 51
13. User's Record ................................................................................................ 1
CV-M9 GE
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1. General
The CV-M9GE is a digital 3CCD progressive scan RGB color camera with GigE Vision Interface. Based on the GigE Vision standard, the camera is connected to the host computer via a standard Gigabit Ethernet port, without the need for a dedicated frame grabber. This high-speed serial interface that is capable of bridging distances up to 100 meters uses CAT 5e or CAT 6 Ethernet cables. All Gigabit Ethernet infrastructures, such as switches, routers and fiber-optic converters, can be used together with this camera, allowing even longer distances to be bridged. The camera uses three 1/3” format XGA (1024 x 768 pixel) CCD sensors mounted on a dichroic prism, providing full resolution for each of the Red, Green and Blue color bands. The compact 3CCD C-mount prism unit is designed for the highest color fidelity. A built-in shading correction greatly reduces chromatic shading, thus widening the choice of C-mount lenses that can be used with this camera. The camera outputs 30 full frames/second as 3 x 8 bit or 3 x 10 bit images in continuous operation. Functions like partial scanning and vertical binning allow even higher frame rates. External trigger can also be applied to the camera, to capture images based on external events.
The CV-M9GE also complies with the GenICam standards, as it has in internal XML file that is used to describe the functions/features of the camera. For further information on GenICam please go to www.emva.org.
As a programming application interface, JAI provides an SDK (Software Development Kit). This SDK includes software documentation, register information, code examples and objects such as Transport Layer and Device Drivers (Optimized Filter Driver and Standard Windows Stack). The JAI SDK Light can be downloaded from www.jai.com
The latest version of this manual can be downloaded from: www.jai.com For camera revision history, please contact your local JAI distributor.
2. Standard Composition
The standard camera composition consists of the camera main body, C-mount protection cap and tripod mount plate.
3. Main Features
• 3 x 1/3” progressive scan RGB color camera
• 1024 (h) x 768 (v) active area
• 4.65 µm square pixels
• Compact RGB prism for C-mount lenses
• Chromatic shading reduction for wider choice of lenses
• 30 frames/second with full resolution
• 86 frames/second with 1/8 partial scan
• Vertical binning for higher sensitivity and frame rate
• 12 bit internal video processing
• 24 or 30-bit RGB output via GigE Vision
• Edge Pre-Select and Pulse Width Control trigger modes
• Sequential trigger mode for on-the-fly change of shutter, gain and ROI
• Manual, continuous (auto-tracking) or one-push auto white balance
• Color bar test image for set-up
• Comprehensive software suite and SDK (SDK Light) for Windows XP
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4. Locations and Functions
/ TRIG
DC IN
GigE
ACT.
LINK
W.B.
POWE R
/ TRIG
(depth0.2)
HIROSE 12pinConnector
8-M3depth5
HONDAGigabit-Ethernrt Jack
①
　②
③
　④
⑤⑥
⑦
⑧
⑨
1 Lens mount of C-mount type. *1) 2 RGB Prism with 3 x 1/3” CCD sensors
3 RJ45 GigE Connector 4 Hirose 12-pin connector for DC +12V power external sync signals 5 LED for power and trigger indication
Orange : Initialization after power ON Green : Normal mode Green flashing : Trigger pulse is being input
6 Switch for one-push white balance
7 LED for GigE network condition: LINK 8 LED for GigE network condition: ACT. 9 Mounting holes 8 x M3 depth 5mm .
*1) Note: Rear protrusion on C-mount lens must be less than 4.0mm
Fig. 1. Locations
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5. Pin Assignment
5.1. 12-pin Multi-connector (DC-in/GPIO/Iris Video)
Type: HR10A-10R-12PB-01 (Hirose) male.
Pin no.
Signal
Remarks 1 GND 2 +12 V DC input 3 GND 4 Iris video
Only for Continuous mode
5 GND 6 LVDS + / TTL IN 1 7 LVDS - / TTL IN 2 8 TTL OUT 1 9 TTL OUT 2
10 TTL IN
3
GPIO IN/OUT
11 +12 V DC input 12 GND
(Seen from rear of camera.)
3
4
5
6
7
8
9
10
11
12
1
2
Fig. 2. 12-pin connector.
5.2. Digital Output Connector for Gigabit Ethernet
RJ-45 Connector
12345678
Fig 3. Gigabit Ethernet connector
Pin No In/Out Name
1 In/Out MX1+ (DA+) 2 In/Out MX1- (DA-) 3 In/Out MX2+ (DB+) 4 In/Out MX3+ (DC+) 5 In/Out MX3- (DC-) 6 In/Out MX2- (DB-) 7 In/Out MX4+ (DD+) 8 In/Out MX4- (DD-)
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6. GPIO (Inputs and outputs)
6.1. Overview
All input and output signals pass through the GPIO (General Purpose Input and Output) module. The GPIO module consists of a Look-Up Table (LUT – Cross-Point Switch), 4 Pulse Generators and a 12-bit counter. In the LUT, the relationship between inputs, counters and outputs is governed by internal register set-up.
LUT
（
Cross point switch)
LVAL IN
12bit
Counter
25MHz
Pixel Cloc
k
xTTL_LVDS Sel
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1 HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
CAMERA TRIGGER CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
LUT
（
Cross point switch)
LVAL IN
LVAL IN
12bit
Counter
25MHz
Pixel Cloc
k
xTTL_LVDS Sel
DVAL IN
DVAL IN
FVAL IN
FVAL IN
EEN IN
EEN IN HIROSE TTL IN 1
HIROSE TTL IN 1 HIROSE TTL IN 2
HIROSE TTL IN 2
LVDS IN
LVDS IN
HIROSE TTL IN 3
HIROSE TTL IN 3
Soft Trigger 0
Soft Trigger 0
Pulse Generator 3
The blocks shown in the above diagram have the following functionality:
6.1.1. LUT (Look Up Table)
The LUT works as a cross-point switch which allows connecting inputs and outputs freely. The signals LVAL_IN, DVAL_IN, FVAL_IN and EEN_IN all originate from the camera timing circuit. The signal CAMERA_TRIGGER is connected to the camera timing circuit, allowing a hardware trigger.
6.1.2. 12-bit Counter
A 25MHz clock or the camera pixel clock can be used as a source. The counter has a “Divide by N”, where N has the range 1 through 4096, allowing a wide range of clock frequencies to be programmed.
6.1.3. Pulse Generators (0 to 3)
Each pulse generator consists of a 20bit counter. The behavior of these signals is defined by their pulse width, start point and end point. The pulse generator signals can be set in either triggered or periodic mode. In triggered mode, the pulse is triggered by the rising edge/falling edge/high level or low level of the input signal. In periodic mode, the trigger continuously generates a signal that is based on the configured pulse width, starting point and endpoint.
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6.2. Inputs and outputs table
Signals I/O Description diagram
LVAL_IN I LVAL (Line Valid) from camera timing circuit
(See chapter 8.4 for timing relationship) DVAL IN I DVAL from camera FVAL_IN I FVAL (Frame Valid) from camera timing circuit
(See chapter 8.4 for timing relationship) EEN_IN I EEN (Exposure Enable) from camera timing
circuit. (See chapter 8.4 for timing
relationship) HIROSE_TTL_IN1 I TTL input on pin 6 of Hirose 12-pin.
Active when TTL is selected by xTTL_LVDS Sel
Fig. 4
HIROSE_TTL_IN2 I TTL input on pin 7 of Hirose 12-pin.
Active when TTL is selected by xTTL_LVDS Sel
Fig. 4
LVDS_IN I LVDS signal input on Hirose connector
LVDS + Pin 6 / LVDS – Pin 7
Active when LVDS is selected by xTTL_LVDS Sel
Fig. 5
HIROSE_TTL_IN3 I TTL input on pin 10 of Hirose 12-pin. Fig. 6 Soft_Trigger_0 I Software trigger input from Ethernet
Refer to GPIO module register xx Pulse Generator out 0 I Pulse Generator 0 output Pulse Generator out 1 I Pulse Generator 1 output Pulse Generator out 2 I Pulse Generator 2 output Pulse Generator out 3 I Pulse Generator 3 output CAMERA TRIGGER O Trigger signal to camera timing circuit. HIROSE TTL OUT 1 O TTL output on Pin 8 of Hirose 12-pin Fig. 7 HIROSE TTL OUT 2 O TTL output on Pin 9 of Hirose 12-pin Fig. 7 Pulse Generator in 0 O Pulse Generator 0 Clear input Pulse Generator in 1 O Pulse Generator 1 Clear input Pulse Generator in 2 O Pulse Generator 2 Clear input Pulse Generator in 3 O Pulse Generator 3 Clear input
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6.2.1. Equivalent circuit for TTL 1 and 2 inputs
This circuit is for TTL IN 1 and TTL IN 2 through
TTL_IN
+3.3V
R3 47K
R4 27K
R5
2.2K
R2
1M
-
+
U1A
D1
R1
1K
pins 6 and 7 at the 12-pin Hirose connector. It is a DC­coupled input. See GPIO selector for setting this input (TTL or LVDS)
Fig.4 Hirose TTL IN (1 and 2) equivalent circuit
6.2.2. Equivalent circuit for LVDS input
This circuit is for LVDS IN – and + through pins 6 and 7 at the 12-pin Hirose connector.
LVDS_IN+
LVDS_IN-
R1
100
D2
-
+
U1A
D1
See GPIO selector for setting this input (TTL or LVDS)
Fig.5 LVDS IN equivalent circuit
6.2.3. Equivalent circuit for TTL IN 3 Input
This circuit is for TTL IN 3 through pin 10 at the 12-pin Hirose connector.
R1 1K
TTL_IN3
+5V
R4 1K
Q1
2
13
C1
0.1uF
D1
2
1
R2
1.2K
R3 15K
This circuit is AC coupled.
Fig.6 Hirose TTL IN 3 equivalent circuit
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6.2.4. Equivalent circuit for TTL OUT 1 and 2 outputs
This circuit is for TTL OUT 1 and 2 through pins 8 and 9 at the Hirose 12-pin connector.
+5V
Q1A
2
16
Q1B
5
4 3
R1 10
R2 10
R3 120
R4 150
TTL_OUT1
The output is sent from a 75 ohm source which is a complementary Emitter-follower circuit. The supply voltage for this circuit is 5V.
Fig.7 Hirose TTL OUT equivalent circuit
6.3. Configuring the GPIO module (register settings)
6.3.1. Signal Selector
Address Internal Name Access Size Value (Range)
0xB058 CAMERA TRIG Selector R/W 4
0xB05C CAMERA Ex. VD Selector R/W 4
0xB060 CAMERA Ex. HD Selector R/W 4
0xB064 HIROSE TTL OUT 1 Selector R/W 4
0xB068 HIROSE TTL OUT 2 Selector R/W 4
0xB06C Pulse Generator 0 Selector R/W 4
0xB070 Pulse Generator 1 Selector R/W 4
0xB074 Pulse Generator 2 Selector R/W 4
0xB078 Pulse Generator 3 Selector R/W 4
GPIO Selector: 0x00:CAMERA LVAL IN 0x01:CAMERA DVAL IN 0x02:CAMERA FVAL IN 0x03:CAMERA EEN IN 0x04:HIROSE TTL IN 1 0x05:HIROSE TTL IN 2 0x06:HIROSE TTL IN 3 0x07:HIROSE LVDS IN 0x09:SOFT TRIG 0 0x0D:Pulse Generator 0 0x0E:Pulse Generator 1 0x0F:Pulse Generator 2 0x10:Pulse Generator 3 0x7F:No Connect
Add 0x80 will result in low active output.
6.3.2. xTTL_LVDS Selector
Address Internal Name Access Size Setting Value (and range)
0xA8B0 xTTL_LVDS Select R/W 4
0x00 : TTL In 1, TTL In 2 Active 0x01 : LVDS In Active
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6.3.3. 12-bit counter
Address Internal Name Access Size Setting Value (and range)
0xB000 Clock source R/W 4
0: 25MHz
1: Pixel Clock
0xB004 Divide by N R/W 4
0x000: N=1 0x001: N=2 0x002: N=3 | 0xFFF: N=4096
6.3.4. Pulse generator (20 bit x 4)
There are 4 pulse generators (designated 0 through 3) that can be used to create various timing scenarios by programming start point, endpoint, length and repeats.
Start Point
End Point
Length
Start Point
End Point
Length
Address Internal Name Access Size Setting Value (and range)
0xB008 Length Counter 0 R/W 4 0x00001 to 0xFFFFF 0xB00C Start point Counter 0 R/W 4 0x00000 to 0xFFFFF
0xB010 Repeat Count 0 R/W 4
0x00: infinite 0x01: 1 time | 0xFF: 255 times
0xB014 End point Counter 0 R/W 4 0x00001 to 0xFFFFF
0xB018 Counter Clear 0 R/W 4
0: Free Run 1: High Level Clear 2: Low Level Clear 4: Rising Edge Clear
8: Falling Edge Clear 0xB01C Length Counter 1 R/W 4 0x00001 to 0xFFFFF 0xB020 Start point Counter 1 R/W 4 0x00000 to 0xFFFFF
0xB024 Repeat Count 1 R/W 4
0: Infinite
1: 1 time
|
255: 255 times 0xB028 End point Counter 1 R/W 4 0x00001 to 0xFFFFF
0xB02C Counter Clear 1 R/W 4
0x00: Free Run
0x01: High Level Clear
0x02: Low Level Clear
0x04: Rising Edge Clear
0x08: Falling Edge Clear 0xB030 Length Counter 2 R/W 4 0x00001 to 0xFFFFF 0xB034 Start point Counter 2 R/W 4 0x00000 to 0xFFFFF
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Address Internal Name Access Size Setting Value (and range)
0xB038 Repeat Count 2 R/W 4
0x00: Infinite
0x01: 1 time
|
0xFF: 255 times 0xB03C End point Counter 2 R/W 4 0x00001 to 0xFFFFF
0xB040 Counter Clear 2 R/W 4
0x00: Free Run
0x01: High Level Clear
0x02: Low Level Clear
0x04: Rising Edge Clear
0x08: Falling Edge Clear 0xB044 Length Counter 3 R/W 4 0x00001 to 0xFFFFF 0xB048 Start point Counter 3 R/W 4 0x00000 to 0xFFFFF
0xB04C Repeat Count 3 R/W 4
0x00: Infinite
0x01: 1 time
|
0xFF: 255 times 0xB050 End point Counter 3 R/W 4 0x00001 to 0xFFFFF
0xB054 Counter Clear 3 R/W 4
0x00: Free Run
0x01: High Level Clear
0x02: Low Level Clear
0x04: Rising Edge Clear
0x08: Falling Edge Clear
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6.4 GPIO programming examples
6.4.1 Trigger Phase Control
100clock delay to the input Trigger
Address
Registe
r
Value 0xA040 Trigger Mode 1 = EPS(Edge pre-select) 0xB000 Clock Choice 1 = Pixel Clock 0xB004 Counter Dividing Value 0 = Pass through 0xB008 Length Counter 0 1000 Clocks 0xB00C Start point Counter 0 100 Clocks 0xB010 Repeat Count 0 1 0xB014 End point Counter 0 500 Clocks 0xB018 Counter Clear 0 4 = Rising Edge Clear 0xB058 CAMERA TRIG Selector 13 = pulse generator 0 0xB06C Pulse Generator 0 Selector 4 = HIROSE TTL In 1
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN
HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
LUT
（Cross point switch)
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN
HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
LUT
（Cross point switch)
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN
HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
LUT
（Cross point switch)
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN
HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
LUT
（Cross point switch)
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
LUT
（Cross point switch)
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
HIROSE TTL IN 1
Pulse Generator 0
100
500
1000
output
HIROSE TTL IN 1
Pulse Generator 0
100
500
1000
output
Pulse Generator 0 timing
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6.4.2 Internal Trigger Generator
Create a trigger signal and trigger the camera
Address
Registe
r
Value 0xA040 Trigger Mode 1 = EPS 0xB000 Clock Choice 1 = Pixel Clock 0xB004 Counter Dividing Value 963 = 1/964 dev(Line Rate) 0xB008 Length Counter 0 1000 Clocks 0xB00C Start point Counter 0 100 Clocks 0xB010 Repeat Count 0 0 = Free Run 0xB014 End point Counter 0 500 Clocks 0xB018 Counter Clear 0 0 = No Clear 0xB058 CAMERA TRIG Selector 13 = pulse generator 0
LUT
（Cross point switch)
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1 HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
Line Rate 37.5KHz
LUT
（Cross point switch)
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1 HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
LUT
（Cross point switch)
LVAL IN
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1 HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD HIROSE TTL OUT 1 HIROSE TTL OUT 2
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
Line Rate 37.5KHz
12bit
Counter
25MHz
Pixel Clock
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
Line Rate 37.5KHz
Pulse Generator 0
100 Line
500 Line
1000 Line
output
Pulse Generator 0
100 Line
500 Line
1000 Line
output
Pulse Generator 0 timing
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6.4.3 Multi EEN Control with PWC
Camera EEN converts to 3 pulses and feed camera in PWC mode
Address
Registe
r
Value 0xA040 Trigger Mode 2 = PWC(Pulse width control) 0xB000 Clock Choice 1 = Pixel Clock 0xB004 Counter Dividing Value 963 = 1/964dev(Line Rate) 0xB008 Length Counter 0 1000 Clocks 0xB00C Start point Counter 0 100 Clocks 0xB010 Repeat Count 0 3 Cycles 0xB014 End point Counter 0 500 Clocks 0xB018 Counter Clear 0 1 = Level Low 0xB058 CAMERA TRIG Selector 4 = Hirose TTL IN 1 0xB06C Pulse Generator 0 Selector 3 = CAMERA EEN IN
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD
HIROSE TTL OUT 1
HIROSE TTL OUT 2
LUT
（Cross point switch)
LVAL IN
12bit
Counter
25MHz
Pixel Clock
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
Line Rate 37.5KHz
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD
HIROSE TTL OUT 1
HIROSE TTL OUT 2
CAMERA TRIGGER
CAMERA Ext. VD CAMERA Ext. HD
HIROSE TTL OUT 1
HIROSE TTL OUT 2
LUT
（Cross point switch)
LVAL IN
12bit
Counter
25MHz
Pixel Clock
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
Line Rate 37.5KHz
LUT
（Cross point switch)
LVAL IN
12bit
Counter
25MHz
Pixel Clock
xTTL_LVDS Select
DVAL IN
FVAL IN
EEN IN HIROSE TTL IN 1
HIROSE TTL IN 2
LVDS IN
HIROSE TTL IN 3
Soft Trigger 0
Pulse Generator 3
(20bit Counter)
Pulse Generator 2
(20bit Counter)
Pulse Generator 1
(20bit Counter)
Pulse Generator 0
(20bit Counter)
Line Rate 37.5KHz
EEN
IN
500
1000
output
EEN
IN
500
1000
output
Pulse Generator 0 timing
CV-M9 GE
- 15 -
7. GigE Vision Streaming Protocol (GVSP)
7.1. Digital Video Output (Bit Allocation)
Although the CV-M9GE is a digital camera, the image is generated by an analog component, the CCD sensor. There are three CCD sensors in this camera. One for each R, G and B channel. The table and diagram below show the relationship between the analog CCD output level and the digital output.
CCD out Analog Signal * Digital Out(30bit) Digital Out(24bit)
Black Setup 3.6%, 25mV 32LSB 8LSB 200mV 700mV 890LSB 222LSB 230mV 800mV 1023LSB 255LSB
Ana log S igna l [mV ]
B lack Leve l
1023
890
32
0
25
700
D ig i ta l Ou t [LSB ]
Wh i te C l ip Leve l
100%Level
800
The standard setting for 10-bit video level is 890 LSB. For 8-bit, the standard setting is 222 LSB. 200 mV CCD output level, 100% video output.
Fig.8 Digital Output
7.2. Bit Allocation (Pixel Format / Pixel Type)
In the GigE Vision Interface, GVSP (GigE Vision Streaming Protocol) is used for an application layer protocol relying on the UDP transport layer protocol. It allows an application to receive image data, image information and other information from a device. In CV-M9GE, the following pixel types supported by GVSP are available. With regard to the details of GVSP, please refer to the GigE Vision Specification available from AIA.
7.2.1. GVSP_PIX_BGR10V1_PACKED (32bit)
１Byte ２Byte ３Byte ４Byte
RRGGBBXXBBBBBBBBGGGGGGGGRRRRRRRR
Little Endian Bit Alignment
7.2.2. GVSP_PIX_BGR10V2_PACKED (32bit)
１Byte ２Byte ３Byte ４Byte
RRRRRRRRRRGGGGGGGGGGBBBBBBBBBBXX
Little Endian Bit Alignment
7.2.3. GVSP_PIX_RGB8_PACKED (24bit)
１Byte 目 ２Byte 目 ３Byte 目
RRRRRRRRGGGGGGGGBBBBBB B B
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