The CV-A33CL is a digital CMOS camera designed for automated imaging applications, featuring
high speed within a uniform and compact housing.
The high-speed shutter function, asynchronous random trigger mode and partial scan mode, with
window of interest, allows the camera to capture high quality images of fast moving objects
with a high frame rate. The CV-A33CL features the Camera Link standardized multiplexed signal
output interface.
The latest version of this manual can be downloaded from: www.jai.com
The latest version of Camera Control Tool for CV-A33CL can be downloaded from: www.jai.com
For camera revision history, please contact your local JAI distributor.
2. Standard Composition
The standard camera composition consists of the camera main body and tripod mount plate.
• 4953 frames/second for a 659 (h) x 3 (v) pixel image
• Programmable X and Y origin and size for window of interest
• Edge pre-select and pulse width external trigger modes
• Global shutter for instant full frame exposure
• Programmable shutter from 1 LVAL to 492 LVAL (16.8 µsec. to 8.3 msec.)
• Auto trigger function based on programmable 659 (h) x n (v) window
• Auto trigger frame rate up to 5403 frames/second
• Accepts standard C-mount lenses
• A-series platform
• Short ASCII commands for fast mode setup via serial port
• Setup by Windows 98/NT/2000 software via RS 232C or Camera Link
- 2 -
4. Locations and Functions
C-Moun t
2
5
4xM3 Depth 4
44
(1 .73 )
35
(1 .38 )
1
4xM3 Depth 4
1. CMOS sensor
2. Lens mount (C-mount)
3. Digital output connector (Camera Link)
4. DC in/Trigger in/RS-232C connector
5. Mounting holes M3. Depth 4. (10x)
4-M3深4
(0 .2 )
M3深4
6-
26
17 .5
26
CV-A33CL
(1 .02 )
5
(0 .2 )
(0 .69 )
5
8
(0 .31 )
(1 .02 )
5
Fig. 1. Locations
50
(1 .97 )
58
(2 .28 )
50
(1 .97 )
5
4
7.6
(0 .3 )
IN /DC
TR IG
/ODIGITAL I
U4-40
コネクター固定ネジ
3
機銘版
5
- 3 -
CV-A33CL
5. Pin Assignment
5.1. 12-pin Multi-connector (DC-IN/Trigger)
Type: HR10A-10R-12PB-01
(Hirose) male.
(Seen from rear of camera.)
9
1
2
11
3
4
8
10
7
12
6
5
Fig. 2. 12-pin connector.
Refer to 7.1. Inside switch settings.
Pin no. Signal Remarks
1 GND
2 +12 V DC input
3 GND
4 N/C
5 GND
6 RXD in
7 TXD out
8 GND
9 EEN out
10 Trigger input
11 N/C
12 GND
*) Internal SW300-1 on rear board for 75 Ω terminations.
RS 232C. Or via Camera Link by internal
SW200 on PK8378A (Off=HR)
And via Camera Link
Or via Camera Link. (TI=1 for HR) *)
5.2. Digital Output Connector for Camera Link
13
26
1
14
Fig. 3. Camera Link connector
The digital output signals follow the Camera Link standardized multiplexed signal output
interface. Camera Link base configuration is used. The interface circuit is build around the NS
type DS90CR285MTD.
The following signals are found on the Digital Output Connector:
SerTC RXD serial data to camera
SerTFG TXD serial data to frame grabber
CC1 Trigger input
CC2 Factory use X0 to X3 Camera Link multiplexed data out
Xclk Camera Link clock. Used as pixel clock.
In the Channel Link X0 to X3 multiplexed signals the following signals are encoded.
D0 – D9 2 x 8/10 bit video data out.
LVAL Line VALid. Video line data is valid. High for valid line.
FVAL Frame VALid. Video frame data is valid. High for valid frame.
DVAL Data VALid. Effective video pixel data is valid. High for valid data.
EEN Exposure ENable. High during exposure.
The polarity is positive and TRIG in negative as factory setting.
For Camera Link interface principle diagram please check Fig. 7.
Type: 26 pin MRD connector
3M 10226-1A10JL
(Or via 12 pin HR by internal SW200.
On for CL)
(Or on 12 pin HR. TI=0 for CL)
- 4 -
CV-A33CL
5.3. Input and Output Circuits
5.3.1. Trigger input
The trigger inputs on pin #10 12 pin Hirose
connector is AC coupled. To allow a long pulse
width, the input circuit is a flip flop, which is
toggled by the negative or positive
differentiated spikes caused by the falling or
rising trigger edges.
The trigger polarity can be changed.
Trigger input level 4 V ±2 V. It can be 75Ω
terminated by internal SW300 on PK8388A.
The trigger inputs can be changed to
Camera Link input. (TI=0 for CL)
Fig. 4. Trigger input.
Trig input
Trig input
pin #10
pin #10
GND
GND
100n
100n
75Ω
75Ω
SW 300
SW 300
1k
1k
15k
15k
68k
68k
1n
1n
100k
100k
+5V
+5V
1k
1k
TTL
TTL
GND
GND
5.3.2. EEN output
On pin #9 on 12 pin HR connector EEN The output
circuit is 75 Ω complementary emitter followers. It
will deliver a full 5 volt signal.
Output level ≥4 V from 75Ω. (No termination).
EEN is also found in Camera Link.
Fig. 5. EEN output
TTL
TTL
100
100
2k2
2k2
10k
10k
+5V
+5V
75
75
2
2
2
2
#9/12
#9/12
EEN output
EEN output
GND
GND
- 5 -
CV-A33CL
5.3.3. Camera Link interface
The video output is Camera Link with 10 or 8 bit video placed in a base configuration. The digital
output signals follow the Camera Link standardized multiplexed signal output interface. The
Camera Link output driver is NS type DS90CR285MTD.
The data bits from the digital video, FVAL, LVAL, DVAL and EEN are multiplexed into the twisted
pairs, which are a part of the Camera Link. Trigger signals and the serial camera control are
feed directly through its own pairs. The trigger input can also be TTL on the 12 pin connector.
(TI=0 for CL. TI=1 for 12 pin HR). The serial camera control can be switches between the 12 pin
connector or CL by the internal switch SW200 on PK8387B.
The 26 pin MDR connector pin assignment follows the Camera Link base configuration.
For a detailed description of Camera Link specifications, please refer to the Camera Link
standard specifications found on www.jai.com
CV-A33 CameraCamera Link Cable
Camera Signals
Camera Signals
8bit 10bit
8bit 10bit
D2 D0
D2 D0
D3 D1
D3 D1
D4 D2
D4 D2
D5 D3
D5 D3
D6 D4
D6 D4
D7 D5
D7 D5
D8 D6
D8 D6
D9 D7
D9 D7
NC D8
NC D8
NC D9
NC D9
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
LVAL
LVAL
FVAL
FVAL
DVAL
DVAL
EEN
EEN
Pclk
Pclk
TXD out
TXD out
RXD in
RXD in
Ext. trig 1 in
Ext. trig 1 in
Ext. Trig 2 in
Ext. Trig 2 in
Ground
Ground
CV-A33 CameraCamera Link Cable
Camera Link
Camera Link
Pin
Pin
A 0 Tx0
A 0 Tx0
A1 Tx1
A1 Tx1
A2 Tx2
A2 Tx2
A3 Tx3
A3 Tx3
A4 Tx4
A4 Tx4
A 5 Tx6
A 5 Tx6
A 6 Tx27
A 6 Tx27
A 7 Tx5
A 7 Tx5
B 0 Tx7
B 0 Tx7
B 1 Tx8
B 1 Tx8
B 2 Tx9
B 2 Tx9
B 3 Tx12
B 3 Tx12
B 4 Tx13
B 4 Tx13
B 5 Tx14
B 5 Tx14
B 6 Tx10
B 6 Tx10
B 7 Tx11
B 7 Tx11
C 0 Tx15
C 0 Tx15
C 1 Tx18
C 1 Tx18
C 2 Tx19
C 2 Tx19
C 3 Tx20
C 3 Tx20
C 4 Tx21
C 4 Tx21
C 5 Tx22
C 5 Tx22
C 6 TX16
C 6 TX16
C 7 Tx17
C 7 Tx17
Tx24
Tx24
Tx25
Tx25
Tx26
Tx26
Tx23
Tx23
Txclk
Txclk
4 x
4 x
7-1
7-1
MUX
MUX
Connector pin
Connector pin
15
15
2
2
16
16
3
3
17
17
4
4
19
19
6
6
18
18
5
5
21
21
8
8
7
7
20
20
22
22
9
9
10
10
23
23
24
24
11
11
12
12
25
25
1
1
14
14
13
13
26
26
X0
X0
X1
X1
X2
X2
X3
X3
Xclk
Xclk
SerTFG
SerTFG
SerTC
SerTC
CC1
CC1
CC2
CC2
CC3
CC3
CC4
CC4
Sheilds
Sheilds
TxCLK
TxOUT3
TxOUT2
TxOUT1
TxOUT0
Fig. 7. Principle diagram for Camera Link base configuration interface
Signal
Signal
Sheilds
Sheilds
Pair 1
Pair 1
Pair 2
Pair 2
Pair 3
Pair 3
Pair 5
Pair 5
Pair 4
Pair 4
Pair 7
Pair 7
Pair 6
Pair 6
Pair 8
Pair 8
Pair 9
Pair 9
Pair 10
Pair 10
Pair 11
Pair 11
A7
C3
B2
A1
Frame
Frame
Grabber
Grabber
A6
C2
B1
A0
To
To
EEN
DVAL
Port/Signal 8bit 10bit Pin No.
Port A0 D2 D0 Tx0
Port A1 D3 D1 Tx1
Port A2 D4 D2 Tx2
Port A3 D5 D3 Tx3
Port A4 D6 D4 Tx4
Port A5 D7 D5 Tx6
Port A6 D8 D6 Tx27
Port A7 D9 D7 Tx5
Port B0 NC D8 Tx7
Port B1 NC D9 Tx8
Port B2 NC NC Tx9
Port B3 NC NC Tx12
Port B4 NC NC Tx13
Port B5 NC NC Tx14
Port B6 NC NC Tx10
Port B7 NC NC Tx11
Port C0 NC NC Tx15
Port C1 NC NC Tx18
Port C2 NC NC Tx19
Port C3 NC NC Tx20
Port C4 NC NC Tx21
Port C5 NC NC Tx22
Port C6 NC NC Tx16
Port C7 NC NC Tx17
Camera Link bit allocation
LVAL Tx24
FVAL Tx25
DVAL Tx26
EEN Tx23
D0 = LSB. D9 = MSB
C7
FVAL
C0
C1
A5
B0
1 pixel cycl e
C6
LVAL
B5
A4
Timing
B6
B7
C4
C5
B3
B4
A2
A3
A6
A7
C2
C3
B1
B2
A0
A1
- 6 -
CV-A33CL
6. Functions and Operations
In the following the format shown in “7.3. CV-A33CL command list” are used for function
commands and parameters.
6.1. Basic functions
The CV-A33CL camera is a progressive scan camera with 10 or 8 bit video output in single
channel Camera Link.
Programmable partial scan, where the start line and the number of lines can be selected with 1
line increment is also available.
There are 4 modes: Normal continuous, and 3 trigger modes: Edge Pre-Select (EPS), Pulse Width
Control (PWC) and Auto Trigger.
The accumulation is LVAL a-synchronous.
In the following some of the functions are shown in details.
6.1.1. CMOS Sensor
The CMOS sensor principle layout is shown.
The sensor is an array of active photosensitive
R
pixels. The global shutter is working
simultaneously on all pixels. The readout can be
random row by row. 4 columns are feed through
a 4 to 1 multiplexer to an A/D converter. The
digitized row signals are placed in a vertical
register by a 1 to 4 multiplexing. From here it is
read out with the pixel clock pulses, even if the
window of interest has fewer columns. The
frame speed depends only of the height of the
window, not of the width.
Pixel principle and column processing with A/D
converting is shown below.
Control
Control
and
and
set up
set up
R
O
O
T
T
W
W
I
I
D
D
M
M
E
E
I
I
C
C
N
N
O
O
G
G
D
D
E
E
2 x 10 bit digital shift register
2 x 10 bit digital shift register
Fig. 7. CMOS principle layout
Pixel
Pixel
Column
Column
Process
Process
and A/D
and A/D
Video
Video
process
process
6.1.2. Pixel principle
Each pixel consists of a sensing part, a pixel memory
and an amplifier. The function can in short be
described. The photo diode and charge capacitor is
reset when switch 1 is closed. The signal accumulation
starts when sw 1 open. The charge is transferred to the
pixel memory capacitor when sw 2 close. The
accumulation stop when sw 2 open, and the signal is
now temporary stored in the memory capacitor. After
Start exposureStop exposure
Start exposureStop exposure
12
12
Light
Light
Photo
Photo
diode
diode
Charge
Charge
capacitor
capacitor
Pixel
Pixel
memory
memory
Read row
Read row
3
3
Reset
Reset
memory
memory
4
4
Buffer
Buffer
amplifier
amplifier
To column
To column
processing
processing
reset of the charge capacitor, a new accumulation can
start. The signal on the pixel memory capacitor is read
out to the column by the read row signal. The memory
Fig. 8. Pixel principle.
can now be reset.
With this construction all pixels will integrate at the same time, (Global shutter). The resulting
image is temporary stored in the pixel memory during read out, while a new exposure can be
started.
All timing is set up in the timing block by an internal serial link.
- 7 -
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