IXYS CPC5622-EVAL-600R, LITELINK III User Manual

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NTEGRATED CIRCUITS DIVISION

1. Introduction

CPC5622-EVAL-600R

LITELINK™ III Evaluation Board
User’s Guide

Thank you for using IXYS IC Division’s
CPC5622-EVAL-600R ev aluation board. The
evaluation board ships with the CPC5622A
LITELINK III and CPC5712U Voltage Monitor to
demonstrate the functionality of a PSTN terminating
two-wire interface that provides both the analog v oice
transmission and signaling functions. The analog
interface is configured to provide a 600 resistive AC
impedance with 0dB gain in both the transmit and
receive directions. While the CPC5622A provides the
hook-switch and ringing detect signaling functions, the
CPC5712U is utilized to monitor and detect changes
in the DC line voltage to determine loop status and
signaling information sent by the network. Loop status
is given by the logic level outputs of t he thr ee
CPC5712U on-board detectors indicating Loop
Presence, Line In Use, and Loop Polarity.

CPC5622-EVAL-600R ev aluation board top a nd
bottom views are shown in the following illustrations.

Figure 1. Evaluation Board Top View

Figure 2. Evaluation Board Bottom View

The printed-circuit board used for the
CPC5622-EVAL-600R eva luation board is a
multi-purpose board that facilitates prototyping of
many PSTN line interface configur ations by simple
component changes. Specific evaluation board
models provided by IXYS IC Division can be identified
by the label appended to the core part number
“CPC5622-EVAL-”. The suffix label “600R” as shown
in Figure 1 for this model indicates the two-wire AC
input impedance is 600. For the 600R model, the
transmit and receive gains are 0dB.

• 600R = 600 resistive AC termination with 0dB

transmit and receive gains.

In addition to the model identification label some
boards may hav e a second label located just belo w
the evaluation board part number indicating the
evaluatio n board’s serial number.

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NTEGRATED CIRCUITS DIVISION

LITELINK III Evaluation Board Users Guide

2. Setup and Using the Evaluation Board

This section describes setting up the CPC5622-EVAL-600R Evaluation Board prior to use.

2.1 Connections

The CPC5622-EV AL-600R evaluation board uses two
100 mil (2.54 mm) pitch pin headers, J1 and J2, for the
input and output connections. IXYS IC recommends
constructing header jumpers to bring the connections
out to your development or test platform. Connector

PSTN loop connections while J2, the 12-position pin
header, pro v ides access for the low voltage side
power, logic control, logic-level loop status detector
outputs and the analog transmit and receiv e voice
paths.

J1, the two-position pin header, provides access to the

Table 1: Telephone Network Access Connector - J1

Pin

Silk
Screen

Schematic
Name

Use

1 1 RING Connect to the Ring (B) lead of the telephone network or a loop simulator.

2 TIP Connect to the Tip (A) lead of the telephone network or a loop simulator.

Table 2: Low Voltage Side Power and Signal Connector - J2

Pin

Silk
Screen

1V+ VCC

Schematic
Name

Use

Power input: +3.3 V

or +5 V

DC

DC

2 TX- TX-_IN Inverting analog input to the LITELINK

3 TX+ TX+_IN Non-inver ting analog input to the LITELINK

4 RX- RX-_OUT Negative analog output from LITELINK

5 RX+ RX+_OUT Positive analog output from LITELINK

6 LOOP LOOP Loop Presence detector output

7 OH OH* Hook switch control. Off-Hook: OH* = 0, On-Hook: OH* = 1

8 RING2 RING2* Full-wave ringing detector output
9 RING RING* Half-wave ringing detector output

10 LIU LIU* Line In Use detector output

11 GND Low voltage side ground

12 POL POLARITY Polarity Detector output

NOTE: For clarity and con sistency with the schematic, the schematic names will be used from this point forward
throughout the text.

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NTEGRATED CIRCUITS DIVISION

LITELINK III Evaluation Board Users Guide

2.2 Using the Evaluation Board

Follow these guidelines for productive use of the LITELINK evaluation board:

• Evaluation board circuit components are sensitiv e to

electrostatic discharge (ESD). Use normal ESD
precautions when working with the LITELINK III
evaluation board.

• Make all low volt age side connections ( J2) to the

board before applying pow er to VCC.
Tip and Ring connections at J1 can be made at any
time before or after VCC power is applied.

• OH* should be open or tied to the VCC input power

pin during power up and held for 50us after power
up.

• Pulling OH* low will cause the CPC5622 to go

off-hook and returning OH* high will cause the unit to
go back on-hook.

3. Functional Description

• Analog transmission in both the transmit path and

the receive path is enabled while of f-hook. When
on-hook, only the receive path is enabled.

• For proper off-hook operation, t he Tip and Rin g

interface must be appropriately biased and
terminated.

• The CPC5622 RING* and RING2* ringing detectors

are only active while on-hook.

• The CPC5712U line voltage and polarity detectors

are active in both the on-hook and off-hook states .

The CPC5622-EVAL-600R provides the analog
interface and signaling functions necessary to
implement a PSTN two-wire terminating device f or
voice and data applications such as PBX FXO,
cordless telephones, FAX machines, set top boxes,
card readers, ATMs, and modems. Analog gains in
both the transmit and receive paths for the 600R
evaluation board are se t to 0dB with the impedance of
the two-wire interface conf igured for 600 ohms
resistive. These analog functions are provided by the
CPC5622A Phone Line Interface integrated circuit.
Additionally, the CPC5622A provides the basic
signaling functions of loop closure / loop open and
ringing detect that are required for a tw o-wire, current
sink, loop start interface. It is important to note that it is
not within the scope of this document to provide
complete behavioral descriptions of the CPC5622A or
the CPC5712U functions as this information is
covered in the data sheets and t he appropriate
application notes.

Basic signaling functions for a loop start, current sink
interface are loop closure (Off-Hook), loop open
(On-Hook) and ringing detect. Loop closure / open is
provided by the hook switch control function with
ringing detect provided by the Snoop input circuit and
the internal ringing detector. Additional loop voltage
detectors used to determine the line status are
provided by the CPC5712U Voltage Monitor with
Detectors integrated circuit. Line condition status
provided by the CPC5712U v oltage detectors are:
Line In Use (LIU), Loop battery presence (LOOP), and
Polarity. While these detectors are not required for the
most basic applications, they are required by the
majority and are therefor provided on the evaluation
board. Access to the analog paths and the detector
functions is provided by the two connectors J1 and J2.
Tip and Ring loop access is provided by J1 while J2
provides access to the low voltage side (SELV) po wer
and signals.

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NTEGRATED CIRCUITS DIVISION

LITELINK III Evaluation Board Users Guide

This evaluation board diff ers from pre viou s generation
evaluation boards by incorporating a common mode
noise cancellation circuit that improves longitudinal
balance and common mode rejection across the voice
band spectrum. This is accomplished by using a small
capacitance from shapes on the printed circuit board
(PCB) and modifications to the recommended passive
components values that set the analog transmission
parameters. Details in the construction of the PCB
capacitor are provided in the ev aluation board’s
printed circuit board design files available on line.

3.1 Connector J1 - Tip and Ring

Connector J1, the two-pin header, provides access to
the Tip and Ring (T/R) terminals of the evaluation
board. The Ring lead is located on pin 1 of the
connector and pin 2 is the Tip lead. Although the
board’s layout is designed for lightning and power
cross surge testing, the connector and it’s 25 mil
square pins are not rated for the peak voltages or
currents specified in the safety regulations. It is
suggested the connector be removed and lead wires
be soldered to the board when performing these tests.

3.2 Connector J2 - Low Voltage Side Interface

ended, short one of the input pins to ground and apply
the analog signal to the other input. Typically, TX- is
shorted to ground and the signal is applied to TX+. For
single ended applications, the maximum input signal is
still 0dBm. (This is 1.095Vp.)

Pin 4: RX-_OUT
Pin 5: RX+_OUT

Pins 4 and 5 are the analog voice negative (RX-) and
positive (RX+) differential outputs for the receive path
(T/R to SELV). The maximum output signal by these
pins is 0dBm. This is 0.548Vp on each output.
For single ended receiv e applications, connect one of
the output pins to the receiver input pin and le ave the
other output open. This will result in a receive pat h
loss of 6dB.

Pin 6: LOOP

This is a logic level output indicating the presence of
loop battery feed from the network. For tip to ring
voltages greater than approximately +/-5V

DC

the

detector will output a logic high (LOOP = 1) and for
T/R voltages less than approximately +/-3V

DC

the

detector will output a logic low (LOOP = 0). The LOOP
detector is polarity insensitive.

Providing access to the low v oltage side analog and
digital interface is connector J2, a single row 12-pin
header connector with 25 mil square pins on 100 mil
centers. Due to space limitations, the silkscreen pin
names where modified slightly from the net names
shown on the schematic. These naming differences
are shown in Table 1 and Table 2 on Page 2.

Pin 1: VCC

Po w er pin for the low voltage (SELV) side circuits.
Apply a nominal 3.3V

or 5VDC with respect to the

DC

ground (GND) connection at Pin 11.

Pin 2: TX-_IN
Pin 3: TX+_IN

Pins 2 and 3 are the analog voice negativ e ( TX-) and
positive (TX+) diff er ential in puts for the transmit path
(SELV to T/R). The maximum signal applied to these
input pins is 0dBm. (This is 0.548Vp on each input.)
For applications where the analog source is single

Pin 7: OH*

OH* is an active low, TTL compatible, logic level in put
used to control the hook switch function of the T/R
network interface. Applying a logic low (OH* = 0) at
this pin will enable the gyrator located on the line side
causing DC current to flow. This is commonly referred
to as the “Off-Hook” state. The gyrator, an electronic
inductor, has a low impedance at DC but a high
impedance in the voice band allowing the two-wire
interface to draw DC loop current without loading the
AC termination. An On-Hook state occurs when
OH* = 1 and loop current ceases.

The OH* net is connected to the OH

input at pin 8 of
the CPC5622A. The CPC5622A requires this input to
be left open or pulled high to VCC during power up
and for a minimum dur ation of 50us following power
up. An internal pull-up resistor at the OH

input
provides the required logic high when the input is left
open.

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