ITE IT8718F Specification

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IT8718F

Environment Control – Low Pin Count Input / Output

(EC - LPC I/O)

Preliminary Specification V0.3

ITE TECH. INC.

Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives.

Please note that the IT8718F V0.3 is applicable to C version and future versions.

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This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this document.

All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this document.

ITE, IT8718F is a trademark of ITE Tech. Inc. Intel is claimed as a trademark by Intel Corp.

Microsoft and Windows are claimed as trademarks by Microsoft Corporation. PCI is claimed as a trademark by the PCI Special Interest Group. IrDA is claimed as a trademark by the Infrared Data Association. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice.

Additional copies of this manual or other ITE literature may be obtained from:

ITE Tech. Inc. Phone: (02) 29126889 Marketing Department Fax: (02) 2910-2551, 2910-2552

8F, No. 233-1, Bao Chiao RD., Hsin Tien, Taipei County 231, Taiwan, R.O.C.

If you have any marketing or sales questions, please contact:

P.Y. Chang, at ITE Taiwan: E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052,

Fax: 886-2-29102551

To find out more about ITE, visit our World Wide Web at:

http://www.ite.com.tw Or e-mail itesupport@ite.com.tw for more product information/services

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Revision History

Section Revision Page No.

• Table 4-1. Pins Listed in Numeric Order was revised.

• Table 5-3. Pin Description of GPI/O Signals was revised.

• In Table 5-6. Pin Description of Infrared Port Signals, added the third and

fourth functions for pin 66.

• In Table 6-4. General Purpose I/O Group 4 (Set 4), pin 66 was revised.

• Table 7-1. Power On Strapping Options was revised.

• Table 8-1. Global Configuration Registers was revised.

• Table 8-9. GPIO Configuration Registers was revised.

• Table 8-10. GPIO Configuration Registers was revised.

• In 8.3.5 Configuration Select and Chip Version (Index=22h,

Default=01h), the default value was revised from “00h” to “01h” and

added “0001b for C version” to the description of bit 3-0.

• In 8.3.6 Clock Selection Register (Index=23h, Default=00h), added

“Powered by VSB” to the description of bit 3-2.

• In 8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h,

Default=00h), the description of bit 0 was revised as “VIDO7” at 0.

• In 8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh), the description of bit 6 and bit 2 was revised.

• In 8.8.10 Environment Controller Special Configuration Register (Index=F3h, Default=00h), the description of bit 7-1 was revised.

• In 8.11.13 GPIO Pin Set 1, 3, 4, 5 and 6 Pin Internal Pull-up Enable Registers (Index=B8h, BAh, BBh, BCh and BDh, Default=00h), there is

no internal P/U function for GPIO set 2.

• In 8.11.14 Simple I/O Set 1, 2, 3, 4, 5 and 6 Enable Registers (Index=C0h, C1h, C2h, C3h C4 and C5h, Default=01h, 00h, 00h, 40h,

00h and 00h), added Simple I/O Set 6 Enable Register.

• In 8.12.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h), the Location mapping table of note 4 was revised.

• In 9.6.2.2.38 Beep Event Enable Register (Index=5Ch, Default=00h), the description of bit 6-4 was revised.

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Contents

CONTENTS

1. Features ....................................................................................................................................................... 1

2. General Description ....................................................................................................................................... 3

3. Block Diagram................................................................................................................................................ 5

4. Pin Configuration ........................................................................................................................................... 7

5. IT8718F Pin Descriptions .............................................................................................................................. 9

6. List of GPIO Pins ......................................................................................................................................... 23

7. Power On Strapping Options and Special Pin Routings ............................................................................. 27

8. Configuration .............................................................................................................................................. 29

8.1 Configuring Sequence Description ................................................................................................... 29

8.2 Description of the Configuration Registers ....................................................................................... 30

8.2.1 Logical Device Base Address .............................................................................................. 35

8.3 Global Configuration Registers (LDN: All) ........................................................................................ 36

8.3.1 Configure Control (Index=02h)............................................................................................. 36

8.3.2 Logical Device Number (LDN, Index=07h) .......................................................................... 36

8.3.3 Chip ID Byte 1 (Index=20h, Default=87h) ............................................................................ 36

8.3.4 Chip ID Byte 2 (Index=21h, Default=18h) ............................................................................ 36

8.3.5 Configuration Select and Chip Version (Index=22h, Default=01h) ...................................... 36

8.3.6 Clock Selection Register (Index=23h, Default=00h)............................................................ 36

8.3.7 Software Suspend and Flash I/F Control Register (Index=24h, Default=00s0s0s0b, MB

PnP)...................................................................................................................................... 37

8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h) .................... 38

8.3.9 GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h) .................... 39

8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h) .................... 39

8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h) .................... 40

8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h) .................... 41

8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h) .................... 41

8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h) ...................................................... 42

8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh).................... 43

8.3.16 Test 1 Register (Index=2Eh, Default=00h) .......................................................................... 43

8.3.17 Test 2 Register (Index=2Fh, Default=00h)........................................................................... 43

8.4 FDC Configuration Registers (LDN=00h) ......................................................................................... 44

8.4.1 FDC Activate (Index=30h, Default=00h) .............................................................................. 44

8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h) ............................................. 44

8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h).............................................. 44

8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h)......................................................... 44

8.4.5 FDC DMA Channel Select (Index=74h, Default=02h) ......................................................... 44

8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h)....................................... 44

8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h)....................................... 45

8.5 Serial Port 1 Configuration Registers (LDN=01h) ............................................................................ 46

8.5.1 Serial Port 1 Activate (Index=30h, Default=00h).................................................................. 46

8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) .................................. 46

8.5.3 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h) ................................... 46

8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h) ............................................46

8.5.5 Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 46

8.5.6 Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h) .......................... 47

8.6 Serial Port 2 Configuration Registers (LDN=02h) ............................................................................ 48

8.6.1 Serial Port 2 Activate (Index=30h, Default=00h).................................................................. 48

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8.6.2 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) .................................. 48

8.6.3 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h) ................................... 48

8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) ............................................48

8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 48

8.6.6 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h) .......................... 49

8.7 Parallel Port Configuration Registers (LDN=03h)............................................................................. 50

8.7.1 Parallel Port Activate (Index=30h, Default=00h).................................................................. 50

8.7.2 Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)..................... 50

8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h) .................... 50

8.7.4 Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)................ 50

8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h) ............... 50

8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h) ........................................... 50

8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h) ............................................. 50

8.7.8 Parallel Port Special Configuration Register (Index=F0h, Default=03h) ............................. 51

8.8 Environment Controller Configuration Registers (LDN=04h) ...........................................................52

8.8.1 Environment Controller Activate Register (Index=30h, Default=00h) .................................. 52

8.8.2 Environment Controller Base Address MSB Register (Index=60h, Default=02h) ................. 52

8.8.3 Environment Controller Base Address LSB Register (Index=61h, Default=90h) .................. 52

8.8.4 PME Direct Access Base Address MSB Register (Index=62h, Default=02h) ....................... 52

8.8.5 PME Direct Access Base Address LSB Register (Index=63h, Default=30h) ........................ 52

8.8.6 Environment Controller Interrupt Level Select (Index=70h, Default=09h) ........................... 52

8.8.7 APC/PME Event Enable Register (PER) (Index=F0h, Default=00h) ................................... 52

8.8.8 APC/PME Status Register (PSR) (Index=F1h, Default=00h) ..............................................53

8.8.9 APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)....................................... 53

8.8.10 Environment Controller Special Configuration Register (Index=F3h, Default=00h) ............ 54

8.8.11 APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h)....................................... 54

8.8.12 APC/PME Special Code Index Register (Index=F5h).......................................................... 54

8.8.13 APC/PME Special Code Data Register (Index=F6h)........................................................... 54

8.9 KBC (keyboard) Configuration Registers (LDN=05h)....................................................................... 55

8.9.1 KBC (keyboard) Activate (Index=30h, Default=01h)............................................................ 55

8.9.2 KBC (keyboard) Data Base Address MSB Register (Index=60h, Default=00h) .................. 55

8.9.3 KBC (keyboard) Data Base Address LSB Register (Index=61h, Default=60h) ................... 55

8.9.4 KBC (keyboard) Command Base Address MSB Register (Index=62h, Default=00h)......... 55

8.9.5 KBC (keyboard) Command Base Address LSB Register (Index=63h, Default=64h).......... 55

8.9.6 KBC (keyboard) Interrupt Level Select (Index=70h, Default=01h) ...................................... 55

8.9.7 KBC (keyboard) Interrupt Type (Index=71h, Default=02h) .................................................. 55

8.9.8 KBC (keyboard) Special Configuration Register (Index=F0h, Default=08h) ............................ 56

8.10 KBC (mouse) Configuration Registers (LDN=06h)........................................................................... 57

8.10.1 KBC (mouse) Activate (Index=30h, Default=00h)................................................................ 57

8.10.2 KBC (mouse) Interrupt Level Select (Index=70h, Default=0Ch) ............................................. 57

8.10.3 KBC (mouse) Interrupt Type (Index=71h, Default=02h) ...................................................... 57

8.10.4 KBC (mouse) Special Configuration Register (Index=F0h, Default=00h) ........................... 57

8.11 GPIO Configuration Registers (LDN=07h) ....................................................................................... 57

8.11.1 SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)........... 57

8.11.2 SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)............ 57

8.11.3 Simple I/O Base Address MSB Register (Index=62h, Default=00h).................................... 58

8.11.4 Simple I/O Base Address LSB Register (Index=63h, Default=00h)..................................... 58

8.11.5 Serial Flash I/F Base Address MSB Register (Index=64h, Default=00h) ............................ 58

8.11.6 Serial Flash I/F Base Address LSB Register (Index=65h, Default=00h) ............................. 58

8.11.7 Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h) .......... 58

8.11.8 Watch Dog Timer Control Register (Index=71h, Default=00h) ............................................ 58

8.11.9 Watch Dog Timer Configuration Register (Index=72h, Default=001s0000b) ...................... 59

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8.11.10 Watch Dog Timer Time-Out Value (LSB) Register (Index=73h, Default=38h) .................... 59

8.11.11 Watch Dog Timer Time-Out Value (MSB) Register (Index=74h, Default=00h) ................... 59

8.11.12 GPIO Pin Set 1, 2, 3, 4, 5 and 6 Polarity Registers (Index=B0h, B1h, B2h, B3h, B4h and

B5h, Default=00h) ................................................................................................................ 59

8.11.13 GPIO Pin Set 1, 3, 4, 5 and 6 Pin Internal Pull-up Enable Registers (Index=B8h, BAh, BBh,

BCh and BDh, Default=00h)................................................................................................. 59

8.11.14 Simple I/O Set 1, 2, 3, 4, 5 and 6 Enable Registers (Index=C0h, C1h, C2h, C3h C4 and

C5h, Default=01h, 00h, 00h, 40h, 00h and 00h).................................................................. 60

8.11.15 Simple I/O Set 1, 2, 3, 4, 5 and 6 Output Enable Registers (Index=C8h, C9h, CAh, CBh,

CCh and CDh, Default=01h, 00h, 00h, 40h, 00h and 00h).................................................. 60

8.11.16 Panel Button De-bounce 0 Input Pin Mapping Registers (Index=E0h, Default=00h).......... 60

8.11.17 Panel Button De-bounce 1 Input Pin Mapping Registers (Index=E1h, Default=00h).......... 60

8.11.18 IRQ External Routing 1-0 Input Pin Mapping Registers (Index=E3h-E2h, Default=00h) .... 60

8.11.19 IRQ External Routing 1-0 Interrupt Level Selection Register (Index=E4h, Default=00h).... 60

8.11.20 VID Watchdog timer 0 Value Register (Index=E5h, Default=00h)....................................... 61

8.11.21 VID Watchdog timer 1 Value Register (Index=E6h, Default=00h)....................................... 61

8.11.22 SMI# Control Register 1 (Index=F0h, Default=00h)............................................................. 61

8.11.23 SMI# Control Register 2 (Index=F1h, Default=00h)............................................................. 61

8.11.24 SMI# Status Register 1 (Index=F2h, Default=00h) .............................................................. 62

8.11.25 SMI# Status Register 2 (Index=F3h, Default=00h) .............................................................. 62

8.11.26 SMI# Pin Mapping Register (Index=F4h, Default=00h) ....................................................... 62

8.11.27 Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h) ........ 62

8.11.28 Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h)................. 62

8.11.29 Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h) ....................................... 63

8.11.30 GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h).................................. 63

8.11.31 GP LED Blinking 1 Control Register (Index=F9h, Default=00h) .......................................... 63

8.11.32 GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h) .................................. 63

8.11.33 GP LED Blinking 2 Control Register (Index=FBh, Default=00h).......................................... 63

8.11.34 VID Input Register (Index=FCh, Default=--h)....................................................................... 64

8.11.35 VID Output/Programed Output Register (Index=FDh, Default=00h) ................................... 64

8.11.36 VID Watchdog timer Control Register (Index=FEh, Default=00h) ....................................... 64

8.11.37 VID Watchdog timer Control Register (Index=FFh, Default=00h) ....................................... 64

8.12 Consumer IR Configuration Registers (LDN=0Ah)........................................................................... 66

8.12.1 Consumer IR Activate (Index=30h, Default=00h) ................................................................ 66

8.12.2 Consumer IR Base Address MSB Register (Index=60h, Default=03h)................................. 66

8.12.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h).................................. 66

8.12.4 Consumer IR Interrupt Level Select (Index=70h, Default=0Bh) .......................................... 66

8.12.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h)............................ 66

9. Functional Description ................................................................................................................................. 69

9.1 LPC Interface .................................................................................................................................... 69

9.1.1 LPC Transactions................................................................................................................. 69

9.1.2 LDRQ# Encoding ................................................................................................................. 69

9.2 Serialized IRQ................................................................................................................................... 69

9.2.1 Continuous Mode ................................................................................................................. 69

9.2.2 Quiet Mode........................................................................................................................... 70

9.2.3 Waveform Samples of SERIRQ Sequence.......................................................................... 70

9.2.4 SERIRQ Sampling Slot ........................................................................................................ 71

9.3 General Purpose I/O ......................................................................................................................... 72

9.4 Advanced Power Supply Control and Power Management Event (PME#) ...................................... 74

9.5 SPI Serial Flash Controller................................................................................................................ 75

9.5.1 Overview............................................................................................................................... 75

9.5.2 Features ............................................................................................................................... 75

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9.5.3 Register Descriptions ........................................................................................................... 75

9.5.3.1 Control Register (SPI_CTRL) .................................................................................. 75

9.5.3.2 Command Register (SPI_CMD) .............................................................................. 76

9.5.3.3 Address 0 Register (SPI_ADDR0) .......................................................................... 76

9.5.3.4 Address 1 Register (SPI_ADDR1) .......................................................................... 76

9.5.3.5 Address 2 Register (SPI_ADDR2) .......................................................................... 76

9.5.3.6 Input Data 0 Register (SPI_IDATA0)....................................................................... 76

9.5.3.7 Input Data 1 Register (SPI_IDATA1)....................................................................... 77

9.5.3.8 Output Data/Input Data 2 Register (SPI_ODATA/ SPI_IDATA2)............................ 77

9.5.4 Function Descriptions........................................................................................................... 77

9.6 Environment Controller ..................................................................................................................... 79

9.6.1 Interfaces.............................................................................................................................. 79

9.6.2 Registers .............................................................................................................................. 79

9.6.2.1 Address Port (Base+05h, Default=00h) .................................................................. 79

9.6.2.2 Register Description ................................................................................................ 83

9.6.2.2.1 Configuration Register (Index=00h, Default=18h) ........................... 83

9.6.2.2.2 Interrupt Status Register 1 (Index=01h, Default=00h)..................... 84

9.6.2.2.3 Interrupt Status Register 2 (Index=02h, Default=00h)..................... 84

9.6.2.2.4 Interrupt Status Register 3 (Index=03h, Default=00h)..................... 84

9.6.2.2.5 SMI# Mask Register 1 (Index=04h, Default=00h) ........................... 84

9.6.2.2.6 SMI# Mask Register 2 (Index=05h, Default=00h) ........................... 84

9.6.2.2.7 SMI# Mask Register 3 (Index=06h, Default=00h) ........................... 84

9.6.2.2.8 Interrupt Mask Register 1 (Index=07h, Default=00h) ...................... 85

9.6.2.2.9 Interrupt Mask Register 2 (Index=08h, Default=00h) ...................... 85

9.6.2.2.10 Interrupt Mask Register 3 (Index=09h, Default=80h) ...................... 85

9.6.2.2.11 Interface Selection Register (Index=0Ah, Default=40h) .................. 85

9.6.2.2.12 Fan PWM Smoothing Step Frequency Selection Register

(Index=0Bh, Default=09h) .........................................................................................

9.6.2.2.13 Fan Tachometer 16-bit Counter Enable Register (Index=0Ch,

Default=00h) ..................................................................................................... 86

9.6.2.2.14 Fan Tachometer 1-3 Reading Registers (Index=0Dh-0Fh) ............. 86

9.6.2.2.15 Fan Tachometer 1-3 Limit Registers (Index=10h-12h).................... 86

9.6.2.2.16 Fan Controller Main Control Register (Index=13h, Default=07h) .... 87

9.6.2.2.17 FAN_CTL Control Register (Index=14h, Default=50h).................... 87

9.6.2.2.18 FAN_CTL1 PWM Control Register (Index=15h,

Default=00h/20h/40h/60h) ..................................................................................... 87

9.6.2.2.19 FAN_CTL2 PWM Control Register (Index=16h,

Default=00h/20h/40h/60h) ..................................................................................... 88

9.6.2.2.20 FAN_CTL3 PWM Control Register (Index=17h,

Default=00h/20h/40h/60h) ..................................................................................... 88

9.6.2.2.21 Fan Tachometer 1-3 Extended Reading Registers (Index=18h-1Ah) .

..................................................................................................... 88

9.6.2.2.22 Fan Tachometer 1-3 Extended Limit Registers (Index=1Bh-1Dh) .. 88

9.6.2.2.23 VIN7-VIN0 Voltage Reading Registers (Index=27h-20h) ................ 88

9.6.2.2.24 VBAT Voltage Reading Register (Index=28h) ................................. 89

9.6.2.2.25 TMPIN3-1 Temperature Reading Registers (Index=2Bh-29h) ........ 89

9.6.2.2.26 VIN7-0 Low Limit Registers (Index=3Fh, 3Dh, 3Bh, 39h, 37h, 35h,

33h, 31h) ..................................................................................................... 89

9.6.2.2.27 TMPIN3-1 High Limit Registers (Index=44h, 42h, 40h)................... 89

9.6.2.2.28 TMPIN3-1 Low Limit Registers (Index=45h, 43h, 41h).................... 89

9.6.2.2.29 ADC Voltage Channel Enable Register (Index=50h, Default=00h). 89

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9.6.2.2.30 ADC Temperature Channel Enable Register (Index=51h,

Default=00h) ..................................................................................................... 89

9.6.2.2.31 TMPIN3-1 Thermal Output Limit Registers (Index=54h-52h,

Default=7Fh) ..................................................................................................... 90

9.6.2.2.32 ADC Temperature Extra Channel Enable Register (Index=55h,

Default=00h) ..................................................................................................... 90

9.6.2.2.33 Thermal Diode Zero Degree Adjust 1 Register (Index=56h,

Default=00h) ..................................................................................................... 90

9.6.2.2.34 Thermal Diode Zero Degree Adjust 2 Register (Index=57h,

Default=00h) ..................................................................................................... 90

9.6.2.2.35 Vendor ID Register (Index=58h, Default=90h) ................................ 90

9.6.2.2.36 Thermal Diode Zero Degree Adjust 3 Register (Index=59h,

Default=00h) ..................................................................................................... 90

9.6.2.2.37 Code ID Register (Index=5Bh, Default=12h) ................................... 91

9.6.2.2.38 Beep Event Enable Register (Index=5Ch, Default=00h) ................. 91

9.6.2.2.39 Beep Frequency Divisor of Fan Event Register (Index=5Dh,

Default=00h) ..................................................................................................... 91

9.6.2.2.40 Beep Frequency Divisor of Voltage Event Register (Index=5Eh,

Default=00h) ..................................................................................................... 91

9.6.2.2.41 Beep Frequency Divisor of Temperature Event Register (Index=5Fh,

Default=00h) ..................................................................................................... 91

9.6.2.2.42 FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of

OFF Registers (Index=70h, 68h, 60h, Default=7Fh)............................................. 91

9.6.2.2.43 FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of

Fan Start Registers (Index=71h, 69h, 61h, Default=7Fh) .....................................92

9.6.2.2.44 FAN_CTL3-1 SmartGuardian Automatic Mode Start PWM Registers

(Index=73h, 6Bh, 63h, Default=00h) ..................................................................... 92

9.6.2.2.45 FAN_CTL3-1 SmartGuardian Automatic Mode Control Registers

(Index=74h, 6Ch, 64h, Default=00h) ..................................................................... 92

9.6.2.2.46 FAN_CTL3-1 SmartGuardian Automatic Mode △ -Temperature

Registers (Index=75h, 6Dh, 65h, Default=7Fh).................................................. 92

9.6.2.2.47 Fan Tachometer 4-5 Reading LSB Registers (Index=80h,82h) ...... 92

9.6.2.2.48 Fan Tachometer 4-5 Reading MSB Registers (Index=81h,83h) ..... 92

9.6.2.2.49 Fan Tachometer 4-5 Limit LSB Registers (Index=84h,86h) ............ 93

9.6.2.2.50 Fan Tachometer 4-5 Limit MSB Registers (Index=85h,87h) ........... 93

9.6.2.2.51 External Temperature Sensor Host Status Register (Index=88h,

Default=---00000b) ................................................................................................ 93

9.6.2.2.52 External Temperature Sensor Host Target Addess Register

(Index=89h, Default=00h)...................................................................................... 94

9.6.2.2.53 External Temperature Sensor Host Write Length Register

(Index=8Ah, Default=00h) ..................................................................................... 94

9.6.2.2.54 External Temperature Sensor Host Read Length Register

(Index=8Bh, Default=00h) ..................................................................................... 94

9.6.2.2.55 External Temperature Sensor Host Command (Write Data 1)

9.6.2.2.56 External Temperature Sensor Write Data (2-8) Register (Index=8Dh,

Default=--h) ..................................................................................................... 94

9.6.2.2.57 External Temperature Sensor Host Control Register (Index=8Eh,

Default=00h) ..................................................................................................... 94

9.6.2.2.58 External Temperature Sensor Read Data (1-16) Register

(Index=8Fh, Default=--h) ...........................................................................................

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9.6.2.2.59 Special FAN Control Mode Extra Vector A, B Temperature Limit of

Fan Start Registers (Index=90h, 94h, Default=FFh) ............................................. 95

9.6.2.2.60 Special FAN Control Mode Extra Vector A, B Slope Registers

(Index=91h, 95h, Default=00h).............................................................................. 95

9.6.2.2.61 Special FAN Control Mode Extra Vector A, B △ -Temperature

Registers (Index=92h, 96h, Default=00h) ............................................................. 96

9.6.3 Operation.............................................................................................................................. 96

9.6.3.1 Power On RESET and Software RESET ................................................................96

9.6.3.2 Starting Conversion ................................................................................................. 96

9.6.3.3 Voltage and Temperature Inputs ............................................................................. 98

9.6.3.4 Layout and Grounding ............................................................................................. 98

9.6.3.5 Fan Tachometer ...................................................................................................... 99

9.6.3.6 Interrupt of the EC ................................................................................................... 99

9.6.3.7 FAN Controller FAN_CTL’s ON-OFF and SmartGuardian Modes........................ 100

9.7 Floppy Disk Controller (FDC).......................................................................................................... 102

9.7.1 Introduction......................................................................................................................... 102

9.7.2 Reset .................................................................................................................................. 102

9.7.3 Hardware Reset (LRESET# Pin)........................................................................................ 102

9.7.4 Software Reset (DOR Reset and DSR Reset)................................................................... 102

9.7.5 Digital Data Separator ........................................................................................................ 102

9.7.6 Write Precompensation...................................................................................................... 102

9.7.7 Data Rate Selection ........................................................................................................... 103

9.7.8 Status, Data and Control Registers.................................................................................... 103

9.7.8.1 Digital Output Register (DOR, FDC Base Address + 02h).................................... 103

9.7.8.2 Tape Drive Register (TDR, FDC Base Address + 03h) ........................................ 103

9.7.8.3 Main Status Register (MSR, FDC Base Address + 04h) ...................................... 104

9.7.8.4 Data Rate Select Register (DSR, FDC Base Address + 04h)............................... 104

9.7.8.5 Data Register (FIFO, FDC Base Address + 05h).................................................. 105

9.7.8.6 Digital Input Register (DIR, FDC Base Address + 07h) ........................................ 106

9.7.8.7 Diskette Control Register (DCR, FDC Base Address + 07h) ................................ 106

9.7.9 Controller Phases............................................................................................................... 106

9.7.9.1 Command Phase ................................................................................................... 106

9.7.9.2 Execution Phase.................................................................................................... 106

9.7.9.3 Result Phase ......................................................................................................... 107

9.7.9.4 Result Phase Status Registers.............................................................................. 107

9.7.10 Command Set .................................................................................................................... 109

9.7.11 Data Transfer Commands.................................................................................................. 119

9.7.11.1 Read Data.............................................................................................................. 119

9.7.11.2 Read Deleted Data ................................................................................................ 119

9.7.11.3 Read a Track ......................................................................................................... 120

9.7.11.4 Write Data.............................................................................................................. 120

9.7.11.5 Write Deleted Data ................................................................................................ 120

9.7.11.6 Format A Track ...................................................................................................... 120

9.7.11.7 SCAN ..................................................................................................................... 121

9.7.11.8 VERIFY .................................................................................................................. 122

9.7.12 Control Commands ............................................................................................................ 122

9.7.12.1 READ ID ................................................................................................................123

9.7.12.2 Configure ...............................................................................................................123

9.7.12.3 RE-CALIBRATE..................................................................................................... 123

9.7.12.4 SEEK ..................................................................................................................... 124

9.7.12.5 RELATIVE SEEK................................................................................................... 124

9.7.12.6 DUMPREG ............................................................................................................ 124

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Contents

9.7.12.7 LOCK ..................................................................................................................... 124

9.7.12.8 VERSION............................................................................................................... 124

9.7.12.9 SENSE INTERRUPT STATUS.............................................................................. 125

9.7.12.10 SENSE DRIVE STATUS .......................................................................................125

9.7.12.11 SPECIFY ............................................................................................................... 125

9.7.12.12 PERPENDICULAR MODE .................................................................................... 126

9.7.12.13 INVALID................................................................................................................. 127

9.7.13 DMA Transfers ................................................................................................................... 127

9.7.14 Low Power Mode................................................................................................................ 127

9.8 Serial Port (UART) Description ....................................................................................................... 128

9.8.1 Data Registers.................................................................................................................... 128

9.8.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR and MCR ........................................... 128

9.8.3 Status Registers: LSR and MSR........................................................................................ 134

9.8.4 Reset .................................................................................................................................. 136

9.8.5 Programming...................................................................................................................... 136

9.8.6 Software Reset................................................................................................................... 136

9.8.7 Clock Input Operation......................................................................................................... 136

9.8.8 FIFO Interrupt Mode Operation.......................................................................................... 137

9.9 Parallel Port..................................................................................................................................... 138

9.9.1 SPP and EPP Modes ......................................................................................................... 138

9.9.2 EPP Mode Operation ......................................................................................................... 140

9.9.3 ECP Mode Operation ......................................................................................................... 141

9.10 Keyboard Controller (KBC) ............................................................................................................. 147

9.10.1 Host Interface ..................................................................................................................... 148

9.10.2 Data Registers and Status Register................................................................................... 148

9.10.3 Keyboard and Mouse Interface .......................................................................................... 149

9.10.4 KIRQ and MIRQ .................................................................................................................149

9.11 Consumer Remote Control (TV Remote) IR (CIR) ......................................................................... 150

9.11.1 Overview............................................................................................................................. 150

9.11.2 Features .............................................................................................................................150

9.11.3 Block Diagram .................................................................................................................... 150

9.11.4 Transmit Operation............................................................................................................. 151

9.11.5 Receive Operation.............................................................................................................. 151

9.11.6 Register Descriptions and Address.................................................................................... 151

9.11.6.1 CIR Data Register (DR)......................................................................................... 152

9.11.6.2 CIR Interrupt Enable Register (IER)...................................................................... 152

9.11.6.3 CIR Receiver Control Register (RCR)................................................................... 153

9.11.6.4 CIR Transmitter Control Register 1 (TCR1) .......................................................... 154

9.11.6.5 CIR Transmitter Control Register (TCR2) ............................................................. 155

9.11.6.6 CIR Baud Rate Divisor Low Byte Register (BDLR)............................................... 158

9.11.6.7 CIR Baud Rate Divisor High Byte Register (BDHR) ............................................. 158

9.11.6.8 CIR Transmitter Status Register (TSR)................................................................. 158

9.11.6.9 CIR Receiver FIFO Status Register (RSR) ...........................................................159

9.11.6.10 CIR Interrupt Identification Register (IIR) .............................................................. 159

10. DC Electrical Characteristics ..................................................................................................................... 161

11. AC Characteristics (VCC = 5V ± 5%, Ta = 0°C to + 70°C) ....................................................................... 163

11.1 Clock Input Timings ........................................................................................................................ 163

11.2 LCLK (PCICLK) and LRESET Timings........................................................................................... 163

11.3 LPC and SERIRQ Timings.............................................................................................................. 164

11.4 Serial Port, ASKIR, SIR and Consumer Remote Control Timings ................................................. 165

11.5 Modem Control Timings.................................................................................................................. 165

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11.6 Floppy Disk Drive Timings .............................................................................................................. 166

11.7 EPP Address or Data Write Cycle Timings..................................................................................... 167

11.8 EPP Address or Data Read Cycle Timings .................................................................................... 168

11.9 ECP Parallel Port Forward Timings ................................................................................................ 168

11.10 ECP Parallel Port Backward Timings................................................................................. 169

11.11 RSMRST#, PWROK1/2, and ACPI Power Control Signals Timings ................................. 169

12. Package Information.................................................................................................................................. 171

13. Ordering Information.................................................................................................................................. 173

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Contents

FIGURES

Figure 7-1. IT8718F Special Applications Circuitry for Intel ICH ..................................................................... 28

Figure 9-1. Start Frame Timing ......................................................................................................................... 70

Figure 9-2. Stop Frame Timing ......................................................................................................................... 70

Figure 9-3. General Logic of GPIO Function .................................................................................................... 73

Figure 9-4. Application Example. Resistor should provide approximately 2V at the Analog Inputs. ................ 97

Figure 9-5. Temperature Interrupt Response Diagram................................................................................... 100

Figure 9-6. SmartGuardian Automatic Mode .................................................................................................. 101

Figure 9-7. Keyboard and Mouse Interface .................................................................................................... 147

Figure 9-8. CIR Block Diagram ....................................................................................................................... 150

Figure 11-1. Clock Input Timings .................................................................................................................... 163

Figure 11-2. LCLK (PCICLK) and LRESET Timings....................................................................................... 163

Figure 11-3. LPC and SERIRQ Timings ......................................................................................................... 164

Figure 11-4. Serial Port, ASKIR, SIR and Consumer Remote Control Timings ............................................. 165

Figure 11-5. Modem Control Timings ............................................................................................................. 165

Figure 11-6. Floppy Disk Drive Timings.......................................................................................................... 166

Figure 11-7. EPP Address or Data Write Cycle Timings ................................................................................ 167

Figure 11-8. EPP Address or Data Read Cycle Timings ................................................................................ 168

Figure 11-9. ECP Parallel Port Forward Timings............................................................................................ 168

Figure 11-10. ECP Parallel Port Backward Timings ....................................................................................... 169

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TABLES

Table 4-1. Pins Listed in Numeric Order............................................................................................................. 8

Table 5-1. Pin Description of Supplies Signals ................................................................................................... 9

Table 5-2. Pin Description of LPC Bus Interface Signals ................................................................................... 9

Table 5-3. Pin Description of GPI/O Signals..................................................................................................... 10

Table 5-4. Pin Description of Hardware Monitor Signals

Table 5-5. Pin Description of Fan Controller Signals........................................................................................ 13

Table 5-6. Pin Description of Infrared Port Signals........................................................................................... 13

Table 5-7. Pin Description of Serial Port 1 Signals ........................................................................................... 15

Table 5-8. Pin Description of Serial Port 2 Signals ........................................................................................... 16

Table 5-9. Pin Description of Parallel Port Signals ........................................................................................... 17

Table 5-10. Pin Description of Floppy Disk Controller Signals ......................................................................... 18

Table 5-11. Pin Description of GPIO function ................................................................................................... 19

Table 5-12. Pin Description of Keyboard Controller Signals............................................................................. 20

Table 5-13. Pin Description of Miscellaneous Signals...................................................................................... 20

Table 6-1. General Purpose I/O Group 1 (Set 1) .............................................................................................. 23

Table 6-2. General Purpose I/O Group 2 (Set 2) .............................................................................................. 23

Table 6-3. General Purpose I/O Group 3 (Set 3) .............................................................................................. 24

Table 6-4. General Purpose I/O Group 4 (Set 4) .............................................................................................. 24

Table 6-5. General Purpose I/O Group 5 (Set 5) .............................................................................................. 25

Table 6-6. General Purpose I/O Group 6 (Set 6) .............................................................................................. 25

Table 7-1. Power On Strapping Options ........................................................................................................... 27

Table 8-1. Global Configuration Registers........................................................................................................ 30

Table 8-2. FDC Configuration Registers........................................................................................................... 31

Table 8-3. Serial Port 1 Configuration Registers .............................................................................................. 31

Table 8-4. Serial Port 2 Configuration Registers .............................................................................................. 31

Table 8-5. Parallel Port Configuration Registers............................................................................................... 32

Table 8-6. Environment Controller Configuration Registers ............................................................................. 32

Table 8-7. KBC(Keyboard) Configuration Registers......................................................................................... 32

Table 8-8. KBC(Mouse) Configuration Registers ............................................................................................. 33

Table 8-9. GPIO Configuration Registers ......................................................................................................... 33

Table 8-10. GPIO Configuration Registers ....................................................................................................... 34

Table 8-11. Consumer IR Configuration Registers........................................................................................... 35

Table 8-12. Base Address of Logical Devices .................................................................................................. 35

Table 9-1. Memory Stick Register List .............................................................................................................. 75

Table 9-2. Address Map on the LPC Bus ......................................................................................................... 79

Table 9-3. Environment Controller Registers.................................................................................................... 80

Table 9-4. Digital Output Register (DOR) ....................................................................................................... 103

Note1

............................................................................ 11

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Contents

Table 9-5. Tape Drive Register (TDR) ............................................................................................................ 103

Table 9-6. Main Status Register (MSR) .......................................................................................................... 104

Table 9-7. Data Rate Select Register (DSR) .................................................................................................. 104

Table 9-8. Data Register (FIFO) ..................................................................................................................... 105

Table 9-9. Digital Input Register (DIR)............................................................................................................ 106

Table 9-10. Diskette Control Register (DCR).................................................................................................. 106

Table 9-11. Status Register 0 (ST0) ...............................................................................................................107

Table 9-12. Status Register 1 (ST1) ...............................................................................................................107

Table 9-13. Status Register 2 (ST2) ...............................................................................................................108

Table 9-14. Status Register 3 (ST3) ...............................................................................................................108

Table 9-15. Command Set Symbol Descriptions ............................................................................................ 109

Table 9-16. Command Set Summary.............................................................................................................. 111

Table 9-17. Effects of MT and N Bits .............................................................................................................. 119

Table 9-18. SCAN Command Result .............................................................................................................. 121

Table 9-19. VERIFY Command Result ........................................................................................................... 122

Table 9-20. Interrupt Identification .................................................................................................................. 125

Table 9-21. HUT Values.................................................................................................................................. 125

Table 9-22. SRT Values.................................................................................................................................. 125

Table 9-23. HLT Values .................................................................................................................................. 126

Table 9-24. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands ....................... 126

Table 9-25. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands .. 126

Table 9-26. Serial Channel Registers ............................................................................................................. 128

Table 9-27. Interrupt Enable Register Description.......................................................................................... 129

Table 9-28. Interrupt Identification Register.................................................................................................... 130

Table 9-29. FIFO Control Register Description............................................................................................... 131

Table 9-30. Receiver FIFO Trigger Level Encoding ....................................................................................... 131

Table 9-31. Baud Rates Using (24 MHz ÷ 13) Clock...................................................................................... 132

Table 9-32. Line Control Register Description ................................................................................................ 133

Table 9-33. Stop Bits Number Encoding......................................................................................................... 133

Table 9-34. Modem Control Register Description........................................................................................... 134

Table 9-35. Line Status Register Description ................................................................................................. 134

Table 9-36. Modem Status Register Description ............................................................................................ 135

Table 9-37. Reset Control of Registers and Pinout Signals ........................................................................... 136

Table 9-38. Parallel Port Connector in Different Modes ................................................................................. 138

Table 9-39. Address Map and Bit Map for SPP and EPP Modes................................................................... 138

Table 9-40. Bit Map of the ECP Registers ...................................................................................................... 141

Table 9-41. ECP Register Definitions .............................................................................................................141

Table 9-42. ECP Mode Descriptions............................................................................................................... 142

Table 9-43. ECP Pin Descriptions................................................................................................................... 142

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Table 9-44. Extended Control Register (ECR) Mode and Description ........................................................... 144

Table 9-45. Data Register READ/WRITE Controls......................................................................................... 148

Table 9-46. Status Register ............................................................................................................................ 148

Table 9-47. List of CIR Registers .................................................................................................................... 151

Table 9-48. Modulation Carrier Frequency ..................................................................................................... 156

Table 9-49. Receiver Demodulation Low Frequency (HCFS = 0) .................................................................. 157

Table 9-50. Receiver Demodulation High Frequency (HCFS = 1) ................................................................. 158

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1. Features

 Low Pin Count Interface

− Comply with Intel Low Pin Count Interface

Specification Rev. 1.0

− Supports LDRQ#, SERIRQ protocols

− Supports PCI PME# Interfaces

 ACPI & LANDesk Compliant

− ACPI V. 1.0 compliant

− Register sets compatible with “Plug and Play

ISA Specification V. 1.0a”

− LANDesk 3.X compliant

− Supports 12 logical devices

 Enhanced Hardware Monitor

− Built-in 8-bit Analog to Digital Converter

− 3 thermal inputs from remote thermal resistor

or thermal diode or diode-connected transistor

− 8 voltage monitor inputs (VBAT is measured

internally.)

− 1 chassis open detection input with low power

Flip-Flop backed by the battery

− Watch Dog comparison of all monitored values

− Provides VID0 – VID7 support for the CPU

− SST/PECI/AMDSI I/F support.

 Fan Speed Controller

− Provides fan on-off and PWM control

− Supports 3 programmable Pulse Width

Modulation (PWM) outputs

− 128 steps of PWM modes

− Monitors 5 fan tachometer inputs

 SmartGuardian Controller

− Provides programmable fan speed automatic

control

− Supports mix-and-match for temperature inputs

and fan speed control outputs

− Overrides fan speed controller during

catastrophic situations

− Provides over temperature beep tone warning

 Two 16C550 UARTs

− Supports two standard Serial Ports

− Supports IrDA 1.0/ASKIR protocols

 Consumer Remote Control (TV remote) IR

with power-up feature

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 IEEE 1284 Parallel Port

− Standard mode -- Bi-directional SPP compliant

− Enhanced mode -- EPP V. 1.7 and V. 1.9

compliant

− High speed mode -- ECP, IEEE 1284 compliant

− Back-drive current reduction

− Printer power-on damage reduction

− Supports POST (Power-On Self Test) Data

Port

 Floppy Disk Controller

− Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M

floppy disk drives

− Enhanced digital data separator

− 3-Mode drives supported

− Supports automatic write protection via

software

 Keyboard Controller

− 8042 compatible for PS/2 keyboard and mouse

− Hardware KBC

− GateA20 and Keyboard reset output

− Supports any key, or 2-5 sequential keys, or 1-

3 simultaneous keys keyboard power-on events

− Supports mouse double-click and/or mouse

move power on events

− Supports Keyboard and Mouse I/F hardware

auto-swap

 48 General Purpose I/O Pins

− Input mode supports either switch de-bounce

or programmable external IRQ input routing

− Output mode supports 2 sets of programmable

LED blinking periods

 Serial Flash I/F for BIOS

− Supports SPI I/F

−

 Watch Dog Timer

− Time resolution 1 minute or 1 second,

maximum 65535 minutes or 65535 seconds

− Output to KRST# and PWROK when expired

 ITE innovative automatic power-failure

resume and power button de-bounce

Features

ITPM-PN-200625 Specifications subject to Change without Notice By Joseph Huang, 6/6/2006

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 Dedicated Infrared pins  VCCH and Vbat Supported  Built-in 32.768 KHz Oscillator

 Single 24/48 MHz Clock Input  +5V Power Supply  128-pin QFP

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General Description

2. General Description

The IT8718F is a Low Pin Count Interface-based highly integrated Super I/O. The IT8718F provides the most commonly used legacy Super I/O functionality plus the latest Environment Control initiatives, such as H/W Monitor, Fan Speed Controller. The device’s LPC interface complies with Intel “LPC Interface Specification Rev. 1.0”. The IT8718F is ACPI & LANDesk compliant.

The IT8718F features the enhanced hardware monitor providing 3 thermal inputs from remote thermal resistors, or thermal diode or diode-connected transistor (2N3904). The device also provides the ITE innovative intelligent automatic Fan ON/OFF & speed control functions (SmartGuardian) to protect the system, reducing the system noise and power consumption.

The IT8718F contains 1 Fan Speed Controller. The fan speed controller is responsible to control 3 fan speeds through three 128 steps of Pulse Width Modulation (PWM) output pins and to monitor five FANs’ Tachometer inputs. It also features two 16C550 UARTs, one IEEE 1284 Parallel Port, one Floppy Disk Controller and one Keyboard Controller.

The IT8718F has integrated 7 logical devices. One high-performance 2.88MB floppy disk controller, with digital data separator, supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high-performance parallel port features the bi-directional Standard Parallel Port (SPP), the Enhanced Parallel Port (EPP V. 1.7 and EPP V. 1.9 are supported), and the IEEE 1284 compliant Extended Capabilities Port (ECP). Two 16C550 standard compatible enhanced UARTs perform asynchronous communication, and also support either IR interface. The device also features one fan speed controller responsible for controlling / monitoring 5 fans and 6 GPIO ports (48 GPIO pins). The IT8718F also has an integrated Keyboard Controller.

These 7 logical devices can be individually enabled or disabled via software configuration registers. The IT8718F utilizes power-saving circuitry to reduce power consumption, and once a logical device is disabled the inputs are gated inhibit, the outputs are tri-state, and the input clock is disabled. The device requires a single 24/48 MHz clock input and operates with +5V power supply. The IT8718F is available in 128-pin QFP (Quad Flat Package).

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3. Block Diagram

SERIRQ

LDRQ#

C P

Block Diagram

24 / 48 MHz

OSC.

Serial Port I/F

IR I/F

Serial Port I/F

Parallel Port

I/F

Floppy

Drive I/F

Clock Gen.

16C550 UART 1

IrDA 1.0 /

ASKIR

16C550 UART 2

IEEE1284

Parallel

Port

Floppy

Disk

Controller

LPC Interface

& Plug-and-Play

Registers

s u B

e c a

f r

t n

I l a

t n e

Keyboard Controller

Consumer

I/R

General

Purpose

I/O

Serial

Flash I/F

Fan

Speed

Controller

PME#

Mouse I/F

Keyboard I/F

CIR I/F

I/O Ports

Serial

Flash I/F

Fan I/F

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8-bit

ADC

Monitored

Voltages

Environment Controller

Fan

Tachometers

Thermal Resistor

Thermal

Sensor

Thermal

Diode

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4. Pin Configuration

Pin Configuration

DTR2#/JP4

RTS2/JP5

DSR2#/GP64

VCC

SOUT2/JP6

SIN2/GP63 FAN_TAC1

FAN_CTL1 FAN_TAC2/GP52 FAN_CTL2/GP51 FAN_TAC3/GP37 FAN_CTL3/GP36

VID5/GP35

VID4/GP34

GNDD VID3/GP33 VID2/GP32 VID1/GP31 VID0/GP30

VIDO5/GP27 VIDO4/GP26

VDO3/FAN_TAC4/GP25

VIDO2/FAN_TAC5/GP24

GP23/SI/VGP2

GP22/SCK/VGP1

VIDO1/GP21/VGP0

VIDO0/GP20 VIDO6/GP17

RESETCON#/CIRTX/CE_N

GP16/SO2

PCIRST1#/GP14

PWROK1/GP13 PCIRST2#/GP12 PCIRST3#/GP11

VCC

VIDVCC

LRESET#

LDRQ#/JP8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

BUSY

102

101

SLCT

100

AVCC

VIN0

VIN1

VIN2

VIN3/ATXPG

VIN4

VIN5/VID7

VIN6/VID6

VIN7/PCIRSTIN#

VREF

TMPIN1

TMPIN2

TMPIN3/SO1

GNDA(D-)

RSMRST#/CIRRX/GP55

PCIRST4#/GP10

MCLK/GP56

MDAT/GP57

82 81

KCLK/GP60

KDAT/GP61

3VSBSW#/GP40

PWROK2/GP41

SUSC#/GP53

PSON#/GP42

PANSWH#/GP43

GNDD

PME#/GP54 PWRON#/GP44

SUSB#

IRRX/GP46

VBAT

COPEN#

VCCH

IRTX/GP47/CE2_N/JP9

DSKCHG#

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Table 4-1. Pins Listed in Numeric Order

Pin Signal Pin Signal Pin Signal Pin Signal

1 DTR2#/JP4 33 PCIRST2#/GP12 65 DSKCHG# 97 VIN1

2 RTS2#/JP5 34 PCIRST3#/GP11 66

IRTX/GP47/ CE2_N/JP9

98 VIN0

3 DSR2#/GP64 35 VCC 67 VCCH 99 AVCC 4 VCC 36 VIDVCC 68 COPEN# 100 SLCT 5 SOUT2/JP6 37 LRESET# 69 VBAT 101 PE 6 SIN2/GP63 38 LDRQ#/JP8 70 GP46/IRRX 102 BUSY 7 FAN_TAC1 39 SERIRQ 71 SUSB# 103 ACK# 8 FAN_CTL1 40 LFRAME# 72 PWRON#/GP44 104 SLIN#

9 FAN_TAC2/GP52 41 LAD0 73 PME#/GP54 105 INIT# 10 FAN_CTL2/GP51 42 LAD1 74 GNDD 106 ERR# 11 FAN_TAC3/GP37 43 LAD2 75 PANSWH#/GP43 107 AFD# 12 FAN_CTL3/GP36 44 LAD3 76 PSON#/GP42 108 STB# 13 VID5/GP35 45 KRST#/GP62 77 SUSC#/GP53 109 PD0 14 VID4/GP34 46 GA20/JP7 78 PWROK2/GP41 110 PD1 15 GNDD 47 PCICLK 79 3VSBSW#/GP40 111 PD2 16 VID3/GP33 48 VIDO7/GP50 80 KDAT/GP61 112 PD3 17 VID2/GP32 49 CLKIN 81 KCLK/GP60 113 PD4 18 VID1/GP31 50 GNDD 82 MDAT/GP57 114 PD5 19 VID0/GP30 51 DENSEL# 83 MCLK/GP56 115 PD6 20 VIDO5/GP27 52 MTRA# 84 PCIRST4#/GP10 116 PD7

21 VIDO4/GP26 53

VIDO3/FAN_TAC

4/GP25 VIDO2FAN_TAC5

/GP24 GP23/SI/

VGP2 GP22/SCK/

VGP1 VIDO1/GP21/

VGP0

54 DRVA# 86 GNDA(D-) 118 DCD1#

56 WDATA# 88 TMPIN2 120 CTS1#

57 DIR# 89 TMPIN1 121 DTR1#/JP1

58 STEP# 90 VREF 122 RTS1#/JP2

SST/AMDSI_D/ MTRB#

PECI/AMDSI_C/ DRVB#

RSMRST#/CIRRX

/GP55

117 GNDD

87 TMPIN3/SO1 119 RI1#

27 VIDO0/GP20 59 HDSEL# 91 VIN7/PCIRSTIN# 123 DSR1# 28 VIDO6/GP17 60 WGATE# 92 VIN6/VID6 124 SOUT1/JP3 29 GP16/SO2 61 RDATA# 93 VIN5/VID7 125 SIN1

RESETCON#/CIR

TX/CE_N PCIRST1#/GP14/

I_STPCLK

62 TRK0# 94 VIN4 126 DCD2#/GP67

63 INDEX# 95 VIN3/ATXPG 127 RI2#/GP66

32 PWROK1/GP13 64 WPT# 96 VIN2 128 CTS2#/GP65

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Pin Descriptions

5. IT8718F Pin Descriptions

Table 5-1. Pin Description of Supplies Signals

Pin(s) No. Symbol Attribute Power Description

4, 35 VCC

99 AVCC 67 VCCH 69 VBAT 36 VIDVCC

15, 50,

GNDD

74, 117

86 GNDA(D-)

Table 5-2. Pin Description of LPC Bus Interface Signals

Pin(s) No. Symbol Attribute Power Description

37 LRESET#

38 LDRQ#/JP8

39 SERIRQ 40 LFRAME#

41 – 44 LAD[0:3]

47 PCICLK

73 PME#/GP54

PWR PWR PWR PWR PWR GND -

GND -

DI VCC

DO16 VCC

DIO16 VCC

DI VCC

DIO16 VCC

DI VCC

DOD8/

VCCH

DIOD8

+5V Power Supply. +5V Analog Power Supply. +5V VCC Help Supply. +3.3V Battery Supply. VID power supply. (1.2 or 3.3V) Digital Ground.

Analog Ground. (D-)

LPC RESET #.

EC block will not be reset by LRESET#, which is controlled by VCC PWRGD.

LPC DMA Request #.

An encoded signal for DMA channel select.

During LRESET#, this pin is input for JP8 power-on strapping option

Serial IRQ. LPC Frame #.

This signal indicates the start of LPC cycle.

LPC Address/Data 0-3.

4-bit LPC address/bi-directional data lines. LAD0 is the LSB and LAD3 is the MSB.

PCI Clock.

33 MHz PCI clock input for LPC I/F and SERIRQ.

Power Management Event # / General Purpose I/O 54.

• The first function of this pin is the power management event #. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up from the D3 (cold) state.

• The second function of this pin is the General Purpose I/O Port 5 Bit 4.

• The function configuration of this pin is determined by programming the software configuration registers.

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Table 5-3. Pin Description of GPI/O Signals

Pin(s) No. Symbol Attribute Power Description

48 VIDO7/

GP50

28 VIDO6/

GP17

29 GP16/

SO2

27 VIDO0/

GP20

DO8/

DIOD8

DO8/

DIOD8

DIOD8/

DO8/

DIOD8

VCC

VIDO7 / General Purpose I/O 50.

• The first function of this pin is VID output pin 7.

• The second function of this pin is the General Purpose I/O

Port 5 Bit 0.

• The function configuration of this pin is decided by the

software configuration registers.

VIDO7 / General Purpose I/O 17.

• The first function of this pin is VID output pin 6.

• The second function of this pin is the General Purpose I/O

Port 1 Bit 7.

• The function configuration of this pin is decided by the

software configuration registers.

General Purpose I/O 16/ Serial Output Data 2.

• The first function of this pin is the General Purpose I/O Port 1 Bit 6.

• The second function is Serial Output Data 2 from Serial Flash.

• The function configuration of this pin is determined by

programming the software configuration registers.

VID output 0 /General Purpose I/O 20.

• The first function of this pin is VID output pin 0.

• The second function of this pin is the General Purpose I/O

Port 2 Bit 0.

• The function configuration of this pin is determined by

programming the software configuration registers.

26 VIDO1/

GP21/

25 GP22/

SCK/

VGP1

24 GP23/

23 VIDO2/

FAN_TAC5/

GP24

DO8/

DIOD8

DIOD8/

DOD8/ DIOD8

DIOD8/

DOD8

DO8/

DI/

DIOD8

VCC

VID output 1 /General Purpose I/O 21.

• The F first function of this pin is VID output pin 1.

• The second function of this pin is the General Purpose I/O

Port 2 Bit 1.

• The function configuration of this pin is determined by

programming the software configuration registers.

General Purpose I/O 22/ Serial Flash Clock.

• The first function of this pin is the General Purpose I/O Port 2 Bit 2.

• The second function of this pin is Serial Clock for Serial Flash.

• The function configuration of this pin is determined by

programming the software configuration registers.

General Purpose I/O 23/ Serial Flash In Data.

• The first function of this pin is the General Purpose I/O Port 2 Bit 3.

• The second function is Serial In Data for Serial Flash.

• The function configuration of this pin is determined by

programming the software configuration registers.

VID output 2 / FAN Tachometer input 5/ General Purpose I/O 24.

• The first function of this pin is VID output pin 2.

• The second function of this pin is Fan Tachometer Input 5.

0 to +5V amplitude fan tachometer input.

• The third function of this pin is the General Purpose I/O Port 2 Bit 4.

• The function configuration of this pin is determined by

programming the software configuration registers.

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Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

22 VIDO3/

FAN_TAC4/

GP25

DO8/

DI/

DIOD8

21 VIDO4/

GP26

20 VIDO5/

GP27

DO8/

DIOD8

DO8/

DOD8

Table 5-4. Pin Description of Hardware Monitor Signals

Pin(s) No. Symbol Attribute Power Description

98 – 96 VIN[0:2]

95 ATXPG/

VIN3

94 VIN4

93 – 92 VID[7:6]/

VIN[5:6]

91 PCIRSTIN#/

VIN7

90 VREF

89 – 88 TMPIN[1:2]

AI AVCC

DI/

AI AVCC

DI/

AO AVCC

AI AVCC

VCC

AVCC

VID output 3 /FAN Tachometer input 5/General Purpose I/O 25.

• The first function of this pin is VID output pin 3.

• The second function of this pin is Fan Tachometer Input 4.

0 to +5V amplitude fan tachometer input.

• The third function of this pin is the General Purpose I/O Port 2 Bit 5.

• The function configuration of this pin is determined by

programming the software configuration registers.

VID output 4 /General Purpose I/O 26.

• The first function of this pin is VID output pin 4.

• The second function of this pin is the General Purpose I/O

Port 2 Bit 6.

VID output 5 /General Purpose I/O 27.

• The first function of this pin is VID output pin 5.

• The second function of this pin is the General Purpose I/O

Port 2 Bit 7.

Note1

Voltage Analog Inputs [0:2].

0 to 4.096V FSR Analog Inputs.

Voltage Analog Input 3 / ATX Power Good.

• The first function of this pin is ATX Power Good.

PWROK1/2 will be (VCC power-level-detect AND RESETCON# AND SUSB# AND ATXPG) if bit0 of Index 2Ch is 1, or (VCC power-level-detect AND RESETCON# AND SUSB#) if the bit is 0.

• The second function of this pin is 0 to 4.096V FSR Analog Inputs.

• The function configuration of this pin is determined by programming the software configuration registers.

Voltage Analog Inputs [4].

0 to 4.096V FSR Analog Inputs.

Voltage Analog Inputs [5:6] / Voltage ID [7:6]

• The first function of this pin is Voltage ID Input [7:6]. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0).

• The second function of this pin is 0 to 4.096V FSR Analog Inputs.

• The function configuration of this pin is determined by programming the software configuration registers.

Voltage Analog Input 7 / PCI Reset Input #.

• The first function of this pin is PCI Reset Input #.

• The second function of this pin is 0 to 4.096V FSR Analog

Inputs.

• The function configuration of this pin is determined by programming the software configuration registers.

Reference Voltage Output.

Regulated and referred voltage for 3 external temperature sensors and negative voltage monitor.

External Thermal Inputs [1:2].

Connected to thermistors [1:2] or thermal temperature sensors.

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Pin(s) No. Symbol Attribute Power Description

87 TMPIN3/

SO1

AI/

AVCC

External Thermal Inputs 3/ Serial Flash Output Data 1.

• The first function of this pin is connected to thermistor 3 or thermal temperature sensor.

• The second function of this pin is Serial Output Data 1 from Serial Flash.

• The function configuration of this pin is determined by programming the software configuration registers.

7 FAN_TAC1

DI VCC

Fan Tachometer Input 1.

0 to +5V amplitude fan tachometer input.

9 FAN_TAC2/

GP52

DI/

DIOD8

VCC

Fan Tachometer Input 2 / General Purpose I/O 52.

• The first function of this pin is Fan Tachometer Input 2. 0 to +5V amplitude fan tachometer input.

• The second function of this pin is the General Purpose I/O Port 5 Bit 2.

• The function configuration of this pin is determined by programming the software configuration registers.

11 FAN_TAC3/

GP37

DI/

DIOD8

VCC

Fan Tachometer Input 3 / General Purpose I/O 37.

• The first function of this pin is Fan Tachometer Input 3. 0 to +5V amplitude fan tachometer input.

• The second function of this pin is the General Purpose I/O

Port 5 Bit 2.

• The function configuration of this pin is determined by

programming the software configuration registers.

19 VID0/

GP30

DIO8/

DIOD8

VCC

Voltage ID 0 / General Purpose I/O 30.

• The first function of this pin is Voltage ID Input 0. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2).

(2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0)

• The second function of this pin is the General Purpose I/O

30.

• The function configuration of this pin is decided by the

software configuration registers.

18 VID1/

GP31

DIO8/

DIOD8

VCC

Voltage ID 1 / General Purpose I/O 31.

• The first function of this pin is Voltage ID Input 1. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2).

(2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0)

• The second function of this pin is the General Purpose I/O

31.

• The function configuration of this pin is decided by the

software configuration registers.

17 VID2/

GP32

DIO8/

DIOD8

VCC

Voltage ID 2 / General Purpose I/O 32.

• The first function of this pin is Voltage ID Input 2. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2).

(2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0)

• The second function of this pin is the General Purpose I/O

32.

• The function configuration of this pin is decided by the

software configuration registers.

16 VID3/

GP33

DIO8/

DIOD8

VCC

Voltage ID 3 / General Purpose I/O 33.

• The first function of this pin is Voltage ID Input 3. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2).

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Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

(2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0)

• The second function of this pin is the General Purpose I/O

33.

• The function configuration of this pin is decided by the

software configuration registers.

14 VID4/

GP34

DIO8/

DIOD8

VCC

Voltage ID 4 / General Purpose I/O 34.

• The first function of this pin is Voltage ID Input 4. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0)

• The second function of this pin is the General Purpose I/O

34.

• The function configuration of this pin is decided by the

software configuration registers.

13 VID5/

GP35

DIO8/

DIOD8

VCC

Voltage ID 5 / General Purpose I/O 35.

• The first function of this pin is Voltage ID Input 5. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2).

(2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0)

• The second function of this pin is the General Purpose I/O

35.

• The function configuration of this pin is decided by the

software configuration registers.

68 COPEN#

DIOD8 VCCH

or VBAT

Case Open Detection #.

• The Case Open Detection is connected to a specially designed low power CMOS flip-flop backed by the battery

for case open state preservation during power loss.

Table 5-5. Pin Description of Fan Controller Signals

Pin(s) No. Symbol Attribute Power Description

8 FAN_CTL1

DOD8 VCC

Fan Control Output 1.

(PWM output signal to Fan’s FET.)

10 FAN_CTL2/

GP51

DOD8/ DIOD8

VCC

Fan Control Output 2 / General Purpose I/O 51.

• The first function of this pin is Fan Control Output 2. (PWM output signal to Fan’s FET.)

• The second function of this pin is the General Purpose I/O Port 5 Bit 1.

• The function configuration of this pin is determined by programming the software configuration registers.

12 FAN_CTL3/

GP36

DOD8/ DIOD8

VCC

Fan Control Output 3 / General Purpose I/O 36.

• The first function of this pin is Fan Control Output 3. (PWM output signal to Fan’s FET.)

• The second function of this pin is the General Purpose I/O Port 3 Bit 6.

• The function configuration of this pin is determined by programming the software configuration registers.

Table 5-6. Pin Description of Infrared Port Signals

Pin(s) No. Symbol Attribute Power Description

30 RESETCON#/

CIRTX/

CE_N

DI/

DOD8/

DOD8

VCC

Reset Connect # / Consumer Infrared Transmit Output / General Purpose I/O 15 / Serial Flash Chip Enable.

• The first function of this pin is Reset Connect #. It connects to reset button, and also other reset source on the motherboard.

• The second function of this pin is Consumer Infrared

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Pin(s) No. Symbol Attribute Power Description

Transmit Output.

• The third function of this pin is the Serial Flash chip enable.

• The function configuration of this pin is determined by

programming the software configuration registers.

85 RSMRST#/

CIRRX/

GP55

DOD8/

DI/

DIOD8

VCCH

Resume Reset # / Consumer Infrared Receive Input / General Purpose I/O 55.

• The first function of this pin is Resume Reset #. It is power good signal of VCCH. The high threshold is 4V ± 0.2V, and the low threshold is 3.5V ± 0.2V

• The second function of this pin is Consumer Infrared Receive Input.

• The Third function of this pin is the General Purpose I/O Port 5 Bit 5.

• The function configuration of this pin is determined by programming the software configuration registers.

70 GP46/

IRRX

DI/

DIOD8

VCCH

Infrared Receive Input / General Purpose I/O 46.

• The first function of this pin is the General Purpose I/O Port 4 Bit 6.

• The second function of this pin is Infrared Receive Input.

• The function configuration of this pin is determined by

programming the software configuration registers.

66 IRTX/

GP47

DO8/

DIOD8

VCC

Infrared Transmit Output / General Purpose I/O 47.

• The first function of this pin is Infrared Transmit output.

• The second function of this pin is the General Purpose I/O

Port 4 Bit 7.

• The fourth function of this pin is GPIO output 1 by sensing VIN6.

• The function configuration of this pin is determined by programming the software configuration registers.

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Pin Descriptions

Table 5-7. Pin Description of Serial Port 1 Signals

Pin(s) No. Symbol Attribute Power Description

125 SIN1

DI VCC

Serial Data Input 1.

This input receives serial data from the communications link.

124 SOUT1/

JP3

DO8/

VCC

Serial Data Output 1.

This output sends serial data to the communications link. This signal is set to a marking state (logic 1) after a Master Reset operation or when the device is in one of the Infrared communications modes.

During LRESET#, this pin is input for JP3 power-on strapping option

123 DSR1#

DI VCC

Data Set Ready 1 #.

When the signal is low, it indicates that the MODEM or data set is ready to establish a communications link. The DSR# signal is a MODEM status input whose condition can be tested by reading the MSR register.

122 RTS1#/

JP2

DO8/

VCC

Request to Send 1 #.

When this signal is low, this output indicates to the MODEM or data set that the device is ready to send data. RTS# is activated by setting the appropriate bit in the MCR register to

1. After a Master Reset operation or during Loop mode, RTS#

is set to its inactive state.

During LRESET#, this pin is input for JP2 power-on strapping option

121 DTR1#/

JP1

DO8/

VCC

Data Terminal Ready 1 #.

DTR# is used to indicate to the MODEM or data set that the device is ready to exchange data. DTR# is activated by setting the appropriate bit in the MCR register to 1. After a Master Reset operation or during Loop mode, DTR# is set to its inactive state.

During LRESET#, this pin is input for JP1 power-on strapping option

120 CTS1#

DI VCC

Clear to Send 1 #.

When the signal is low, it indicates that the MODEM or data set is ready to accept data. The CTS# signal is a MODEM status input whose condition can be tested by reading the MSR register.

119 RI1#

DI VCC

Ring Indicator 1 #.

When the signal is low, it indicates that a telephone ring signal has been received by the MODEM. The RI# signal is a MODEM status input whose condition can be tested by reading the MSR register.

118 DCD1#

DI VCC

Data Carrier Detect 1 #.

When the signal is low, it indicates that the MODEM or data set has detected a carrier. The DCD# signal is a MODEM status input whose condition can be tested by reading the MSR register.

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Table 5-8. Pin Description of Serial Port 2 Signals

Pin(s) No. Symbol Attribute Power Description

6 SIN2/

GP63

5 SOUT2/

JP6

3 DSR2#/

GP64

2 RTS2#/

JP5

1 DTR2#/

JP4

128 CTS2#/

GP65

127 RI2#/

GP66

DI/

DIOD8

DO8/DI VCC

DI/

DIOD8

DO8/DI VCC

DI/

DIOD8

DI/

DIOD8

VCC

Serial Data In 2/ General Purpose I/O 63.

• The first function of this pin is Serial Data In 2 of Serial Port

2. This input receives serial data from the communications link.

• The second function of this pin is the General Purpose I/O Port 6 Bit 3. This set only supports Simple I/O function.

• The function configuration of this pin is determined by programming the software configuration registers.

Serial Data Out 2.

The instant when internal power-ok is ready, this pin is input for JP6 power-on strapping option

Data Set Ready 2 #/ General Purpose I/O 64.

• The first function of this pin is Data Set Ready 2 of Serial Port 2. When low, indicates that the MODEM or data set is ready to establish a communications link. The DSR# signal is a MODEM status input whose condition can be tested by reading the MSR register.

• The second function of this pin is the General Purpose I/O Port 6 Bit 4. This set only supports Simple I/O function.

The function configuration of this pin is determined by programming the software configuration registers.

Request to Send 2 #.

When low, this output indicates to the MODEM or data set that the device is ready to send data. RTS# is activated by setting the appropriate bit in the MCR register to 1. After a Master Reset operation or during Loop mode, RTS# is set to its inactive state.

During LRESET#, this pin is input for JP5 power-on strapping option

Data Terminal Ready 2 #.

During LRESET#, this pin is input for JP4 power-on strapping option

Clear to Send 2 #/ General Purpose I/O 65.

• The first function of this pin is Clear to Send 2 of Serial Port

2. When low, indicates that the MODEM or data set is ready to accept data. The CTS# signal is a MODEM status input whose condition can be tested by reading the MSR register.

• The second function of this pin is the General Purpose I/O Port 6 Bit 5. This set only supports Simple I/O function.

• The function configuration of this pin is determined by programming the software configuration registers.

Ring Indicator 2 #/ General Purpose I/O 66.

• The first function of this pin is Ring Indicator 2 of Serial Port

2. When low, indicates that a telephone ring signal has been received by the MODEM. The RI# signal is a MODEM status input whose condition can be tested by reading the MSR register.

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Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

• The second function of this pin is the General Purpose I/O Port 6 Bit 6. This set only supports Simple I/O function.

• The function configuration of this pin is determined by programming the software configuration registers.

126 DCD2#/

GP67

DI/

DIOD8

VCC

Data Carrier Detect 2 #/ General Purpose I/O 67.

• The first function of this pin is Data Carrier Detect 2 of Serial Port 2. When low, indicates that the MODEM or data set has detected a carrier. The DCD# signal is a MODEM status input whose condition can be tested by reading the MSR register.

• The second function of this pin is the General Purpose I/O Port 6 Bit 7. This set only supports Simple I/O function.

• The function configuration of this pin is determined by programming the software configuration registers.

Table 5-9. Pin Description of Parallel Port Signals

Pin(s) No. Symbol Attribute Power Description

100 SLCT

DI VCC

Printer Select.

This signal goes high when the line printer has been selected.

101 PE

DI VCC

Printer Paper End.

This signal is set high by the printer when it runs out of paper.

102 BUSY

DI VCC

Printer Busy.

This signal goes high when the line printer has a local operation in progress and cannot accept data.

103 ACK#

DI VCC

Printer Acknowledge #.

This signal goes low to indicate that the printer has already received a character and is ready to accept another one.

104 SLIN#

DIO24 VCC

Printer Select Input #.

When the signal is low, the printer is selected. This signal is derived from the complement of bit 3 of the printer control register.

105 INIT#

DIO24 VCC

Printer Initialize #.

When the signal is low, the printer is selected. This signal is derived from the complement of bit 3 of the printer control register.

106 ERR#

DI VCC

Printer Error #.

When the signal is low, it indicates that the printer has encountered an error. The error message can be read from bit 3 of the printer status register.

107 AFD#

DIO24 VCC

Printer Auto Line Feed #.

When the signal is low, it is derived from the complement of bit 1 of the printer control register and is used to advance one line after each line is printed.

108 STB#

DI VCC

Printer Strobe #.

When the signal is low, it is the complement of bit 0 of the printer control register and is used to strobe the printing data into the printer.

109 – 116 PD[0:7]

DIO24 VCC

Parallel Port Data [0:7].

This bus provides a byte-wide input or output to the system. The eight lines are held in a high impedance state when the port is deselected.

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Table 5-10. Pin Description of Floppy Disk Controller Signals

Pin(s) No. Symbol Attribute Power Description

51 DENSEL#

52 MTRA#

53 SST/

AMDSI_D/

MTRB#

54 DRVA#

55 PECI/

AMDSI_C/

DRVB#

56 WDATA#

57 DIR#

58 STEP#

59 HDSEL#

60 WGATE#

61 RDATA#

62 TRK0#

63 INDEX#

64 WPT#

65 DSKCHG#

DO24L VCC

SST

VCC

DIOD24/

DO24L

DO24L VCC

PECI

VCC

DIOD24/

DO24L

DO24L VCC

DI VCC

FDD Density Select #.

DENSEL# is high for high data rates (500 Kbps, 1 Mbps). DENSEL# is low for low data rates (250 Kbps, 300 Kbps).

FDD Motor A Enable #.

This signal is active low.

External Thermal Sensor Data / FDD Motor B Enable #.

• The first function of this pin is SST.

• The Second function of this pin is External Thermal Sensor

Clock. (AMDSI_D)

• The third function of this pin is FDD Motor B #. This signal

is active low.

• The function configuration of this pin is determined by programming the software configuration registers. When External Thermal Sensor Host is enabled (bit<6:4> of EC Index 0Ah), this pin is selected as SST or ETS_DAT.

FDD Drive A Enable #.

This signal is active low.

External Thermal Sensor Clock / FDD Drive B Enable #.

• The first function of this pin is PECI.

• The second function of this pin is External Thermal Sensor

Clock. (AMDSI_C)

• The third function of this pin is FDD Drive B #. This signal is

active low.

FDD Write Serial Data to the Drive #.

This signal is active low.

FDD Head Direction #.

Step in when this signal is low and step out when high during a SEEK operation.

FDD Step Pulse #.

This signal is active low.

FDD Head Select #.

This signal is active low.

FDD Write Gage Enable #.

This signal is active low.

FDD Read Disk Data #.

This signal is active low. It is serial data input from FDD.

FDD Track 0 #.

This signal is active low. It indicates that the head of the selected drive is on track 0.

FDD Index #.

This signal is active low. It indicates the beginning of a disk track.

FDD Write Protect #.

This signal is active low. It indicates that the disk of the selected drive is write-protected.

FDD Disk Change #.

This signal is active low. It senses whether the drive door has been opened or a diskette has been changed.

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Pin Descriptions

Table 5-11. Pin Description of GPIO function

Pin(s) No. Symbol Attribute Power Description

31 PCIRST1#/

GP14

32 PWROK1/

GP13

33 PCIRST2#/

GP12

34 PCIRST3#/

GP11

84 PCIRST4#/

GP10

DOD8

DIOD8

DOD8/ DIOD8

DOD8

DIOD8

DOD8

DIOD8

DOD8

DIOD8

Note2

VCC

VCCH

PCI Reset 1 # / General Purpose I/O 14.

• The first function of this pin is PCI Reset 1 #. It is a buffer of LRESET#.

• The second function of this pin is the General Purpose I/O

Port 1 Bit 4.

• The function configuration of this pin is determined by programming the software configuration registers.

Power OK 1 of VCC / General Purpose I/O 13.

• The first function of this pin is Power OK 1 of VCC.

• The second function of this pin is the General Purpose I/O

Port 1 Bit 3.

• The function configuration of this pin is determined by programming the software configuration registers.

PCI Reset 2 # / General Purpose I/O 12.

• The first function of this pin is PCI Reset 2 #. It is a buffer of LRESET#.

• The second function of this pin is the General Purpose I/O

Port 1 Bit 2.

• The function configuration of this pin is determined by programming the software configuration registers.

PCI Reset 3 # / General Purpose I/O 11.

• The first function of this pin is PCI Reset 3 #. It is a buffer of LRESET#. It is a buffer output of LRESET# if bit1 of Index 2Ch is 0. It will be (LRESET# AND PCIRSTIN#) if bit1 of Index 2Ch is 1.

• The second function of this pin is the General Purpose I/O

Port 1 Bit 1.

• The function configuration of this pin is determined by programming the software configuration registers.

PCI Reset 4 # / General Purpose I/O 10.

• The first function of this pin is PCI Reset 4 #. It is a buffer of LRESET#.

• The second function of this pin is the General Purpose I/O

Port 1 Bit 0.

• The function configuration of this pin is determined by programming the software configuration registers.

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Table 5-12. Pin Description of Keyboard Controller Signals

Pin(s) No. Symbol Attribute Power Description

80 KDAT/

GP61

DIOD24/

DIOD24

VCCH

Keyboard Data/ General Purpose I/O 61.

• The first function of this pin is Keyboard Data.

• The second function of this pin is the General Purpose I/O

Port 6 Bit 1. This set only supports Simple I/O function.

The function configuration of this pin is determined by programming the software configuration registers. This pin doesn’t support internal pull-up.

81 KCLK/

GP60

DIOD24/

DIOD24

VCCH

Keyboard Clock/ General Purpose I/O 60.

• The first function of this pin is Keyboard Clock.

• The second function of this pin is the General Purpose I/O

Port 6 Bit 0. This set only supports Simple I/O function.

The function configuration of this pin is determined by programming the software configuration registers. This pin doesn’t support internal pull-up.

82 MDAT/

GP57

DIOD24/

DIOD24

VCCH

PS/2 Mouse Data/ General Purpose I/O 57.

• The first function of this pin is PS/2 Mouse Data.

• The second function of this pin is the General Purpose I/O

Port 5 Bit 7.

• The function configuration of this pin is determined by programming the software configuration registers. This pin doesn’t support internal pull-up.

83 MCLK/

GP56

DIOD24/

DIOD24

VCCH

PS/2 Mouse Clock/ General Purpose I/O 56.

• The first function of this pin is PS/2 Mouse Clock.

• The second function of this pin is the General Purpose I/O

Port 5 Bit 6.

• The function configuration of this pin is determined by programming the software configuration registers. This pin doesn’t support internal pull-up.

45 KRST#/

GP62

DO16/

DIOD16

VCC

Keyboard Reset #/ General Purpose I/O 62.

• The first function of this pin is Keyboard Reset #.

• The second function of this pin is the General Purpose I/O

Port 6 Bit 2. This set only supports Simple I/O function.

• The function configuration of this pin is determined by programming the software configuration registers.

46 GA20/

JP7

DO16 VCC

Gate Address 20.

During LRESET#, this pin is input for JP7 power-on strapping option

Table 5-13. Pin Description of Miscellaneous Signals

Pin(s) No. Symbol Attribute Power Description

49 CLKIN 72 PWRON#/

GP44

75 PANSWH#/

GP43

DI VCC DOD8/ DIOD8

DI/

DIOD8

VCCH

24 or 48 MHz Clock Input. Power On Request Output # / General Purpose I/O44.

• The first function of this pin is Power On Request Output #.

• The second function of this pin is the General Purpose I/O

Port 4 Bit 4.

• The function configuration of this pin is determined by programming the software configuration registers.

Main Power Switch Button Input # / General Purpose I/O

43.

• The first function of this pin is Main Power Switch Button Input #.

• The second function of this pin is the General Purpose I/O

Port 4 Bit 3.

• The function configuration of this pin is determined by programming the software configuration registers.

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Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

76 PSON#/

GP42

DOD8/ DIOD8

VCCH

Power Supply On-Off Output # / General Purpose I/O 42.

• The first function of this pin is Power Supply On-Off Control Output #.

• The second function of this pin is the General Purpose I/O

Port 4 Bit 2.

• The function configuration of this pin is determined by programming the software configuration registers.

71 SUSB#

DI VCCH

SUSB # Input .

• The function of this pin is SUSB # Input.

77 SUSC#/

GP53

DI/

DIOD8

VCCH

SUSC# Input / General Purpose I/O 53.

• The first function of this pin is SUSC# Input.

• The second function of this pin is the General Purpose I/O

Port 5 Bit 3.

• The function configuration of this pin is determined by programming the software configuration registers.

78 PWROK2/

GP41

DOD8/ DIOD8

VCCH

Power OK 2 of VCC / General Purpose I/O 41.

• The first function of this pin is Power OK 2 of VCC.

• The second function of this pin is the General Purpose I/O

Port 4 Bit 1.

• The function configuration of this pin is determined by programming the software configuration registers.

79 3VSBSW#/

GP40

DO8/

DIOD8

VCCH

3VSBSW# / General Purpose I/O 40.

• The first function of this pin is 3VSBSW#.

• The second function of this pin is the General Purpose I/O

Port 4 Bit 0.

• The function configuration of this pin is determined by programming the software configuration registers.

Note 1: In addition to providing a highly integrated chip, ITE has also implemented a “SmartGuardian Utility”

for hardware monitor application, providing a total solution for customers. The “SmartGuardian Utility” and the application circuit of hardware monitor function (the function arrangement of VIN0-7, TMPIN1-3, FAN_TAC13 and FAN_CTL1-3) are interdependent. That is to say, the “ SmartGuardian Utility” is programmed according to the application circuit of hardware monitor function. ITE strongly recommends customers to follow the referenced application circuit of IT8718F to reduce the “time-to-market” schedule.

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Pin No. Symbol Recommended function arrangement

98 VIN0 2 Volt for VCORE1 of CPU

97 VIN1 2 Volt for VCORE2 of CPU

96 VIN2 3.3 Volt for system

95 VIN3 5 Volt for system

94 VIN4 +12 Volt for system

93 VIN5 -12 Volt for system

92 VIN6 -5 Volt for system

91 VIN7 5 Volt for VCCH

Note 2: If the power-on strapping input JP4 is low, the output attributes of these pins will be push-pull. IO Cell:

DO8: 8mA Digital Output buffer DOD8: 8mA Digital Open-Drain Output buffer DO16: 16mA Digital Output buffer DO24: 24mA Digital Output buffer DO24L: 24mA shink/8mA drive Digital Output buffer

DIO8: 8mA Digital Input/Output buffer DIOD8: 8mA Digital Open-Drain Input/Output buffer DIO16: 16mA Digital Input/Output buffer DIOD16: 16mA Digital Open-Drain Input/Output buffer DIO24: 24mA Digital Input/Output buffer DIOD24: 24mA Digital Open-Drain Input/Output buffer

DI: Digital Input AI: Analog Input AO: Analog Output

SST: special design for SST interface PECI: special design for PECI interface

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6. List of GPIO Pins

Table 6-1. General Purpose I/O Group 1 (Set 1)

Pin(s) No. Symbol Attribute Description

84 PCIRST4#/

GP10

34 PCIRST3#/

GP11

33 PCIRST2#/

GP12

32 PWROK1/

GP13

31 PCIRST1#/

GP14

30 RESETCON#

/CIRTX/

/CE_N

29 GP16/

SO2

28 VIDO6/

GP17

DOD8/

DI/DIOD8

DOD8/ DIOD8

DI/

DOD8/

DOD8

DI/

DIOD8 DOD8/

DIOD8

Table 6-2. General Purpose I/O Group 2 (Set 2)

Pin(s) No. Symbol Attribute Description

27 VIDO0/

GP20

26 VIDO1/

GP21

25 GP22/

SCK

24 GP23/

23 VIDO2/

FAN_TAC5/

GP24

22 VIDO3/

FAN_TAC4/

GP25

21 VIDO4/

GP26

20 VIDO5/

GP27

DOD8/ DIOD8

DI/

DIOD8

DI/

DIOD8 DOD8/

DI/

DIOD8 DOD8/

DI/

DIOD8 DOD8/

DIOD8/

DOD8/ DIOD8

PCI Reset 4 # / General Purpose I/O 10.

PCI Reset 3 # / General Purpose I/O 11.

PCI Reset 2 # / General Purpose I/O 12.

Power OK 1 of VCC / General Purpose I/O 13.

PCI Reset 1 # / General Purpose I/O 14.

Reset Connect # /Consumer Infrared Transmit Output / Serial Flash Chip Enable#

General Purpose I/O 16/Serial Flash Output Data 2.

VID Output 6 / General Purpose I/O 17. /O_STPCLK / Serial Flash chip enable 2 /Power-On Strapping 9

VID Output 0 / General Purpose I/O 20.

VID Output 1 / General Purpose I/O 21.

General Purpose I/O 22 / Serial Flash Clock.

General Purpose I/O 23 / Serial Flash In Data.

VID Output 2 / FAN_TAC input set 5 /General Purpose I/O 24.

VID Output 3 / FAN_TAC input set 5 /General Purpose I/O 25.

VID Output 4 / General Purpose I/O 26.

VID Output 5/ General Purpose I/O 27.

List of GPIO Pins

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Table 6-3. General Purpose I/O Group 3 (Set 3)

Pin(s) No. Symbol Attribute Description

19 VID0/

GP30

18 VID1/

GP31

17 VID2/

GP32

16 VID3/

GP33

14 VID4/

GP34

13 VID5/

GP35

12 FAN_CTL3/

GP36

11 FAN_TAC3/

GP37

DIO8/

DIOD8

DIO8/

DIOD8

DIO8/

DIOD8

DIO8/

DIOD8

DIO8/

DIOD8

DIO8/

DIOD8 DOD8/

DIOD8

DI/

DIOD8

Voltage ID 0 / General Purpose I/O 30.

Voltage ID 1 / General Purpose I/O 31.

Voltage ID 2 / General Purpose I/O 32.

Voltage ID 3 / General Purpose I/O 33.

Voltage ID 4 / General Purpose I/O 34.

Voltage ID 5 / General Purpose I/O 35.

Fan Control Output 3 / General Purpose I/O 36.

Fan Tachometer Input 3 / General Purpose I/O 37.

Table 6-4. General Purpose I/O Group 4 (Set 4)

Pin(s) No. Symbol Attribute Description

79 3VSBSW#/

GP40

78 PWROK2/

GP41

76 PSON#/

GP42

75 PANSWH#/

GP43

72 PWRON#/

GP44 71 SUSB# 70 GP46/

IRRX

66 IRTX/

GP47/

CE_2N/

JP9

DOD8/ DIOD8

DI/

DIOD8 DOD8/

DIOD8

DI SUSB # Input.

DI/

DIOD8

DO8/ DIOD8/ DIOD8/

3VSBSW# / General Purpose I/O 40.

Power OK 2 of VCC / General Purpose I/O 41.

Power Supply On-Off Control Output # / General Purpose I/O 42.

Main Power Switch Button Input # / General Purpose I/O 43.

Power On Request Output # / General Purpose I/O 44.

General Purpose I/O 46 / Infrared Receive Input.

Infrared Transmit Output / General Purpose I/O 47 / Serial Flash chip enable 2 / Power-On Strapping 9.

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Table 6-5. General Purpose I/O Group 5 (Set 5)

Pin(s) No. Symbol Attribute Description

48 VIDO7/

GP50

10 FAN_CTL2/

GP51

9 FAN_TAC2/

GP52

77 SUSC#/

GP53

73 PME#/

GP54

85 RSMRST#/

CIRRX/

GP55

83 MCLK/

GP56

82 MDAT/

GP57

DOD8/

DIOD16

DOD8/ DIOD8

DI/

DIOD8

DI/

DIOD8 DOD8/

DI/

DIOD8

DIOD24/

DIOD24

DIOD24/

DIOD24

VID output 7 / General Purpose I/O 50.

Fan Control Output 2 / General Purpose I/O 51.

Fan Tachometer Input 2 / General Purpose I/O 52.

SUSC# Input / General Purpose I/O 53

Power Management Event # / General Purpose I/O 54.

Resume Reset # / Consumer Infrared Receive Input / General Purpose I/O 55.

PS/2 Mouse Clock/ General Purpose I/O 56. PS/2 Mouse Data/ General Purpose I/O 57.

Table 6-6. General Purpose I/O Group 6 (Set 6)

Pin(s) No. Symbol Attribute Description

81 KCLK/

GP60

80 KDAT/

GP61

45 KRST#/

GP62

6 SIN2/

GP63

3 DSR2#/

GP64

128 CTS2#/

GP65

127 RI2#/

GP66

126 DCD2#/

GP67

DIOD24/

DIOD24

DIOD24/

DIOD24

DO16/

DIOD16

DI/

DIOD8

DI/

DIOD8

DI/

DIOD8

DI/

DIOD8

DI/

DIOD8

Keyboard Clock/ General Purpose I/O 60.

Keyboard Data/ General Purpose I/O 61.

Keyboard Reset/ General Purpose I/O 62.

Serial Data In 2/ General Purpose I/O 63.

Data Set Ready 2 #/ General Purpose I/O 64.

Clear to Send 2 #/ General Purpose I/O 65.

Ring Indicator 2 #/ General Purpose I/O 66.

Data Carrier Detect 2 #/ General Purpose I/O 67.

List of GPIO Pins

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Power On Strapping Options and Special Pin Routings

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7. Power On Strapping Options and Special Pin Routings

Table 7-1. Power On Strapping Options

JP1

Pin 121

JP2

Pin 122

JP3

Pin 124

JP4

Pin 1

[JP5:JP7]

Pin 2 & 46

JP6

Pin 5

Symbol Value Description

1 Disabled

Flashseg1_EN

Flash I/F Address Segment FFF8_0000~FFFF_FFFF &

000E_0000~000F_FFFF is enabled.

FLH_SO2 is selected as the Serial Flash I/F SO pin.

SerFlh_SO_SEL

0 FLH_SO1 is selected as the Serial Flash I/F SO pin.

CHIP_SEL -- Chip selection in Configuration

The output buffers of PCIRST1#, PCIRST2#, PCIRST3#,and

BUF_SEL

PCIRST4# are open-drain

0 The output buffers are push-pull.

11 The default value of EC Index 15h/16h/17h is 00h.

10 The default value of EC Index 15h/16h/17h is 20h.

FAN_CTL_SEL

01 The default value of EC Index 15h/16h/17h is 40h.

00 The default value of EC Index 15h/16h/17h is 60h.

1 The threshold voltage of VID is 2.0/0.8V.

VID_ISEL

0 The threshold voltage of VID is 0.8/0.4V.

JP7

Pin 46

JP8

Pin 38

WDT_EN

1 Disable WDT to rest PWROK

0 Enable WDT to rest PWROK

1 Disable VID output pins

VIDO_EN

0 Enable VID output pins

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Intel

ICH

VCCH

System

On-Off

Button

Figure 7-1. IT8718F Special Applications Circuitry for Intel ICH

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PWBTN#

PWRON#

(72)

PANSWH#

(75)

SUSC#

(77)

3VSBSW#(79)

IT8718F

SUSB#

(71)

PSON#(76)

To switch Suspendto-RAM power

ATX

Power Supply

PSON#

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Configuration

8. Configuration

8.1 Configuring Sequence Description

After the hardware reset or power-on reset, the IT8718F enters the normal mode with all logical devices disabled except KBC. The initial state (enable bit) of this logical device (KBC) is determined by the state of pin 121 (DTR1#) at the falling edge of the system reset during power-on reset.

Hardware Reset

Any other I/O transition cycle

Wait for key string

I/O write to 2Eh

Is the data

"87h" ?

Any other I/O transition cycle

Check Pass key

I/O write to 2Eh

Next Data?

Last Data?

MB PnP Mode

There are three steps to completing the configuration setup: (1) Enter the MB PnP Mode; (2) Modify the data of configuration registers; (3) Exit the MB PnP Mode. The undesired result may occur if the MB PnP Mode is not exited normally.

(1) Enter the MB PnP Mode

To enter the MB PnP Mode, four special I/O write operations are to be performed during the Wait for Key state. To ensure the initial state of the key-check logic, it is necessary to perform four write operations to the Special Address port (2Eh). Two different enter keys are provided to select configuration ports (2Eh/2Fh or 4Eh/4Fh) of the next step.

Address port Data port

87h, 01h, 55h, 55h; 2Eh 2Fh

or 87h, 01h, 55h, AAh; 4Eh 4Fh

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(2) Modify the Data of the Registers

All configuration registers can be accessed after entering the MB PnP Mode. Before accessing a selected register, the content of Index 07h must be changed to the LDN to which the register belongs, except some Global registers.

(3) Exit the MB PnP Mode

Set bit 1 of the configure control register (Index=02h) to “1” to exit the MB PnP Mode.

Description of the Configuration Register All the registers except APC/PME registers will be reset to the default state when RESET is activated.

8.2 Description of the Configuration Registers

All the registers except APC/PME’ registers will be reset to the default state when RESET is activated.

Table 8-1. Global Configuration Registers

LDN Index R/W Reset Configuration Register or Action

All 02h W NA Configure Control

All 07h R/W NA Logical Device Number (LDN)

All 20h R 87h Chip ID Byte 1

All 21h R 18h Chip ID Byte 2

All 22h W-R 01h Configuration Select and Chip Version (01h for C version)

All 23h R/W 00h Clock Selection Register

All 24h R/W 00h Software Suspend and Flash I/F Control Register

07h

Note1

25h R/W 01h

Note1

26h R/W 00h

Note1

27h R/W 00h GPIO Set 3 Multi-Function Pin Selection Register

Note1

28h R/W 40h

Note1

29h R/W 00h

Note1

2Ah R/W 00h

GPIO Set 1 Multi-Function Pin Selection Register

Bit 0 powered by VCCH.

GPIO Set 2 Multi-Function Pin Selection Register

Bit 0-7 powered by VCCH.

GPIO Set 4 Multi-Function Pin Selection Register

Bit 0-7 powered by VCCH.

GPIO Set 5 Multi-Function Pin Selection Register

Bit 3-5 powered by VCCH.

Extended 1 Multi-Function Pin Selection Register

Bit 0-7 powered by VCCH.

All 2Bh R/W 00h Logical Block Configuration Lock Register

07h

F4h

Note1

2Ch R/W 00h

Note1

2Eh R/W 00h Test 1 Register

Note1

2Fh R/W 00h Test 2 Register

Extended 2 Multi-Function Pin Selection Register

Bit 0-7 powered by VCCH.

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Configuration

Table 8-2. FDC Configuration Registers

LDN Index R/W Reset Configuration Register or Action

00h 30h R/W 00h FDC Activate

00h 60h R/W 03h FDC Base Address MSB Register

00h 61h R/W F0h FDC Base Address LSB Register

00h 70h R/W 06h FDC Interrupt Level Select

00h 74h R/W 02h FDC DMA Channel Select

00h F0h R/W 00h FDC Special Configuration Register 1

00h F1h R/W 00h FDC Special Configuration Register 2

Table 8-3. Serial Port 1 Configuration Registers

LDN Index R/W Reset Configuration Register or Action

01h 30h R/W 00h Serial Port 1 Activate

01h 60h R/W 03h Serial Port 1 Base Address MSB Register

01h 61h R/W F8h Serial Port 1 Base Address LSB Register

01h 70h R/W 04h Serial Port 1 Interrupt Level Select

01h F0h R/W 00h Serial Port 1 Special Configuration Register 1

01h F1h R/W 50h Serial Port 1 Special Configuration Register 2

01h F2h R/W 00h Serial Port 1 Special Configuration Register 3

01h F3h R/W 7Fh Serial Port 1 Special Configuration Register 4

Table 8-4. Serial Port 2 Configuration Registers

LDN Index R/W Reset Configuration Register or Action

02h 30h R/W 00h Serial Port 2 Activate

02h 60h R/W 02h Serial Port 2 Base Address MSB Register

02h 61h R/W F8h Serial Port 2 Base Address LSB Register

02h 70h R/W 03h Serial Port 2 Interrupt Level Select

02h F0h R/W 00h Serial Port 2 Special Configuration Register 1

02h F1h R/W 50h Serial Port 2 Special Configuration Register 2

02h F2h R/W 00h Serial Port 2 Special Configuration Register 3

02h F3h R/W 7Fh Serial Port 2 Special Configuration Register 4

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Table 8-5. Parallel Port Configuration Registers

LDN Index R/W Reset Configuration Register or Action

03h 30h R/W 00h Parallel Port Activate

03h 60h R/W 03h Parallel Port Primary Base Address MSB Register

03h 61h R/W 78h Parallel Port Primary Base Address LSB Register

03h 62h R/W 07h Parallel Port Secondary Base Address MSB Register

03h 63h R/W 78h Parallel Port Secondary Base Address LSB Register

03h 70h R/W 07h Parallel Port Interrupt Level Select

03h 74h R/W 03h Parallel Port DMA Channel Select

03h F0h R/W 03h

Note3

Parallel Port Special Configuration Register

Note2

Table 8-6. Environment Controller Configuration Registers

LDN Index R/W Reset Configuration Register or Action

04h 30h R/W 00h Environment Controller Activate

04h 60h R/W 02h Environment Controller Base Address MSB Register

04h 61h R/W 90h Environment Controller Base Address LSB Register

04h 62h R/W 02h PME Direct Access Base Address MSB Register

04h 63h R/W 30h PME Direct Access Base Address LSB Register

04h 70h R/W 09h Environment Controller Interrupt Level Select

04h F0h R/W 00h APC/PME Event Enable Register

04h F1h R/W 00h APC/PME Status Register

04h F2h R/W 00h APC/PME Control Register 1

04h F3h R/W 00h Environment Controller Special Configuration Register

04h F4h R-R/W 00h APC/PME Control Register 2

04h F5h R/W - APC/PME Special Code Index Register

04h F6h R/W - APC/PME Special Code Data Register

Table 8-7. KBC(Keyboard) Configuration Registers

LDN Index R/W Reset Configuration Register or Action

05h 30h R/W 01h KBC Activate

05h 60h R/W 00h KBC Data Base Address MSB Register

05h 61h R/W 60h KBC Data Base Address LSB Register

05h 62h R/W 00h KBC Command Base Address MSB Register

05h 63h R/W 64h KBC Command Base Address LSB Register

05h 70h R/W 01h KBC Interrupt Level Select

05h 71h R-R/W 02h KBC Interrupt Type

Note5

05h F0h R/W 00h KBC Special Configuration Register

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Configuration

Table 8-8. KBC(Mouse) Configuration Registers

LDN Index R/W Reset Configuration Register or Action

06h 30h R/W 00h KBC (Mouse) Activate

06h 70h R/W 0Ch KBC (Mouse) Interrupt Level Select

06h 71h R-R/W 02h KBC (Mouse) Interrupt Type

Note5

06h F0h R/W 00h KBC (Mouse) Special Configuration Register

Table 8-9. GPIO Configuration Registers

LDN Index R/W Reset Configuration Register or Action

07h 60h R/W 00h SMI# Normal Run Access Base Address MSB Register

07h 61h R/W 00h SMI# Normal Run Access Base Address LSB Register

07h 62h R/W 00h Simple I/O Base Address MSB Register

07h 63h R/W 00h Simple I/O Base Address LSB Register

07h 64h R/W 00h Serial Flash I/F Base Address MSB Register

07h 65h R/W 00h Serial Flash I/F Base Address LSB Register

07h 70h R/W 00h Panel Button De-bounce Interrupt Level Select Register

07h 71h R/W 00h Watch Dog Timer Control Register

07h 72h R/W 001s0000b Watch Dog Timer Configuration Register

07h 73h R/W 38h Watch Dog Timer Time-out Value (LSB) Register

07h 74h R/W 00h Watch Dog Timer Time-out Value (MSB) Register

07h B0h R/W 00h GPIO Set 1 Pin Polarity Register

07h B1h R/W 00h GPIO Set 2 Pin Polarity Register

07h B2h R/W 00h GPIO Set 3 Pin Polarity Register

07h B3h R/W 00h GPIO Set 4 Pin Polarity Register

07h B4h R/W 00h GPIO Set 5 Pin Polarity Register

07h B5h R/W 00h GPIO Set 6 Pin Polarity Register

07h B8h R/W 00h GPIO Set 1 Pin Internal Pull-up Enable Register

07h B9h R/W 00h GPIO Set 2 Pin Internal Pull-up Enable Register

07h BAh R/W 00h GPIO Set 3 Pin Internal Pull-up Enable Register

07h BBh R/W 00h GPIO Set 4 Pin Internal Pull-up Enable Register

07h BCh R/W 00h GPIO Set 5 Pin Internal Pull-up Enable Register

07h BDh R/W 00h GPIO Set 6 Pin Internal Pull-up Enable Register

07h C0h R/W 01h

07h C1h R/W 00h

Simple I/O Set 1 Enable Register

Bit-0 powered by VCCH.

Simple I/O Set 2 Enable Register

Bit 0-7 powered by VCCH.

07h C2h R/W 00h Simple I/O Set 3 Enable Register

07h C3h R/W 40h

Simple I/O Set 4 Enable Register

Bit 0-7 powered by VCCH.

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07h C4h R/W 00h

Simple I/O Set 5 Enable Register

Bit 0-7 powered by VCCH.

07h C8h R/W 01h Simple I/O Set 1 Output Enable Register

07h C9h R/W 00h Simple I/O Set 2 Output Enable Register

07h CAh R/W 00h Simple I/O Set 3 Output Enable Register

07h CBh R/W 40h

07h CCh R/W 00h

Simple I/O Set 4 Output Enable Register

Bit 0-7 powered by VCCH.

Simple I/O Set 5 Output Enable Register

Bit 0-7 powered by VCCH.

Table 8-10. GPIO Configuration Registers

LDN Index R/W Reset Configuration Register or Action

07h E0h R/W 00h Panel Button De-bounce 0 Input Pin Mapping Register

07h E1h R/W 00h Panel Button De-bounce 1 Input Pin Mapping Register

07h E2h R/W 00h IRQ External Routing 0 Input Pin Mapping Register

07h E3h R/W 00h IRQ External Routing 1 Input Pin Mapping Register

07h E4h R/W 00h

IRQ External Routing 1-0 Interrupt Level Selection Register

07h E5h R/W 00h VID Watchdog Timer 0 Value Register

07h E6h R/W 00h VID Watchdog Timer 1 Value Register

07h E7h R/W 00h Reserved

07h F0h R/W 00h SMI# Control Register 1

07h F1h R/W 00h SMI# Control Register 2

07h F2h R/W 00h SMI# Status Register 1

07h F3h R/W 00h SMI# Status Register 2

07h F4h R/W 00h SMI# Pin Mapping Register

07h F5h R/W 00h

Hardware Monitor Thermal Output Pin Mapping Register

Bit 0-7 powered by VCCH.

07h F6h R/W 00h Hardware Monitor Alert Beep Pin Mapping Register

07h F7h R/W 00h Keyboard Lock Pin Mapping Register

07h F8h R/W 00h

07h F9h R/W 00h

07h FAh R/W 00h

07h FBh R/W 00h

GP LED Blinking 1 Pin Mapping Register

Bit 0-7 powered by VCCH.

GP LED Blinking 1 Control Register

Bit 0-7 powered by VCCH.

GP LED Blinking 2 Pin Mapping Register

Bit 0-7 powered by VCCH.

GP LED Blinking 2 Control Register

Bit 0-7 powered by VCCH.

07h FCh R/W-R --h VID Input Register

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07h FDh R/W 00h

VID Output Register

Bit 0-7 powered by VCCH.

Configuration

07h FEh R/W 00h VID Watchdog Timer Control Register

07h FFh R/W 00h

VID Watchdog timer Control Register

Table 8-11. Consumer IR Configuration Registers

LDN Index R/W Reset Configuration Register or Action

0Ah 30h R/W 00h Consumer IR Activate

0Ah 60h R/W 03h Consumer IR Base Address MSB Register

0Ah 61h R/W 10h Consumer IR Base Address LSB Register

0Ah 70h R/W 0Bh Consumer IR Interrupt Level Select

0Ah F0h R/W 00h Consumer IR Special Configuration Register

Note 1: All these registers can be read from all LDNs. Note 2: When the ECP mode is not enabled, this register is read only as “04h”, and cannot be written. Note 3: When the bit 2 of the Primary Base Address LSB Register of Parallel Port is set to 1, the EPP mode

cannot be enabled. Bit 0 of this register is always 0.

Note 4: These registers are read only unless the write enable bit (Index=F0h) is asserted.

8.2.1 Logical Device Base Address

The base I/O range of logical devices shown below is located in the base I/O address range of each logical device.

Table 8-12. Base Address of Logical Devices

Logical Devices Address Notes

LDN=0 FDC Base + (2 - 5) and + 7

LDN=1 SERIAL PORT 1 Base + (0 -7)

LDN=2 SERIAL PORT 2 Base1 + (0 -7) COM port

LDN=3 PARALLEL PORT

LDN=4 Environment Controller

Base1 + (0 -3)

Base1 + (0 -7)

Base1 + (0 -3) and Base2 + (0 -3)

Base1 + (0 -7) and Base2 + (0 -3)

Base3

Base1 + (0 -7)

Base2 + (0 -3)

SPP

SPP+EPP

SPP+ECP

SPP+EPP+ECP

POST data port

Environment Controller

PME#

LDN=5 KBC Base1 + Base2 KBC

LDN=A Consumer IR Base + (0 -7)

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8.3 Global Configuration Registers (LDN: All)

8.3.1 Configure Control (Index=02h)

This register is write only. Its values are not sticky; that is to say, a hardware reset will automatically clear

the bits, and does not require the software to clear them.

Bit Description

7-2

Reserved

1 Returns to the “Wait for Key” state. This bit is used when the configuration sequence is

completed.

0 Resets all logical devices and restores configuration registers to their power-on states.

8.3.2 Logical Device Number (LDN, Index=07h)

This register is used to select the current logical devices. By reading from or writing to the configuration of I/O, Interrupt, DMA and other special functions, all registers of the logical devices can be accessed. In addition,

ACTIVATE command is only effective for the selected logical devices. This register is read/write.

8.3.3 Chip ID Byte 1 (Index=20h, Default=87h) This register is the Chip ID Byte 1 and is read only. Bits [7:0]=87h when read.

8.3.4 Chip ID Byte 2 (Index=21h, Default=18h) This register is the Chip ID Byte 2 and is read only. Bits [7:0]=18h when read.

8.3.5 Configuration Select and Chip Version (Index=22h, Default=01h)

Bit Description

Configuration Select

This bit is used to select the chip, which needs to be configured. When there are two IT8718F chips in a system, and “1” is written, this bit will select JP3=1 (power-on strapping value of SOUT1) to be configured. The chip with JP3=0 will exit the configuration mode. To write “0”, the chip with JP3=0 will be configured and the chip with JP3=0 will exit. If no write operations occur on this register, both chips will be configured.

6-4 3-0

Reserved Version

0001b for C version.

8.3.6 Clock Selection Register (Index=23h, Default=00h)

Bit Description

7-6

XLOCK select

These two bits determine the XLOCK function. 00: Software XLOCK (default) 01: Reserved 10: Pin 48 (GP50)

11: Pin 11 (GP37)

Reserved

Clock Source Select of Watch Dog Timer

0: Internal oscillating clock (default) 1: External CLKIN

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Configuration

Bit Description

3-2

Selects the delay of PWROK1/2 ( Powered by VSB )

00: POWOK1/2 will be delayed 300 ~600ms from VCC5V > 4.0V. 01: POWOK1/2 will be no delay from VCC5V > 4.0V. 10: POWOK1/2 will be delayed 150 ~300ms from VCC5V > 4.0V. 11: Reserved.

Reserved

CLKIN Frequency

0: 48 MHz. 1: 24 MHz.

8.3.7 Software Suspend and Flash I/F Control Register (Index=24h, Default=00s0s0s0b, MB PnP)

Bit Description

7-6

Reserved

Serial Flash I/F SO Selection

0: Pin 29 1: Pin 87

LPC Memory/FWM write to Serial Flash I/F Enable

0: Disable (default) 1: Enable

Flash I/F Address Segment 3 (FFF8_0000h-FFFD_FFFFh, FFFE_0000h-FFFE_FFFFh)

0: Disable 1: Enable

Flash I/F Address Segment 2 (FFEF_0000h-FFEF_FFFFh, FFEE_0000h-FFEE_FFFFh)

0: Disable (default) 1: Enable

Flash I/F Address Segment 1 (FFFE_0000h_FFFF_FFFFh, 000E_0000h-000F_FFFFh)

0: Disable 1: Enable

Software Suspend

This register is the Software Suspend register. When the bit 0 is set, the IT8718F enters the “Software Suspend” state. All the devices, except KBC, remain inactive until this bit is cleared or when the wake-up event occurs. The wake-up event occurs at any transition on signals RI1# (pin

119) and Rl2# (pin 127). 0: Normal 1: Software Suspend

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8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h)

If the enabled bits are not set, the multi-function pins will perform the original functions. On the other hand, if they are set, they will perform the GPIO functions. This register can be read from any LDN, but can only be written if LDN=07h.

Bit Description

Function Selection of pin 28

0: VIDO6 1: General Purpose I/O 17 (GP17)

Function Selection of pin 29

0: Reserved 1: General Purpose I/O 16 (GP16)

Function Selection of pin 30 if bit5 of index 2A is 1

0: Consumer Infrared Transmit Output (CIRTX) 1: Reserved

Function Selection of pin 31 if bit4 of index 2A is 1

0: Reserved 1: General Purpose I/O 14 (GP14)

Function Selection of pin 32 if bit3 of index 2A is 1

0: Reserved 1: General Purpose I/O 13 (GP13)

Function Selection of pin 33 if bit2 of index 2A is 1

0: Reserved 1: General Purpose I/O 12 (GP12)

Function Selection of pin 34 if bit1 of index 2A is 1

0: Reserved 1: General Purpose I/O 11 (GP11)

Function Selection of pin 84 if bit0 of index 2A is 1

0: Reserved 1: General Purpose I/O 10 (GP10)

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Configuration

8.3.9 GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h)

Bit Description

Function Selection of pin 20

0: VIDO5 1: General Purpose I/O 27 (GP27)

Function Selection of pin 21

0: VIDO4

1: General Purpose I/O 26 (GP26)

Function Selection of pin 22

0: VIDO3/FAN_TAC4 1: General Purpose I/O 25 (GP25)

Function Selection of pin 23

0: VIDO2/FAN_TAC5 1: General Purpose I/O 24 (GP24)

Function Selection of pin 24

0: SI 1: General Purpose I/O 23 (GP23)

Function Selection of pin 25

0: SCK

1: General Purpose I/O 22 (GP22)

Function Selection of pin 26

0: VIDO1 1: General Purpose I/O 21 (GP21)

Function Selection of pin 27

0: VIDO0

1: General Purpose I/O 20 (GP20)

8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h)

Bit Description

Function Selection of pin 11

0: Fan Tachometer Input 3 (FAN_TAC3) 1: General Purpose I/O 37 (GP37)

Function Selection of pin 12

0: Fan Control Output 3 (FAN_CTL3) 1: General Purpose I/O 36 (GP36)

Function Selection of pin 13

0: Voltage ID5 (VID5) 1: General Purpose I/O 35 (GP35)

Function Selection of pin 14

0: Voltage ID4 (VID4) 1: General Purpose I/O 34 (GP34)

Function Selection of pin 16

0: Voltage ID3 (VID3)

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Bit Description

1: General Purpose I/O 33 (GP33)

Function Selection of pin 17

0: Voltage ID2 (VID2) 1: General Purpose I/O 32 (GP32)

Function Selection of pin 18

0: Voltage ID1 (VID1) 1: General Purpose I/O 31 (GP31)

Function Selection of pin 19

0: Voltage ID0 (VID0) 1: General Purpose I/O 30 (GP30)

8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h)

Bit Description

Function Selection of pin 66

0: Infrared Transmit Output (IRTX) 1: General Purpose I/O 47 (GP47)

Function Selection of pin 70

0: Infrared Receive Input (IRRX) 1: General Purpose I/O 46 (GP46)

Function Selection of pin 71

0: SUSB# 1: Reserved

Function Selection of pin 72

0: Power On Request Output # (PWRON#) 1: General Purpose I/O 44 (GP44)

Function Selection of pin 75

0: Main Power Switch Button Input # (PANSWH#) 1: General Purpose I/O 43 (GP43)

Function Selection of pin 76

0: Power Supply ON-Off Control Output # (PSON#) 1: General Purpose I/O 42 (GP42)

Function Selection of pin 78

0: PWROK2 1: General Purpose I/O 41 (GP41)

Function Selection of pin 79

0: 3VSBSW# 1: General Purpose I/O 40 (GP40)

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Configuration

8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h)

Bit Description

Function Selection of pin 6, 3, 128, 127, 126

0: SIN2, DSR2#, CTS2#, RI2, DCD2#. 1: General Purpose I/O 63, 64, 65, 66, 67.

Function Selection of pin 83, 82, 81, 80, 45

0: MCLK, MDAT, KCLK, KDAT, KRST# 1: General Purpose I/O 56, 57, 60, 61, 62

Function Selection of pin 85

0: Consumer Infrared Receive Input (CIRRX) or RSMRST#. RSMRST# is an open-drain output

function, which is active low about 16ms when VCCH5V is power-on.

1: General Purpose I/O 55 (GP55).

Function Selection of pin 73

0: Power Management Event # (PME#) 1: General Purpose I/O 54 (GP54)

Function Selection of pin 77

0: SUSC# 1: General Purpose I/O 53 (GP53)

Function Selection of pin 9

0: Fan Tachometer Input 2 (FAN_TAC2) 1: General Purpose I/O 52 (GP52)

Function Selection of pin 10.

0: Fan Control Output 2 (FAN_CTL2) 1: General Purpose I/O 51 (GP51)

Function Selection of pin 48

0: VIDO7 1: General Purpose I/O 50 (GP50)

8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h)

This register can be read from any LDN, but can only be written if LDN=07h.

Bit Description

Enable 3VSBSW# (For System Suspend-to-RAM)

0: 3VSBSW# will be always inactive. 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.

Multi-function selection of pin 53

0: MTRB# 1: Reserved (EC index 0Ah/bit<6:4>≠000b external thermal sensor host enable, pin-53 swap to external thermal function.)

Extended multi-function selection of 30

0: RESETCON# 1: Determined by bit5 of GPIO Set 1 Multi-function Selection Register (Index 25h)

Extended multi-function selection of pin 31

0: PCIRST1# 1: Determined by bit4 of GPIO Set 1 Multi-function Selection Register (Index 25h)

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Extended multi-function selection of pin 32

0: PWROK1 1: Determined by bit3 of GPIO Set 1 Multi-function Selection Register (Index 25h)

Extended multi-function selection of pin 33

0: PCIRST2# 1: Determined by bit2 of GPIO Set 1 Multi-function Selection Register (Index 25h)

Extended multi-function selection of pin 34

0: PCIRST3# 1: Determined by bit1 of GPIO Set 1 Multi-function Selection Register (Index 25h)

Extended multi-function selection of pin 84

0: PCIRST4# 1: Determined by bit0 of GPIO Set 1 Multi-function Selection Register (Index 25h)

8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h)

When the lock function is enabled (bit7=1 or XLOCK# is low), configuration registers of the selected logical block and Clock Selection register (index = 23h), and this register will be read-only.

Bit Description

Software Lock Enable Once this bit is set to 1 by software, it can be only cleared by hardware reset.

0: Configuration lock is controlled by XLOCK#. (Default) 1: Configuration registers Logic Blocks selected by bits 6-0 and this register is read-only.

GPIO Select (LDN7)

0: GPIO Configuration registers are programmable.

1: GPIO Configuration registers are read-only if LOCK is enabled.

KBC (Keyboard) and KBC (Mouse) Select (LDN5 and LDN6)

0: KBC (Keyboard) and KBC (Mouse) Configuration registers are programmable. 1: KBC (Keyboard) and KBC (Mouse) Configuration registers are read-only if LOCK is enabled.

EC Select (LDN4)

0: EC Configuration registers are programmable. 1: EC Configuration registers are read-only if LOCK is enabled.

Parallel Port Select (LDN3)

0: Parallel Port Configuration registers are programmable. 1: Parallel Port Configuration registers are read-only if LOCK is enabled.

Serial Port 2 Select. (LDN2)

0: Serial Port 2 Configuration registers are programmable. 1: Serial Port 2 Configuration registers are read-only if LOCK is enabled.

Serial Port 1 Select. (LDN1)

0: Serial Port 1 Configuration registers are programmable. 1: Serial Port 1 Configuration registers are read-only if LOCK is enabled.

FDC Select (LDN0)

The lock function will not affect bit0 of FDC Special Configuration register (software write protect). 0: FDC Configuration registers are programmable.

1: FDC Configuration registers are read-only (except Software Write Protect bit) if LOCK is enabled.

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Configuration

8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh)

This register can be read from any LDN, but can only be written if LDN=07h.

Bit Description

Enables VIN6 to GPIO

0: Disable 1: Enable

Reserved (K8 PWRON_SEL)

Reserved

Extended multi-function selection of pin23

0: Disable FAN_TAC set 5 1: Enable FAN_TAC set 5

Extended multi-function selection of pin 22

0: Disable FAN_TAC set 4

1: Enable FAN_TAC set 4 2 1

Reserved Enables PCIRSTIN# (pin 91), and switches the VIN7 function to the internal voltage divider for VCCH5V

0: Disable 1: Enable

Enables ATXPG (pin 95), and switches the VIN3 function to the internal voltage divider for VCC5V

0: Disable 1: Enable

8.3.16 Test 1 Register (Index=2Eh, Default=00h)

This register is the Test 1 Register and is reserved for ITE. It should not be set.

8.3.17 Test 2 Register (Index=2Fh, Default=00h)

This register is the Test 2 Register and is reserved for ITE. It should not be set.

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8.4 FDC Configuration Registers (LDN=00h)

8.4.1 FDC Activate (Index=30h, Default=00h)

Bit Description

7-1

Reserved FDC Enable

1: Enable 0: Disable

8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4

Read only, with “0h” for Base Address [15:12].

3-0 Mapped as Base Address [11:8].

8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address [7:3].

Read only as “000b.”

8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h)

Bit Description

7-4 3-0 Select the interrupt level

Reserved with default “0h.”

Note1

for FDC.

8.4.5 FDC DMA Channel Select (Index=74h, Default=02h)

Bit Description

7-3 2-0 Select the DMA channel

Reserved with default “00h.”

Note2

for FDC.

8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h)

Bit Description

7-5

Reserved with default “00h.”

FDD I/F Input pins internal pull-up control

0: Disable 1: Enable

3 1: IRQ sharing

0: Normal IRQ

2 1: Swap Floppy Drives A, B

0: Normal

1 1: 3-mode

0: AT-mode

0 1: Software Write Protect

0: Normal

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8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h)

Bit Description

7-4

Reserved with default “00h”

3-2 FDD B Data Rate Table Select (DRT1-0) 1-0 FDD A Data Rate Table Select (DRT1-0)

Configuration

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8.5 Serial Port 1 Configuration Registers (LDN=01h)

8.5.1 Serial Port 1 Activate (Index=30h, Default=00h)

Bit Description

7-1

Reserved

Serial Port 1 Enable

1: Enable 0: Disable

8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.5.3 Serial Port 1 Base Address LSB Register (Index= 61h, Default=F8h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address[7:3] Read only as “000b”

8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h)

Bit Description

7-4 3-0

Reserved with default “0h” Select the interrupt level

Note1

for Serial Port 1

8.5.5 Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h)

Bit Description

6-4

Reserved Serial Port 1 Mode

Note3

000: Standard (default) 001: IrDA 1.0 (HP SIR) 010 : ASKIR else : Reserved

Reserved with default “0”

2-1

Clock Source

00: 24 MHz/13 (Standard) 01: 24 MHz/12 10: Reserved 11: Reserved

0 1: IRQ sharing

0: Normal

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Configuration

8.5.6 Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h)

Bit Description

7 1: No transmissions delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX

mode.

0: Transmission delays (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode.

6 1: No receptions delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.

0: Reception delays (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.

Single Mask Mode

When set, the RX of UART is masked under TX transmission.

4 1: Half Duplex (default)

0: Full Duplex

SIR RX polarity

1: Active low 0: Active high

2-0

Reserved

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8.6 Serial Port 2 Configuration Registers (LDN=02h)

8.6.1 Serial Port 2 Activate (Index=30h, Default=00h)

Bit Description

7-1

Reserved

Serial Port 2 Enable

1: Enable 0: Disable

8.6.2 Serial Port 2 Base Address MSB Register (Index= 60h, Default=02h)

Bit Description

7-4 3-0

Read only with “0h” for Base Address [15:12] Read/write, mapped as Base Address [11:8]

8.6.3 Serial Port 2 Base Address LSB Register (Index= 61h, Default=F8h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address [7:3] Read only as “000b”

8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h)

Bit Description

7-4 3-0 Select the interrupt level

Reserved with default “0h”

Note1

for Serial Port 2

8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)

Bit Description

6-4

Reserved Serial Port 2 Mode

Note3

000: Standard (default) 001: IrDA 1.0 (HP SIR) 010 : ASKIR else : Reserved

Reserved with default “0”

2-1

Clock Source

00: 24 MHz/13 (Standard) 01: 24 MHz/12 10: Reserved 11: Reserved

0 1: IRQ sharing

0: Normal

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Configuration

8.6.6 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)

Bit Description

7 1: No transmission delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode.

0: Transmission delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode.

6 1: No reception delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.

0: Reception delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.

Single Mask Mode: When set, the RX of UART is masked under TX transmission.

4 1: Half Duplex (default)

0: Full Duplex

SIR RX polarity

1: Active low 0: Active high

2-0

Reserved

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8.7 Parallel Port Configuration Registers (LDN=03h)

8.7.1 Parallel Port Activate (Index=30h, Default=00h)

Bit Description

7-1

Reserved

Parallel Port Enable

1: Enable 0: Disable

8.7.2 Parallel Port Primary Base Address MSB Register (Index =60h, Default=03h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)

If the bit 2 is set to 1, the EPP mode is disabled automatically.

Bit Description

7-2 1-0

Read/write, mapped as Base Address[7:2] Read only as “00b”

8.7.4 Parallel Port Secondary Base Address MSB Register (Index =62h, Default=07h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h)

Bit Description

7-2 1-0

Read/write, mapped as Base Address[7:2] Read only as “00b”

8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h)

Bit Description

7-4 3-0

Reserved with default “0h” Select the interrupt level

Note1

for Parallel Port

8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h)

Bit Description

7-3 2-0

Reserved with default “00h” Select the DMA channel

Note2

for Parallel Port

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Configuration

8.7.8 Parallel Port Special Configuration Register (Index=F0h, Default=03h)

Bit Description

7-4

Reserved

3 1: POST Data Port Disable

0: POST Data Port Enable

2 1: IRQ sharing

0: Normal

1-0

Parallel Port Modes

00 : Standard Parallel Port mode (SPP) 01 : EPP mode 10 : ECP mode 11 : EPP mode & ECP mode

If the bit 1 is set, the ECP mode will be enabled. If the bit 0 is set, the EPP mode will be enabled. These two bits are independent. However, according to the EPP spec., when Parallel Port Primary Base Address LSB Register bit 2 is set to 1, the EPP mode cannot be enabled.

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8.8 Environment Controller Configuration Registers (LDN=04h)

8.8.1 Environment Controller Activate Register (Index=30h, Default=00h)

Bit Description

7-1

Reserved

Environment Controller Enable

1: Enable 0: Disable

This is a read/write register.

8.8.2 Environment Controller Base Address MSB Register (Index=60h, Default=02h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.8.3 Environment Controller Base Address LSB Register (Index=61h, Defa ult=90h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address[7:3] Read only as “000b”

8.8.4 PME Direct Access Base Address MSB Register (Index=62h, Default=02h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.8.5 PME Direct Access Base Address LSB Register (Index=63h, Default=30h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address[7:3] Read only as “000b.”

8.8.6 Environment Controller Interrupt Level Select (Index=70h, Default=09h)

Bit Description

7-4 3-0

Reserved with default “0h” Select the interrupt level

Note1

for Environment Controller

8.8.7 APC/PME Event Enable Register (PER) (Index=F0h, Default=00h)

Bit Description

7 It is set to 1 when VCCH is off. Write 1 to clear this bit. This bit is ineffective if 0 is written to this

bit.

Reserved

Reserved with default “0h”

4 0: PS/2 Mouse event disabled

1: PS/2 Mouse event enabled

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Configuration

3 0: Keyboard event disabled

1: Keyboard event enabled

2 0: RI2# event disabled

1: RI2# event enabled

1 0: RI1# event disabled

1: RI1# event enabled

0 0: CIR event disabled

1: CIR event enabled

8.8.8 APC/PME Status Register (PSR) (Index=F1h, Default=00h)

Bit Description

7 It is set to 1 when VCC is on at the previous AC power failure and 0 when VCC is off. 6

Reserved

4 0: No PS/2 Mouse Event Detected

1: PS/2 Mouse Event Detected

3 0: No Keyboard Event Detected

1: Keyboard Event Detected

2 0: No RI2# Event Detected

1: RI2# Event Detected

1 0: No RI1# Event Detected

1: RI1# Event Detected

0 0: No CIR event Detected

1: CIR event Detected

8.8.9 APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)

Bit Description

PER and PSR normal run access enabled

PME# output control

0: Enable

1: Disable

This bit is restored automatically to the previous VCC state before the power failure occurs.

Disables all APC events after the power failure occurs, excluding PANSWH#.

Keyboard event mode selection when VCC is on

1: Determined by PCR 2 0: Pulse falling edge on KCLK

Mouse event when VCC is off

1: Click Key twice sequentially 0: Pulse falling edge on MCLK

Mouse event when VCC is on

1: Click Key twice sequentially 0: Pulse falling edge on MCLK

CIRRX Pin Selection

1: Pin84 0: Pin85

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8.8.10 Env i ronment Controller Special Configuration Register (Index=F3h, Default=00h)

Bit Description

7-6

Scan frequency of H/W monitor

00: 1Hz 01: 2Hz 10: 4Hz

11: 8Hz

5-1

Reserved

0 1: IRQ sharing

0: Normal

8.8.11 APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h)

Bit Description

Disable KCLK/KDAT and MCLK/MDAT auto-swap

0: Enable 1: Disable

Reserved

PSON# state when VCCH is switched from off to on.

0: High-Z (default power OFF) 1: Inverting of PSIN

4 Masks PANSWH# power-on event

3-2

Key Number of the Keyboard power-up event

00: 5 (Key string mode), 3 (Stroke keys at same time mode) 01: 4 (Key string mode), 2 (Stroke keys at same time mode) 10: 3 (Key string mode), 1 (Stroke keys at same time mode) 11: 2 (Key string mode), Reserved (Stroke keys at the same time mode)

1-0

Keyboard power-up event mode selection

00: KCLK falling edge 01: Key string mode 10: Stroke keys at same time mode 11: Reserved

8.8.12 APC/PME Special Code Index Register (Index=F5h)

Bit Description

7-6 5-0

Reserved (should be “00”) Indicate which Identification Key Code or CIR code register is to be read/written via 0xF6

8.8.13 APC/PME Special Code Data Register (Index=F6h)

There are 5 bytes for the Key String mode, 3 bytes for Stroke Keys at the same time mode and CIR event codes.

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Configuration

8.9 KBC (keyboard) Configuration Registers (LDN=05h)

8.9.1 KBC (keyboard) Activate (Index=30h, Default=01h)

Bit Description

7-1

Reserved

KBC (keyboard) Enable

1: Enable 0: Disable

8.9.2 KBC (keyboard) Data Base Address MSB Register (Index=60h, Default=00h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address [15:12] Read/write, mapped as Base Address [11:8]

8.9.3 KBC (keyboard) Data Base Address LSB Register (Index=61h, Default=60h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0]

8.9.4 KBC (keyboard) Command Base Address MSB Register (Index=62h, Default=00h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.9.5 KBC (keyboard) Command Base Address LSB Register (Index=63h, Default=64h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0]

8.9.6 KBC (keyboard) Interrupt Level Select (Index=70h, Default=01h)

Bit Description

7-4 3-0

Reserved with default “0h” Select the interrupt level

Note1

for KBC (keyboard)

8.9.7 KBC (keyboard) Interrupt Type (Index=71h, Default=02h)

This register indicates the type of interrupt set for KBC (keyboard) and is read only as “02h” when bit 0 of the

KBC (keyboard) Special Configuration Register is cleared. When bit 0 is set, this type of interrupt can be selected as level or edge trigger.

Bit Description

7-2

Reserved

1 1: High Level

0: Low Level

0 1: Level Type

0: Edge Type

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8.9.8 KBC (keyboard) Special Configuration Register (Index=F0h, Def au lt=08h)

Bit Description

7-5

Reserved

4 1: IRQ sharing

0: Normal

3 1: KBC’s clock 8 MHz

0: KBC’s clock 12 MHz

2 1: Key lock enabled

0: Key lock disabled

1 1: Type of interrupt of KBC (keyboard) can be changed.

0: Type of interrupt of KBC (keyboard) is fixed.

Reserved

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Configuration

8.10 KBC (mouse) Configuration Registers (LDN=06h)

8.10.1 KBC (mouse) Activate (Index=30h, Default=00h)

Bit Description

7-1

Reserved

KBC (mouse) Enable

1: Enable 0: Disable

8.10.2 KBC (mouse) Interrupt Level Select (Index=70h, Default=0Ch)

Bit Description

7-4 3-0

Reserved with default “0h” Select the interrupt level

Note1

for KBC (mouse)

8.10.3 KBC (mouse) Interrupt Type (Index=71h, Default=02h)

This register indicates the type of interrupt used for KBC (mouse) and is read only as “02h” when bit 0 of the

KBC (mouse) Special Configuration Register is cleared. When bit 0 is set, the type of interrupt can be selected as level or edge trigger.

Bit Description

7-2

Reserved

1 1: High Level

0: Low Level

0 1: Level Type

0: Edge Type

8.10.4 KBC (mouse) Special Configuration Register (Index=F0h, Default=00h)

Bit Description

7-2

Reserved with default “00h”

1 1: IRQ sharing

0: Normal

0 1: Type of interrupt of KBC (mouse) can be changed

0: Type of interrupt of KBC (mouse) is fixed

8.11 GPIO Configuration Registers (LDN=07h)

8.11.1 SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address [15:12] Read/write, mapped as Base Address [11:8]

8.11.2 SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0]

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8.11.3 Simple I/O Base Address MSB Register (Index=62h, Default=00h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address [15:12] Read/write, mapped as Base Address [11:8]

8.11.4 Simple I/O Base Address LSB Register (Index=63h, Default=00h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0]

8.11.5 Serial Flash I/F Base Address MSB Register (Index=64h, Default=00h)

Bit Description

7-4 3-0

Read only as “0h” for Base Address [15:12] Read/write, mapped as Base Address [11:8]

8.11.6 Serial Flash I/F Base Address LSB Register (Index=65h, Default=00h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address [7:3] Read only as “000b”

8.11.7 Panel Button De-bounce Interrupt Lev el Select Register (Index=70h, Default=00h)

Bit Description

7-4 3-0

Reserved Select the interrupt level

Note1

for Panel Button De-bounce

8.11.8 Watch Dog Timer Control Register (Index=71h, Default=00h)

Bit Description

WDT is reset upon a CIR interrupt.

WDT is reset upon a KBC (mouse) interrupt.

WDT is reset upon a KBC (keyboard) interrupt.

Reserved

3-2

Reserved

Force Time-out

This bit is self-clearing.

WDT Status

1: WDT value reaches 0. 0: WDT value is not 0.

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Configuration

8.11.9 Watch Dog Timer Configuration Register (Index=72h, Default=001s0000b)

Bit Description

WDT Time-out value select 1

1: Second 0: Minute

WDT output through KRST (pulse) enable

1: Enable 0: Disable

WDT Time-out value Extra select

1: 64ms x WDT Timer-out value (default = 4s) 0: Determined by WDT Time-out value select 1 (bit 7 of this register)

WDT output through PWROK1/PWROK2 (pulse) enable

1: Enable 0: Disable

During LRESET#, this bit is select by JP7 power-on strapping option

3-0

Select the interrupt level Note1 for WDT

8.11.10 Watch Dog Timer Time-Out Value (LSB) Register (Index=73h, Default=38h)

Bit Description

7-0

WDT time-out value 7-0

8.11.11 Watch Dog Timer Time-Out Value (MSB) Register (Index=74h, Default=00h)

Bit Description

7-0

WDT time-out value 15-8

8.11.12 GPIO Pin Set 1, 2, 3, 4, 5 and 6 Polarity Registers (Index=B0h, B1h, B2h, B3h, B4h and B5h, Default=00h)

These registers are used to program the GPIO pin type as polarity inverting or non-inverting.

Bit Description

7-0 1: Inverting

0: Non-inverting

8.11.13 GPIO Pin Set 1, 3, 4, 5 and 6 Pin Internal Pull-up Enable Registers (Index=B8h, BAh, BBh, BCh and BDh, Default=00h)

These registers are used to enable the GPIO pin internal pull-up. (There is no internal P/U function for GPIO set 2.)

Bit Description

7-0 1: Enable

0: Disable

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8.11.14 Simple I/O Set 1, 2, 3, 4, 5 and 6 Enable Registers (Index=C0h, C1h, C2h, C3h C4 and C5h, Default=01h, 00h, 00h, 40h, 00h and 00h)

These registers are used to select the function as the Simple I/O function or the Alternate function.

Bit Description

7-0 1: Simple I/O function

0: Alternate function

8.11.15 Simple I/O Set 1, 2, 3, 4, 5 and 6 Output Enable Registers (Index=C8h, C9h, CAh, CBh, CCh and CDh, Default=01h, 00h, 00h, 40h, 00h and 00h)

These registers are used to determine the direction of the Simple I/O.

Bit Description

7-0 0: Input mode

1: Output mode

8.11.16 Panel Button De-bounce 0 Input Pin Mapping Registers (Index=E0h, Default=00h)

Bit Description

Reserved

IRQ Enable

5-0

Input pin Location

Please see Location mapping table

Note4

8.11.17 Panel Button De-bounce 1 Input Pin Mapping Registers (Index=E1h, Default=00h)

Bit Description

7-6 5-0

Reserved Input pin Location

Please see Location mapping table

Note4

8.11.18 IRQ External Routing 1-0 Input Pin Mapping Registers (Index=E3h-E2h, Default=00h)

Bit Description

Reserved

6 IRQ Enable

5-0

Input pin Location

Please see Location mapping table

Note4

8.11.19 IRQ External Routing 1-0 Interrupt Level Selection Register (Index=E4h, Default=00h)

Bit Description

7-4 Select the interrupt level Note1 for IRQ External Routing 1 3-0 Select the interrupt level Note1 for IRQ External Routing 0

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8.11.20 VID Watchdog timer 0 Value Register (Index=E5h, Default=00h)

Bit Description

7-0

VID Watchdog Timer 0 Value

Writing to this register will load a new counter. Reading it when VID Watchdog is disabled (bit2 of Index FFh = 0) will respond the setting value. Reading it when VID Watchdog is enabled (bit 2 of

Index FFh = 1) will respond the left counters to timeout.

8.11.21 VID Watchdog timer 1 Value Register (Index=E6h, Default=00h)

Bit Description

7-0

VID Watchdog Timer 1 Value

Writing to this register will load a new counter. Reading it when VID Watchdog is disabled (bit3 of Index FFh = 0) will respond the setting value. Reading it when VID Watchdog is enabled (bit3 of Index FFh = 1) will respond the left counters to timeout.

8.11.22 SMI# Control Register 1 (Index=F0h, Default=00h)

Bit Description

Reserved

Enables the generation of an SMI# due to KBC (Mouse)’s IRQ (EN_MIRQ).

Enables the generation of an SMI# due to KBC (Keyboard)’s IRQ (EN_KIRQ).

Enables the generation of an SMI# due to Environment Controller’s IRQ (EN_ECIRQ).

Enables the generation of an SMI# due to Parallel Port’s IRQ (EN_PIRQ).

Enables the generation of an SMI# due to Serial Port 2’s IRQ (EN_S2IRQ).

Enables the generation of an SMI# due to Serial Port 1’s IRQ (EN_S1IRQ).

Enables the generation of an SMI# due to FDC’s IRQ (EN_FIRQ).

8.11.23 SMI# Control Register 2 (Index=F1h, Default=00h)

Bit Description

Forces to clear all the SMI# status register bits, non-sticky.

6 0: Edge trigger

1: Level trigger

5-4

Reserved

Enables the generation of an SMI# due to WDT’s IRQ (EN_WDT)

Enables the generation of an SMI# due to CIR’s IRQ (EN_CIR)

Enables the generation of an SMI# due to PBD’s IRQ (EN_PBD)

Configuration

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8.11.24 SMI# Status Register 1 (Index=F2h, Default=00h)

This register is used to read the status of SMI# inputs.

Bit Description

Reserved

KBC (PS/2 Mouse)’s IRQ

KBC (Keyboard)’s IRQ

Environment Controller’s IRQ

Parallel Port’s IRQ

Serial Port 2’s IRQ

Serial Port 1’s IRQ

FDC’s IRQ

8.11.25 SMI# Status Register 2 (Index=F3h, Default=00h)

This register is used to read the status of SMI# inputs.

Bit Description

7-6

Panel Button De-bounce Status 1-0

Writing 1 will reset the status.

0: None detected.

1: Detected.

5-4

3 2 1 0

Reserved Reserved WDT’s IRQ CIR’s IRQ PBD’s IRQ

8.11.26 SMI# Pin Mapping Register (Index=F4h, Default=00h)

Bit Description

7-6 5-0

Reserved SMI# Pin Location

Please see Location mapping table

Note4

8.11.27 Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h)

Bit Description

7-6 5-0

Reserved Thermal Output Pin Location

Please see Location mapping table

Note4

8.11.28 Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h)

Bit Description

7-6 5-0

Reserved Alert Beep Pin Location

Please see Location mapping table

Note4

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8.11.29 Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h)

Bit Description

7-6 5-0

Reserved Keyboard Lock Pin Location

Please see Location mapping table

Note4

8.11.30 GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h)

Bit Description

7-6 5-0

Reserved GP LED Blinking 1 Location

Please see Location mapping table

Note4

8.11.31 GP LED Blinking 1 Control Register (Index=F9h, Default=00h)

Bit Description

7-4

2-1

Reserved

GP LED Blinking 1 short low pulse enabled GP LED 1 Frequency Control

00: 4 Hz 01: 1 Hz 10: 1/4 Hz 11: 1/8 Hz

GP LED Blinking 1 Output low enabled

8.11.32 GP LED Blinking 2 Pin Mappi ng Regist er (Index=FAh, Default=00h)

Bit Description

7-6 5-0

Reserved GP LED Blinking 2 Location

Please see Location mapping table

Note4

8.11.33 GP LED Blinking 2 Control Register (Index=FBh, Default=00h)

Bit Description

7-4

2-1

Reserved

GP LED Blinking 2 short low pulse enabled GP LED 2 Frequency Control

00: 4 Hz 01: 1 Hz 10: 1/4 Hz 11: 1/8 Hz

GP LED Blinking 2 Output low enabled

Configuration

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8.11.34 VID Input Register (Index=FCh, Default=--h)

Bit Description

7-0

VID 7-0 inputs

They are read-only. The threshold for VID inputs is not TTL level (0.4V for low, 2.2V for high), but special CMOS level (1.5V for low, 2.5V for hig

h) Writing “1” to bit 0 to update initial VID input.

8.11.35 VID Output/Programed Output Register (Index=FDh, Default=00h)

Bit Description

7-0

VID 7-0 output or Programmed output values

If DYNAMIC_en is low, this register is VID Output value for software mode. If the bit is high, this register is the Programmed output values. In the dynamic VID mode, the programmed output value is 2’s complement. For example, when the 6-bit table is selected, only bits 5-0 are valid.

000011b means 3 steps higher than inputs, and 111011b means 5 steps lower than inputs.

8.11.36 VID Watchdog timer Control Register (Index=FEh, Default=00h)

Bit Description

7-6

VID_READING_SEL. VID 7-0 Readings selection.

00: Bits 7-0 is the initial value of VID inputs. 01: Bits 7-0 is the current value of VID inputs. 10: Bits 7-0 is the current value of VID outputs. 11: Reserved.

5-4 3-2

Reserved Dynamic table selection

00: VRM9 01: VRM10 (6-bit VID)

10: VRM11 (7-bit VID) 11: VRM11 (8-bit VID)

DYNAMIC_en. VID output selection

1: Dynamic VID output

The value of VIDOUT output pins is generated from the input signals VIDIN and VID 7-0 output

values (bit7-0). If VID input and output is the same pin, this bit cannot be enabled. 0: Software

The value of VIDOUT output pins is directly VID 7-0 output values (bit7-0).

VID_OE. VID output enable

1: output 0: input

8.11.37 VID Watchdog timer Control Register (Index=FFh, Default=00h)

Bit Description

7-6

Reserved

VID Watchdog 1 Time-unit

1: VID watchdog 1 time-unit is 62.5ms(1/16) 0: VID watchdog 1 time-unit is about 1ms(1/1024)

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VID Watchdog 0 Time-unit

Configuration

1: VID watchdog 0 time-unit is 62.5ms(1/16) 0: VID watchdog 0 time-unit is about 1ms(1/1024)

VID Watchdog 1 Enable

1: Enable VID watchdog timer 1 0: Disable VID watchdog timer 1

VID Watchdog 0 Enable

1: Enable VID watchdog timer 0 0: Disable VID watchdog timer 0

VID Watchdog 1 Time-out

1: VID watchdog 1 timeout occurs. Writing 1 to it will clear itself. 0: No VID watchdog 1 timeout event

VID Watchdog 0 Time-out

1: VID watchdog 0 timeout occurs. Writing 1 to it will clear itself. 0: No VID watchdog 0 timeout event.

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8.12 Consumer IR Configuration Registers (LDN=0Ah)

8.12.1 Consumer IR Activ ate (Index=30h, Default=00h)

Bit Description

7-1

Reserved

Consumer IR Enable

1: Enable 0: Disable

8.12.2 Consumer IR Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4 3-0

Read only with “0h” for Base Address[15:12] Read/write, mapped as Base Address[11:8]

8.12.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h)

Bit Description

7-3 2-0

Read/write, mapped as Base Address[7:3] Read only as “000b”

8.12.4 Consumer IR Interrupt Lev el Select (Index=70h, Default=0Bh)

Bit Description

7-4

Reserved with default “0h”

3-0 Select the interrupt level Note1 for Consumer IR

8.12.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h)

Bit Description

7-1

Reserved with default “00h”

0 1: IRQ sharing

0: Normal

Note 1:

Interrupt level mapping Fh-Dh: not valid Ch: IRQ12 3h: IRQ3 2h: not valid 1h: IRQ1 0h: no interrupt selected

Note 2:

DMA channel mapping 7h-5h: not valid 4h: no DMA channel selected 3h: DMA3 2h: DMA2 1h: DMA1 0h: DMA0

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Note 3:

Except the standard mode, COM1 and COM2 cannot be selected in the same mode.

Note 4: The Location mapping table

Location Description

001 000 GP10 (pin 84). Powered by VCCH. 001 001 GP11 (pin 34). 001 010 GP12 (pin 33). 001 011 GP13 (pin 32). 001 100 GP14 (pin 31). 001 110 GP16 (pin 29). 001 111 GP17 (pin 28). 010 000 GP20 (pin 27). Powered by VCCH. 010 001 GP21 (pin 26). Powered by VCCH. 010 010 GP22 (pin 25). Powered by VCCH. 010 011 GP23 (pin 24). Powered by VCCH. 010 100 GP24 (pin 23). Powered by VCCH. 010 101 GP25 (pin 22). Powered by VCCH. 010 110 GP26 (pin 21). Powered by VCCH. 010 111 GP27 (pin 20). Powered by VCCH. 011 000 GP30 (pin 19). 011 001 GP31 (pin 18). 011 010 GP32 (pin 17). 011 011 GP33 (pin 16). 011 100 GP34 (pin 14). 011 101 GP35 (pin 13). 011 110 GP36 (pin 12). 011 111 GP37 (pin 11). 100 000 GP40 (pin 79). Powered by VCCH. 100 001 GP41 (pin 78). Powered by VCCH. 100 010 GP42 (pin 76). Powered by VCCH. 100 011 GP43 (pin 75). Powered by VCCH. 100 100 GP44 (pin 72). Powered by VCCH. 100 110 GP46 (pin 70). Powered by VCCH. 100 111 GP47 (pin 66). 101 000 GP50 (pin 48). 101 001 GP51 (pin 10). 101 010 GP52 (pin 9). 101 011 GP53 (pin 77). Powered by VCCH. 101 100 GP54 (pin 73). Powered by VCCH. 101 101 GP55 (pin 85). Powered by VCCH. 101 110 GP56 (pin 83). Powered by VCCH. 101 111 GP57 (pin 82). Powered by VCCH. 110 000 GP60 (pin 81). Powered by VCCH. 110 001 GP61 (pin 80). Powered by VCCH. 110 010 GP62 (pin 45). 110 011 GP63 (pin 6). 110 100 GP64 (pin 3). 110 101 GP65 (pin 128). 110 110 GP66 (pin 127). 110 111 GP67 (pin 126).

Else

Reserved

Configuration

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Functional Description

9. Functional Description

9.1 LPC Interface

The IT8718F supports the peripheral site of the LPC I/F as described in the LPC Interface Specification Rev.1.0 (Sept. 29, 1997). In addition to the required signals (LAD3-0, LFRAME#, LRESET#, LCLK (LCLK is the same as PCICLK.)), the IT8718F also supports LDRQ#, SERIRQ and PME#.

9.1.1 LPC Transactions

The IT8718F supports some parts of the cycle types described in the LPC I/F specification. Memory read and Memory write cycles are used for the Flash I/F. I/O read and I/O write cycles are used for the programmed I/O cycles. DMA read and DMA write cycles are used for DMA cycles. All of these cycles are characteristic of the single byte transfer.

For LPC host I/O read or write transactions, the Super I/O module processes a positive decoding, and the LPC interface can respond to the result of the current transaction by sending out SYNC values on LAD[3:0] signals or leave LAD[3:0] tri-state depending on its result.

For DMA read or write transactions, the LPC interface will make reactions according to the DMA requests from the DMA devices in the Super I/O modules, and decide whether to ignore the current transaction or not.

The FDC and ECP are 8-bit DMA devices, so if the LPC Host initializes a DMA transaction with data size of 16/32 bits, the LPC interface will process the first 8-bit data and response with an SYNC ready (0000b) which will terminate the DMA burst. The LPC interface will then re-issue another LDRQ# message to assert DREQn after finishing the current DMA transaction.

9.1.2 LDRQ# Encoding

The Super I/O module provides two DMA devices: the FDC and the ECP. The LPC Interface provides LDRQ# encoding to reflect the DREQ[3:0] status. Two LDRQ# messages or different DMA channels may be issued back-to-back to trace DMA requests quickly. But, four PCI clocks will be inserted between two LDRQ# messages of the same DMA channel to guarantee that there are at least 10 PCI clocks for one DMA request to change its status. (The LPC host will decode these LDRQ# messages, and send those decoded DREQn to the legacy DMA controller which runs at 4 MHz or 33/8 MHz).

9.2 Serialized IRQ

The IT8718F follows the specification of Serialized IRQ Support for PCI System, Rev. 6.0, September 1, 1995, to support the serialized IRQ feature, and is able to interface most PC chipsets. The IT8718F encodes the parallel interrupts to an SERIRQ which will be decoded by the chipset with built-in Interrupt Controllers (two 8259 compatible modules).

9.2.1 Continuous Mode

When in the Continuous mode, the SIRQ host initiates the Start frame of each SERIRQ sequence after sending out the Stop frame by itself. (The next Start frame may or may not begin immediately after the turnaround state of the current Stop frame.) The SERIRQ is always activated and SIRQ host keeps polling all the IRQn and system events, even though no IRQn status is changed. The SERIRQ enters the Continuous mode following a system reset.

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9.2.2 Quiet Mode

In the Quiet mode, when the situation that one SIRQ Slave detects its input IRQn/events have been changed, it may initiate the first clock of Start frame. The SIRQ host can then follow to complete the SERIRQ sequence. In the Quiet mode, the SERIRQ has no activity following the Stop frame until it is initiated by SIRQ Slave, which implies low activity = low mode power consumption.

9.2.3 Waveform Samples of SERIRQ Sequence

PCICLK

SERIRQ

PCICLK

SERIRQ

Start Frame

S/H H

(4/6/8)T

S: Slave drive H: Host drive R: Recovery T: Turn-around S/H: Slave drive when in Quiet mode, Host drive when in Continuous mode

IRQ0 Frame

T SRT SRT SRTS RT

IRQ1 Frame SMI# Frame IRQ3 Frame

IRQ4 Frame

SRT

Figure 9-1. Start Frame Timing

Last Frame Start Frame

Stop Frame

0~n Tclk idle state

S: Slave drive H: Host drive R: Recovery T: Turn-around I: Idle W: Waiting

(Quiet)

RTWS H SRT H RTH1SRT HI

2 Tclk

Last Frame Stop Frame

0~n T, depends on master

(Continuous)

3 Tclk

Figure 9-2. Stop Frame Timing

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9.2.4 SERIRQ Sampling Slot

Slot

Number

IRQn/

Events

#of Clocks

Past Start

1 IRQ0 2 -

2 IRQ1 5 Y

3 SMI# 8 Y

4 IRQ3 11 Y

5 IRQ4 14 Y

6 IRQ5 17 Y

7 IRQ6 20 Y

8 IRQ7 23 Y

9 IRQ8 26 Y

10 IRQ9 29 Y

11 IRQ10 32 Y

12 IRQ11 35 Y

13 IRQ12 38 Y

14 IRQ13 41 -

15 IRQ14 44 Y

16 IRQ15 47 Y

17 IOCHCK# 50 -

18 INTA# 53 -

19 INTB# 56 -

20 INTC# 59 -

21 INTD# 62 -

32:22 Unassigned 95 / 65 -

Functional Description

IT8718F

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9.3 General Purpose I/O

The IT8718F provides five sets of flexible I/O control and special functions for the system designers via a set of multi-functional General Purpose I/O pins (GPIO). The GPIO functions will not be performed unless the related enable bits of the GPIO Multi-function Pin Selection registers (Index 25h, 26h, 27h, 28h and 29h of the Global Configuration Registers) are set. The GPIO functions include the simple I/O function and alternate function, and the function selection is determined by the Simple I/O Enable Registers (LDN=07h, Index=C0h, C1h, C2h, C3h and C4h).

The Simple I/O function includes a set of registers, which correspond to the GPIO pins. All control bits are divided into five registers. The accessed I/O ports are programmable and are five consecutive I/O ports (Base Address+0, Base Address+1, Base Address+2, Base Address+3, Base Address+4). Base Address is programmed on the registers of GPIO Simple I/O Base Address LSB and MSB registers (LDN=07h, Index=60h and 61h).

The Alternate Function provides several special functions for users, including Watch Dog Timer, SMI# output routing, External Interrupt routing, Panel Button De-bounce, Keyboard Lock input routing, LED Blinking, Thermal output routing, and Beep output routing. The last two are the sub-functions of Hardware Monitor.

The Panel Button De-bounce is an input function. After the panel button de-bounce is enabled, a related status bit will be set when an active low pulse is detected on the GPIO pin. The status bits will be cleared by writing 1’s to them. Panel Button De-bounce Interrupt will be issued if any one of the status bit is set. However, the new setting status will not issue another interrupt unless the previous status bit is cleared before being set.

The Key Lock function locks the keyboard to inhibit the keyboard interface. The programming method is to set bit 2 on the register Index F0h of KBC (keyboard) (LDN=5). The pin location mapping, Index F7h must also be programmed correctly.

The Blinking function provides a low frequency blink output. By connecting to some external components, it can be used to control a power LED. There are several frequencies that can be selected.

The Watch Dog Timer (WDT) function is constituted by a time counter, a time-out status register, and the timer reset control logic. The time-out status bit may be mapped to an interrupt or KRST# through the WDT Configuration register. The WDT has a programmable time-out range from 1 to 65535 minutes or 1 to 65535 seconds. The units are also programmable, either a minute or a second, via bit7 of the WDT Configuration register. When the WDT Time-out Value register is set to a non-zero value, the WDT loads the value and begin counting down from the value. When the value reaches to 0, the WDT status register will be set. There are many system events that can reload the non-zero value into the WDT. They include a CIR interrupt, a Keyboard Interrupt, a Mouse Interrupt. The effect on the WDT for each of the events may be enabled or disabled through bits in the WDT control register. No matter what value in the time counter is, the host may force a time-out to occur by writing a “1” to the bit 1 of the WDT Configuration register.

The External Interrupt routing function provides a useful feature for motherboard designers. Through this function, the parallel interrupts of other on-board devices can be easily re-routed into the Serial IRQ.

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Functional Description

The SMI# is a non-maskable interrupt dedicated to the transparent power management. It consists of different enabled interrupts generated from each of the functional blocks in the IT8718F. The interrupts are redirected as the SMI# output via the SMI# Control Register 1 and SMI# Control Register 2. The SMI# Status Registers 1 and 2 are used to read the status of the SMI input events. All the SMI# Status Register bits can be cleared when the corresponding source events become invalidated. These bits can also be cleared by writing 1 to bit 7 of SMI# Control Register 2, whether the events of the corresponding sources are invalidated or not. The SMI# events can be programmed as the pulse mode or level mode whenever an SMI# event occurs. The logic equation of the SMI# event is described below:

SMI# event = (EN_FIRQ and FIRQ) or (EN_S1IRQ and S1IRQ) or (EN_S2IRQ and S2IRQ) or (EN_PIRQ and PIRQ) or (EN_EC and EC_SMI) or (EN_PBDIRQ or PBDIRQ) or (EN_KIRQ and KIRQ) or (EN_MIRQ and MIRQ) or (EN_CIR and CIR_IRQ) or (EN_WDT and WDT_IRQ) or (EN_STPCLK and STPCLK_IRQ)

Thermal Output

LED Blinking 1

LED Blinking 2

Beep#

SMI#

Simple I/O Register Bit-n

2 3

Simple I/O

enable

Polarity

Pull-up enable

SD-bus

WR#

D-

TYPE

Output

enable

GPIO

RD_

Interrupt

SD-bus

RD_(IDX=64h, 65h)

status

Panel Button De-bounce Bit-n

De-bounce

enable

De-bounce circuit

External IRQ Routing

(Level 3 - 7, 9 - 11, 14-15)

Keyboard lock

Figure 9-3. General Logic of GPIO Function

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9.4 Advanced Power Supply Control and Power Management Event (PME#)

The circuit for advanced power supply control (APC) provides three power-up events, Keyboard, Mouse and CIR. When any of these three events is true, PWRON# will perform a low state until VCC is switched to the ON state. The three events include the followings:

1. Detection of KCLK edge or special pattern of KCLK and KDAT. The special pattern of KCLK means

pressing pre-set key string sequentially, and KDAT means pressing pre-set keys simultaneously.

2. Detection of MCLK edge or special pattern of MCLK and MDAT. The special pattern of MCLK and MDAT

means clicking on any mouse button twice sequentially.

3. Receiving CIR patterns are matched the previous stored pattern stored at the APC/PME Special Code

Index and Data Register.

The PANSWH# and PSON# are especially designed for the system. PANSWH# serves as a main power switch input, which is wire-AND to the APC output PWRON#. PSON# is the ATX Power control output, which is a power-failure gating circuit. The power-failure gating circuit is responsible for gating the PSIN input until PANSWH# becomes active when the VCCH is switched from OFF to ON.

The power-failure gating circuit can be disabled by setting the APC/PME Control Register 2 (LDN=04h, index F4h, bit 5). The gating circuit also provides an auto-restore function. When the bit 5 of PCR1 is set, the previous PSON# state will be restored when the VCCH is switched from OFF to ON.

The Mask PWRON# Activation bit (bit 4 of PCR 1) is used to mask all Power-up events except Switch on event when the VCCH state is just switched from FAIL to OFF. In other words, when this bit is set and the power state is switched from FAIL to OFF, the only validated function is PANSWH#.

The PCR2 register is responsible for determining the Keyboard power up events and APC conditions. Bit 4 is used to mask the PANSWH# power-on event on the PWRON# pin. To enable this bit, the keyboard power-up event should be enabled and set by (1) pressing pre-set key string sequentially or (2) stroking pre-set keys simultaneously. The APC/PME# special code index and data registers are used to specify the special key codes in the special power-up events of (1) pressing pre-set key string sequentially or (2) stroking pre-set keys simultaneously.

A CIR event is generated if the input CIR RX pattern is the same as the previously stored pattern stored at PME Special Code Index and Data Registers (LDN=04h, Index=F5h and F6h). The total maximum physical codes are nineteen bytes (from Index 20h to 32h). The first byte (Index 20h) is used to specify the pattern length (in bytes). Bits[7:4] are used when VCC is on; and Bits[3:0] when VCC goes OFF. The length represented in each 4 bits will be incremented by 3 internally as the actual length to be compared. For most of the CIR protocols, the first several bytes are always the same for each key (or pattern). The differences are always placed in the last several bytes. Thus, the system designer can program the IT8718F to generate a CIR PME# event as any keys when VCC is ON and a special key (i.e. POWER-ON) when VCC is OFF.

All APC registers (Index=F0h, F2h, F4h, F5h and F6h) are powered by back-up power (VBAT) when VCCH is OFF. PME# is used to wake up the system from low-power states (S1-S5). Except the five events of the APC’s, there will be other events to generate PME#: They are RI1# and RI2# events. RI1# and RI2# are Ring Indicator of Modem status at ACPI S1 or S2 state. A falling edge on these pins issues PME# events if the enable bits are set.

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Functional Description

9.5 SPI Serial Flash Controller

9.5.1 Overview

The SPI Serial Flash Controller is an LPC to the serial Flash I/F controller.

9.5.2 Features

 SPI Interface  LPC memory cycle and firmware memory cycle supported

9.5.3 Register Descriptions

Table 9-1. Memory Stick Register List

Address R/W Default Name

Base + 0h R/W 20h Control Register (SPI_CTRL)

Base + 1h R/W 00h Command Register (SPI_CMD)

Base + 2h R/W 00h Address 0 Register (SPI_ADDR0)

Base + 3h R/W 00h Address 1 Register (SPI_ADDR1) Base + 4h R/W 00h Address 2 Register (SPI_ADDR2) Base + 5h R -- Input Data 0 Register (SPI_IDATA0) Base + 6h R -- Input Data 1 Register (SPI_IDATA1)

Base + 7h R/W-R 00h/--

Output Data Register (SPI_ODATA)/ Input Data 2 Register

(SPI_IDATA2)

9.5.3.1 Control Register (SPI_CTRL) Address: Base address + 0h

Bit R/W Default Description

7 R -

SPI Status

Report SPI I/F status 0: SPI I/F is idle 1: SPI I/F is busy

6 R/W 0b

Start IO Transfer

Start SPI cycle with the instruction/parameter given through I/O port. 0: No Start IO 1: Enable Start IO/going

5 R/W 1b

Multiple Byte mode

Enable Multiple Byte mode in LPC memory write/read cycle. 0: Disable 1: Enable

4 R/W 0b

SCK Selection

Select SCK Frequency. 0: 33MHz/2. 1: 33MHz.

3-2 R/W 00b

Input Data Byte

Determine input data byte number in the Start IO mode. 00: None. 01: 1 byte. (SPI_DATAI0) 10: 2 bytes. (SPI_DATAI0, SPI_DATAI1).

11: 3 bytes. (SPI_DATAI0, SPI_DATAI1, SPI_DATAI2).

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Bit R/W Default Description

1-0 R/W 00b

Output Data Byte

Determine the output data byte number (including Instruction, Address, Data) in the Start IO mode. 00: 1 byte. (SPI_CMD) 01: 2 bytes. (SPI_CMD, SPI_DATAO) 10: 4 bytes. (SPI_CMD, ADDR2, ADDR1, ADDR0)

11: 5 bytes. (SPI_CMD, ADDR2, ADDR1, ADDR0, SPI_DATAO)

9.5.3.2 Command Register (SPI_CMD) Address: Base address + 1h

Bit R/W Default Description

7 – 0 R/W 00h

Command Register (SPI_CMD [7:0])

This register will set the Instruction command code in the Start IO mode. (The first byte)

9.5.3.3 Address 0 Register (SPI_ADDR0) Address: Base address + 2h

Bit R/W Default Description

7 – 0 R/W 00h

Address 0 Register (SPI_ADDR0 [7:0])

This register will set the Address [7:0] in the Start IO mode.

9.5.3.4 Address 1 Register (SPI_ADDR1) Address: Base address + 3h

Bit R/W Default Description

7 – 0 R/W 00h

Address 1 Register (SPI_ADDR1 [7:0])

This register will set the Address [15:8] in the Start IO mode.

9.5.3.5 Address 2 Register (SPI_ADDR2) Address: Base address + 4h

Bit R/W Default Description

7 – 0 R/W 00h

Address 2 Register (SPI_ADDR2 [7:0])

This register will set the Address [23:16] in the Start IO mode.

9.5.3.6 Input Data 0 Register (SPI_IDATA0) Address: Base address + 5h

Bit R/W Default Description

7 – 0 R --

Input Data 0 Register (SPI_IDATA0 [7:0])

This register will set the Input Data 0 byte in the Start IO mode.

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Functional Description

9.5.3.7 Input Data 1 Register (SPI_IDATA1) Address: Base address + 6h

Bit R/W Default Description

7 – 0 R --

Input Data 1 Register (SPI_IDATA1 [7:0])

This register will set the Input Data 1 byte in the Start IO mode.

9.5.3.8 Output Data/Input Data 2 Register (SPI_ODATA/ SPI_IDATA2) Address: Base address + 7h

Bit R/W Default Description

7 – 0 R/W 00h

Output Data Register (SPI_ODATA [7:0])/ Input Data 2 Register (SPI_IDATA1 [7:0])

This register will set the Output Data byte in the Start IO mode, or Input Data 2 when the input data byte number is 3.

9.5.4 Function Descriptions

Programming sequence: All the instruction code and byte numbers should refer to the Serial Flash product specification.

Start IO mode:

// 1: Check SPI I/F IOR [SPI_CTRL]; // check bit7 SPI status

// 2: Set the parameters. Don’t care the write sequence. IOW [SPI_CMD] XXh: // Set SPI Instruction IOW [SPI_ADDR0] XXh: // Set SPI Address0, if necessary IOW [SPI_ADDR1] XXh: // Set SPI Address1, if necessary IOW [SPI_ADDR2] XXh: // Set SPI Address2, if necessary IOW [SPI_ODATA] XXh: // Set SPI Output Data, if necessary

// 3: Start SPI I/F IOW [SPI_CTRL] {4’h1, Input_data_byte, Output_data_byte};

LPC memory cycle:

When the host issues LPC memory read cycle with the matching memory space, the controller will issue SPI read cycle automatically. The controller will pre-read 0-3 byte(s) data in buffers. The pre-read data byte number is determined by the starting address 0 and 1. The number will be 3 bytes if the two addresses are 00b. The number will be 2 bytes if the two addresses are 01b. The number will be 1 byte if the two addresses are 10b. There is no pre-read data if the two addresses are 11b.If the address of the next coming LPC memory cycles matches the buffers’ address; no SPI read cycle would be issued. For most of the serial flash product, Write-Enable instruction through the Start IO mode should be given before issuing LPC memory writes cycle. Normally, each LPC memory cycle will issue one byte SPI programming cycle (Instruction, Addresses, 1 byte Data). If the Multiple Byte mode is enabled, multi-byte SPI programming cycle will be issued. For example:

// LPC Memory Write Multiple byte mode // 1: Write-Enable command IOR [SPI_CTRL]; // check bit7 SPI status IOW [SPI_CMD] 06h: // Set SPI Instruction IOW [SPI_CTRL] {4’h3, 2’b00, 2’b00};

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// Start IO SPI cycle and enable the LPC memory Multiple Byte mode

// 2: LPC memory write cycles: The first LPC memory cycle will start the SPI cycle and determine the // Programming page address. The following LPC memory write cycles should be continue addresses. // And, the total bytes cannot be more than 256 – [starting address 7-0]. These conditions should be // confirmed by the programmer. The controller will not check them. During this period, the SPI cycle // will not be finished. Between the two MEMW cycles, HOLD# pin will assert and SCK will be forced in low. MEMW [Starting address]: // Set SPI Address and the first byte data. MEMW [Starting address+1]: // Set SPI second byte data. MEMW [Starting address+2]: // Set SPI third byte data. : MEMW [Starting address+N]: // Set SPI Nth byte data.

// 3: Terminate SPI I/F IOW [SPI_CTRL] {4’h0, 2’b00, 2’b00};

// Terminate LPC memory write Page Program mode and SPI cycle

// LPC Memory Read Multiple byte mode // 1: Write-Enable command IOW [SPI_CTRL] {4’h2, 2’b00, 2’b00};

// Enable LPC memory Multiple Byte mode

// 2: LPC memory read cycles: The first LPC memory cycle will start the SPI cycle and determine the // reading address. The following LPC memory read cycles should be the continue addresses. // And, the total bytes will not be limited. The programmer should confirm these conditions. // The controller will not check them. During this period, the SPI cycle will not be finished. Between the two // MEMR cycles, HOLD# pin will assert and SCK will be forced in low. MEMR [Starting address]: // Set SPI Address and the first byte data. MEMR [Starting address+1]: // Set SPI second byte data. MEMR [Starting address+2]: // Set SPI third byte data. : MEMR [Starting address+N]: // Set SPI Nth byte data.

// 3: Terminate SPI I/F IOW [SPI_CTRL] {4’h0, 2’b00, 2’b00};

// Terminate LPC memory Read Multiple Byte mode and SPI cycle

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Functional Description

9.6 Environment Controller

The Environment Controller (EC), built in the IT8718F, includes eight voltage inputs, three temperature sensor inputs, five FAN Tachometer inputs, and three sets of advanced FAN Controllers. The EC monitors the hardware environment and implements the environmental control for personal computers.

The IT8718F contains an 8-bit ADC (Analog-to-Digital Converter), which is responsible for monitoring the voltages and temperatures. The ADC converts the analog inputs ranging from 0V to 4.096V into 8-bit digital bytes. Thanks to the additional external components, the analog inputs are able to monitor different voltage ranges, in addition to monitoring the fixed input range of 0V to 4.096V. Through the external thermistors, the temperature sensor inputs can be converted into 8-bit digital bytes, enabling the sensor inputs, and monitoring the temperature around the thermistors or thermal diode. A built-in ROM is also provided to adjust the non-linear characteristics of thermistors.

FAN Tachometer inputs are digital inputs with an acceptable input range of 0V to 5V, and are responsible for measuring the FAN’s Tachometer pulse periods.

The EC of the IT8718F provides multiple internal registers and an interrupt generator for programmers to monitor the environment and control the FANs. Both the LPC Bus and Serial Bus interfaces are supported to accommodate the needs for various applications.

9.6.1 Interfaces LPC Bus: The Environment Controller of the IT8718F decodes two addresses.

Table 9-2. Address Map on the LPC Bus

Registers or Ports Address

Address register of the EC Base+05h

Data register of the EC Base+06h

Note 1: The Base Address is determined by the Logical Device configuration registers of the Environment

Controller (LDN=04h, registers index=60h, 61h).

To access an EC register, the address of the register is written to the address port (Base+05h). Read or write data from or to that register via data port (Base+06h).

9.6.2 Registers

9.6.2.1 Address Port (Base+05h, Default=00h)

Bit Description

Outstanding; Read only

This bit is set when a data write is performed to Address Port via the LPC Bus.

6-0 Index: Internal Address of RAM and Registers.

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Table 9-3. Environment Controller Registers

Index R/W Default Registers or Action

00h R/W 18h Configuration

01h R 00h Interrupt Status 1

02h R 00h Interrupt Status 2

03h R 00h Interrupt Status 3

04h R/W 00h SMI# Mask 1

05h R/W 00h SMI# Mask 2

06h R/W 00h SMI# Mask 3

07h R/W 00h Interrupt Mask 1

08h R/W 00h Interrupt Mask 2

09h R/W 80h Interrupt Mask 3

0Ah R/W 40h Interface Selection Register

0Bh R/W 09h Fan PWM Smoothing Step Frequency Selection Register

0Ch R/W 00h Fan Tachometer 16-bit Counter Enable Register

0Dh R - Fan Tachometer 1 Reading Register

0Eh R - Fan Tachometer 2 Reading Register

0Fh R - Fan Tachometer 3 Reading Register

10h R/W - Fan Tachometer 1 Limit Register

11h R/W - Fan Tachometer 2 Limit Register

12h R/W - Fan Tachometer 3 Limit Register

13h R/W 07h Fan Controller Main Control Register

14h R/W 50h FAN_CTL Control Register

15h R/W 00h/20h40h/60h FAN_CTL1 PWM Control Register

16h R/W 00h/20h/40h/60h FAN_CTL2 PWM Control Register

17h R/W 00h/20h/40h/60h FAN_CTL3 PWM Control Register

18h R - Fan Tachometer 1 Extended Reading Register

19h R - Fan Tachometer 2 Extended Reading Register

1Ah R - Fan Tachometer 3 Extended Reading Register

1Bh R/W - Fan Tachometer 1 Extended Limit Register

1Ch R/W - Fan Tachometer 2 Extended Limit Register

1Dh R/W - Fan Tachometer 3 Extended Limit Register

20h R - VIN0 Voltage Reading Register

21h R - VIN1 Voltage Reading Register

22h R - VIN2 Voltage Reading Register

23h R - VIN3 Voltage Reading Register

24h R - VIN4 Voltage Reading Register

25h R - VIN5 Voltage Reading Register

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Functional Description

Index R/W Default Registers or Action

26h R - VIN6 Voltage Reading Register

27h R - VIN7 Voltage Reading Register

28h R - VBAT Voltage Reading Register

29h R - TMPIN1 Temperature Reading Register

2Ah R - TMPIN2 Temperature Reading Register

2Bh R - TMPIN3 Temperature Reading Register

30h R/W - VIN0 High Limit Register

31h R/W - VIN0 Low Limit Register

32h R/W - VIN1 High Limit Register

33h R/W - VIN1 Low Limit Register

34h R/W - VIN2 High Limit Register

35h R/W - VIN2 Low Limit Register

36h R/W - VIN3 High Limit Register

37h R/W - VIN3 Low Limit Register

38h R/W - VIN4 High Limit Register

39h R/W - VIN4 Low Limit Register

3Ah R/W - VIN5 High Limit Register

3Bh R/W - VIN5 Low Limit Register

3Ch R/W - VIN6 High Limit Register

3Dh R/W - VIN6 Low Limit Register

3Eh R/W - VIN7 High Limit Register

3Fh R/W - VIN7 Low Limit Register

40h R/W - TMPIN1 High Limit Register

41h R/W - TMPIN1 Low Limit Register

42h R/W - TMPIN2 High Limit Register

43h R/W - TMPIN2 Low Limit Register

44h R/W - TMPIN3 High Limit Register

45h R/W - TMPIN3 Low Limit Register

50h R/W 00h ADC Voltage Channel Enable Register

51h R/W 00h ADC Temperature Channel Enable Register

52h R/W 7Fh TMPIN1 Thermal Output Limit Register

53h R/W 7Fh TMPIN2 Thermal Output Limit Register

54h R/W 7Fh TMPIN3 Thermal Output Limit Register

55h R/W 00h ADC Temperature Extra Channel Enable Register

56h R/W 00h Thermal Diode 1 Zero Degree Adjust Register

57h R/W 00h Thermal Diode 2 Zero Degree Adjust Register

58h R 90h ITE Vendor ID Register

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Index R/W Default Registers or Action

59h R/W 00h Thermal Diode 3 Zero Degree Adjust Register

5Bh R 12h Core ID Register

5Ch R/W 00h Beep Event Enable Register

5Dh R/W 00h Beep Frequency Divisor of Fan Event Register

5Eh R/W 00h Beep Frequency Divisor of Voltage Event Register

5Fh R/W 00h Beep Frequency Divisor of Temperature Event Register

60h R/W 7Fh

61h R/W 7Fh

FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of OFF Register

FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers

62h R/W 7Fh Reserved Registers

63h R/W 00h FAN_CTL1 SmartGuardian Automatic Mode Start PWM Registers

64h R/W 00h FAN_CTL1 SmartGuardian Automatic Mode Control Registers

65h R/W 7Fh

FAN_CTL1 SmartGuardian Automatic Mode △-Temperature Registers

68h R/W 7Fh

69h R/W 7Fh

FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of OFF Register

FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers

6Ah R/W 7Fh Reserved Registers

6Bh R/W 00h FAN_CTL2 SmartGuardian Automatic Mode Start PWM Registers

6Ch R/W 00h FAN_CTL2 SmartGuardian Automatic Mode Control Registers

6Dh R/W 7Fh

70h R/W 7Fh

71h R/W 7Fh

FAN_CTL2 SmartGuardian Automatic Mode △-Temperature Registers

FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of OFF Register

FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers

72h R/W 7Fh Reserved Registers

73h R/W 00h FAN_CTL3 SmartGuardian Automatic Mode Start PWM Registers

74h R/W 00h FAN_CTL3 SmartGuardian Automatic Mode Control Registers

75h R/W 7Fh

FAN_CTL3 SmartGuardian Automatic Mode △-Temperature Registers

80h R - Fan Tachometer 4 Reading LSB Register

81h R - Fan Tachometer 4 Reading MSB Register

82h R/W - Fan Tachometer 4 Limit LSB Register

83h R/W - Fan Tachometer 4 Limit MSB Register

88h R/W -0h External Temperature Sensor Host Status Register

89h R/W 00h External Temperature Sensor Host Target Address Register

8Ah R/W 00h External Temperature Sensor Host Write Length Register

8Bh R/W 00h External Temperature Sensor Host Read Length Register

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ITE IT8718F Specification

Specifications and Main Features

Frequently Asked Questions

User Manual