ITE IT8510E, IT8510G, IT8510TE Schematics
IT8510E/TE/G
Embedded Controller
Preliminary Specification 0.7.2
ITE TECH. INC.
Specification subject to Change without notice, AS IS a nd for reference only. For purchasing, please contact sales
representatives.
Copyright © 2005 ITE Tech. Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related products
included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITE’s Standard
Terms and Conditions, a copy of which is included in the back of this document.
ITE, IT8510E/TE/G is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE Tech. Inc. Phone: (02) 2912-6889
Marketing Department Fax: (02) 2910-2551, 2910-2552
8F, No. 233-1, Bao Chiao RD., Hsin Tien,
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If you have any marketing or sales questions, please contact:
P.Y. Chang, at ITE Taiwan: E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052,
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Revision Histor
Revision History
Section Revision Page No.
6
In section 6.2.2.4, the value of Chip Version (CHIPVER) was changed. 48
6 In section 6.3.4.1 FBIU Configuration Register (FBCFG), OVRSHBM
and OVRBADDR fields were added.
6 In section 6.3.4.2 Flash Programming Configuration Register (FPCFG),
HSPD field was added.
7 In section 7.4.3.5 Keyboard Scan In Control Register (KSICTRLR),
OVRPPEN field was added.
7 In section 7.5.3.1 General Control Register (GCR), GFLE field was
added.
7 In section 7.11.4.5 Prescaler Clock Frequency Select Register
(PCFSR), its table was revised.
7
4, 11
12
In section 7.14.4.10, Chip Version (ECHIPVER) was added 247
TFBGA package information was added. 263
In section 12 Ordering Information, lead-free information was added. 267
76
77
174
176
222
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CONTENTS
1. Features ....................................................................................................................................................... 1
2. General Description ....................................................................................................................................... 3
3. System Block Diagram................................................................................................................................... 5
3.1 Block Diagram..................................................................................................................................... 5
3.2 Host/EC Mapped Memory Space ....................................................................................................... 6
3.3 EC Mapped Memory Space................................................................................................................ 9
3.4 Register Abbreviation........................................................................................................................ 10
4. Pin Configuration ......................................................................................................................................... 11
5. Pin Descriptions ........................................................................................................................................... 17
5.1 Pin Descriptions ................................................................................................................................ 17
5.2 Chip Power Planes and Power States..............................................................................................23
5.3 Pin Power Planes and States ........................................................................................................... 24
5.4 PWRFAIL# Interrupt to INTC ........................................................................................................... 28
5.5 Reset Sources and Types................................................................................................................. 29
5.5.1 Relative Interrupts to INTC................................................................................................... 29
5.6 Chip Power Mode and Clock Domain............................................................................................... 30
5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function ................................................................... 34
5.8 Power Consumption Consideration .................................................................................................. 36
6. Host Domain Functions................................................................................................................................ 39
6.1 Low Pin Count Interface.................................................................................................................... 39
6.1.1 Overview............................................................................................................................... 39
6.1.2 Features ............................................................................................................................... 39
6.1.3 Accepted LPC Cycle Type ................................................................................................... 39
6.1.4 Debug Port Function ............................................................................................................ 40
6.1.5 Serialized IRQ (SERIRQ) ..................................................................................................... 40
6.1.6 Relative Interrupts to INTC/WUC ......................................................................................... 41
6.1.7 LPCPD# and CLKRUN#....................................................................................................... 42
6.1.8 Check Items.......................................................................................................................... 43
6.2 Plug and Play Configuration (PNPCFG)........................................................................................... 44
6.2.1 Logical Device Assignment .................................................................................................. 47
6.2.2 Super I/O Configuration Registers ....................................................................................... 48
6.2.2.1 Logical Device Number (LDN)................................................................................. 48
6.2.2.2 Chip ID Byte 1 (CHIPID1)........................................................................................ 48
6.2.2.3 Chip ID Byte 2 (CHIPID2)........................................................................................ 48
6.2.2.4 Chip Version (CHIPVER)......................................................................................... 48
6.2.2.5 Super I/O Control Register (SIOCTRL) ................................................................... 48
6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)..................................................... 49
6.2.2.7 Super I/O General Purpose Register (SIOGP)........................................................ 49
6.2.2.8 Super I/O Power Mode Register (SIOPWR) ........................................................... 50
6.2.3 Standard Logical Device Configuration Registers................................................................ 50
6.2.3.1 Logical Device Activate Register (LDA)................................................................... 51
6.2.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 51
6.2.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 51
6.2.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 51
6.2.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 52
6.2.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 52
6.2.3.7 Interrupt Request Type Select (IRQTP) .................................................................. 52
6.2.3.8 DMA Channel Select 0 (DMAS0) ............................................................................ 53
6.2.3.9 DMA Channel Select 0 (DMAS1) ............................................................................ 53
6.2.4 System Wake-Up Control (SWUC) Configuration Registers ............................................... 53
6.2.4.1 Logical Device Activate Register (LDA)................................................................... 53
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 53
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6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 54
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54
6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 54
6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 54
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 55
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 55
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 55
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 55
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 55
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 56
6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 56
6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 56
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 56
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 57
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 57
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 57
6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 57
6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 57
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 58
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 58
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 58
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 58
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 58
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 58
6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 59
6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 59
6.2.7.9 Shared Memory Base Address High Byte Register (SHMBAH).............................. 59
6.2.7.10 Shared Memory Base Address Low Byte Register (SHMBAL) ............................... 59
6.2.7.11 Shared Memory Size Configuration Register (SHMSZ) .......................................... 60
6.2.7.12 LPC Memory Control (LPCMCTRL) ........................................................................ 60
6.2.8 Real Time Clock (RTC) Configuration Registers ................................................................. 60
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 61
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 61
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 61
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 61
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 62
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 62
6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 62
6.2.8.8 RAM Lock Register (RLR) ....................................................................................... 62
6.2.8.9 Date of Month Alarm Register Offset (DOMAO) ..................................................... 62
6.2.8.10 Month Alarm Register Offset (MONAO) .................................................................. 63
6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 63
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 63
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 63
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 63
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 64
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 64
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 64
6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 64
6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 64
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 65
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 65
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6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 65
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 65
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 65
6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 65
6.2.10.7 Interrupt Request Type Select (IRQTP) .................................................................. 65
6.2.11 Programming Guide ............................................................................................................. 67
6.3 Shared Memory Flash Interface Bridge (SMFI) ................................................................................ 69
6.3.1 Overview............................................................................................................................... 69
6.3.2 Features ............................................................................................................................... 69
6.3.3 Function Description............................................................................................................. 69
6.3.3.1 Flash Requirement .................................................................................................. 69
6.3.3.2 Host to M Bus Translation ....................................................................................... 69
6.3.3.3 Memory Mapping ..................................................................................................... 69
6.3.3.4 Indirect Memory Read/Write Transaction ................................................................ 70
6.3.3.5 Locking Between Host and EC Domains................................................................. 70
6.3.3.6 Host Access Protection............................................................................................ 71
6.3.3.7 Response to a Forbidden Access............................................................................ 71
6.3.3.8 Scratch SRAM ......................................................................................................... 71
6.3.3.9 No-wait Mode........................................................................................................... 72
6.3.3.10 Flash Interface ......................................................................................................... 72
6.3.4 EC Interface Registers ......................................................................................................... 76
6.3.4.1 FBIU Configuration Register (FBCFG) .................................................................... 76
6.3.4.2 Flash Programming Configuration Register (FPCFG)............................................. 77
6.3.4.3 Memory Zone Configuration Register (MZCFG) ..................................................... 77
6.3.4.4 Static Memory Zone Configuration Register (SMZCFG)......................................... 78
6.3.4.5 Flash EC Code Banking Select Register (FECBSR)............................................... 79
6.3.4.6 Flash Memory Size Select Register (FMSSR) ........................................................ 79
6.3.4.7 Flash Memory Prescaler Register (FMPSR) ........................................................... 80
6.3.4.8 Shared Memory EC Control and Status Register (SMECCS)................................. 80
6.3.4.9 Shared Memory Host Semaphore Register (SMHSR) ............................................ 81
6.3.4.10 Shared Memory EC Override Read Protect Registers 0-9 (SMECORPR 0-9) ....... 81
6.3.4.11 Shared Memory EC Override Write Protect Registers 0-9 (SMECOWPR0-9) ....... 82
6.3.5 Host Interface Registers....................................................................................................... 83
6.3.5.1 Shared Memory Indirect Memory Address Register 0 (SMIMAR0) ........................ 84
6.3.5.2 Shared Memory Indirect Memory Address Register 1 (SMIMAR1) ........................ 84
6.3.5.3 Shared Memory Indirect Memory Address Register 2 (SMIMAR2) ........................ 84
6.3.5.4 Shared Memory Indirect Memory Address Register 3 (SMIMAR3) ........................ 84
6.3.5.5 Shared Memory Indirect Memory Data Register (SMIMDR) ................................... 84
6.3.5.6 Shared Memory Host Access Protect Register 1-4 (SMHAPR1-4)........................ 84
6.3.5.7 Shared Memory Host Semaphore Register (SMHSR) ............................................ 85
6.4 System Wake-Up Control (SWUC) ...................................................................................................86
6.4.1 Overview............................................................................................................................... 86
6.4.2 Features ............................................................................................................................... 86
6.4.3 Functional Description..........................................................................................................86
6.4.3.1 Wake-Up Status....................................................................................................... 86
6.4.3.2 Wake-Up Events...................................................................................................... 87
6.4.3.3 Wake-Up Output Events.......................................................................................... 88
6.4.3.4 Other SWUC Controlled Options............................................................................. 88
6.4.4 Host Interface Registers....................................................................................................... 90
6.4.4.1 Wake-Up Event Status Register (WKSTR) ............................................................. 90
6.4.4.2 Wake-Up Event Enable Register (WKER)............................................................... 91
6.4.4.3 Wake-Up Signals Monitor Register (WKSMR) ........................................................ 91
6.4.4.4 Wake-Up ACPI Status Register (WKACPIR) .......................................................... 92
6.4.4.5 Wake-Up SMI Enable Register (WKSMIER)........................................................... 92
6.4.4.6 Wake-Up IRQ Enable Register (WKIRQER)........................................................... 93
6.4.5 EC Interface Registers ......................................................................................................... 93
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6.4.5.1 SWUC Control Status 1 Register (SWCTL1) .......................................................... 93
6.4.5.2 SWUC Control Status 2 Register (SWCTL2) .......................................................... 94
6.4.5.3 SWUC Control Status 3 Register (SWCTL3) .......................................................... 95
6.4.5.4 SWUC Host Configuration Base Address Low Byte Register (SWCBALR)............ 95
6.4.5.5 SWUC Host Configuration Base Address High Byte Register (SWCBAHR) .......... 95
6.4.5.6 SWUC Interrupt Enable Register (SWCIER)........................................................... 95
6.4.5.7 SWUC Host Event Status Register (SWCHSTR).................................................... 96
6.4.5.8 SWUC Host Event Interrupt Enable Register (SWCHIER) ..................................... 97
6.5 Keyboard Controller (KBC) ............................................................................................................... 98
6.5.1 Overview............................................................................................................................... 98
6.5.2 Features ............................................................................................................................... 98
6.5.3 Functional Description..........................................................................................................98
6.5.4 Host Interface Registers....................................................................................................... 99
6.5.4.1 KBC Data Input Register (KBDIR)......................................................................... 100
6.5.4.2 KBC Data Output Register (KBDOR) .................................................................... 100
6.5.4.3 KBC Command Register (KBCMDR) .................................................................... 100
6.5.4.4 KBC Status Register (KBSTR) .............................................................................. 100
6.5.5 EC Interface Registers ....................................................................................................... 101
6.5.5.1 KBC Host Interface Control Register (KBHICR).................................................... 101
6.5.5.2 KBC Interrupt Control Register (KBIRQR)............................................................. 102
6.5.5.3 KBC Host Interface Keyboard/Mouse Status Register (KBHISR) ......................... 103
6.5.5.4 KBC Host Interface Keyboard Data Output Register (KBHIKDOR) ...................... 103
6.5.5.5 KBC Host Interface Mouse Data Output Register (KBHIMDOR) .......................... 103
6.5.5.6 KBC Host Interface Keyboard/Mouse Data Input Register (KBHIDIR) ................. 104
6.6 Power Management Channel (PMC).............................................................................................. 105
6.6.1 Overview............................................................................................................................. 105
6.6.2 Features ............................................................................................................................. 105
6.6.3 Functional Description........................................................................................................ 105
6.6.3.1 General Description ............................................................................................... 105
6.6.3.2 Compatible Mode................................................................................................... 106
6.6.3.3 Enhanced PM mode .............................................................................................. 107
6.6.4 Host Interface Registers..................................................................................................... 108
6.6.4.1 PMC Data Input Register (PMDIR)........................................................................ 109
6.6.4.2 PMC Data Output Register (PMDOR) ................................................................... 109
6.6.4.3 PMC Command Register (PMCMDR) ................................................................... 109
6.6.4.4 Status Register (PMSTR) ...................................................................................... 109
6.6.5 EC Interface Registers ....................................................................................................... 110
6.6.5.1 PM Status Register (PMSTS)................................................................................ 110
6.6.5.2 PM Data Out Port (PMDO) .................................................................................... 111
6.6.5.3 PM Data Out Port with SCI (PMDOSCI)................................................................ 111
6.6.5.4 PM Data Out Port with SMI (PMDOSMI)............................................................... 111
6.6.5.5 PM Data In Port (PMDI)......................................................................................... 111
6.6.5.6 PM Data In Port with SCI (PMDISCI) .................................................................... 112
6.6.5.7 PM Control (PMCTL) ............................................................................................. 112
6.6.5.8 PM Interrupt Control (PMIC).................................................................................. 113
6.6.5.9 PM Interrupt Enable (PMIE) .................................................................................. 113
6.7 Real-Time Clock (RTC)................................................................................................................... 115
6.7.1 Overview............................................................................................................................. 115
6.7.2 Feature ............................................................................................................................... 115
6.7.3 Functional Description........................................................................................................ 115
6.7.4 Host Interface Registers..................................................................................................... 116
6.7.4.1 RTC Bank 0 Register............................................................................................. 118
6.7.4.1.1 Seconds Register (SECREG) ....................................................... 118
6.7.4.1.2 Seconds Alarm 1 Register (SECA1REG) ...................................... 118
6.7.4.1.3 Minutes Register (MINREG) ......................................................... 119
6.7.4.1.4 Minutes Alarm 1 Register (MINA1REG) ........................................ 119
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6.7.4.1.5 Hours Register (HRREG)............................................................... 119
6.7.4.1.6 Hours Alarm 1 Register (HRA1REG)............................................. 119
6.7.4.1.7 Day Of Week Register (DOWREG) ............................................... 119
6.7.4.1.8 Date Of Month Register (DOMREG).............................................. 120
6.7.4.1.9 Month Register (MONREG) ........................................................... 120
6.7.4.1.10 Year Register (YRREG)................................................................. 120
6.7.4.1.11 RTC Control Register A (CTLREGA)............................................. 120
6.7.4.1.12 RTC Control Register B (CTLREGB)............................................. 121
6.7.4.1.13 RTC Control Register C (CTLREGC) ............................................ 122
6.7.4.1.14 RTC Control Register D (CTLREGD) ............................................ 123
6.7.4.1.15 Date of Month Alarm 1 Register (DOMA1REG)............................. 123
6.7.4.1.16 Month Alarm 1 Register (MONA1REG) ......................................... 123
6.7.4.2 RTC Bank 1 Register............................................................................................. 123
6.7.4.2.1 Seconds Alarm 2 Register (SECA2REG) ...................................... 123
6.7.4.2.2 Minutes Alarm 2 Register (MINA2REG) ........................................ 123
6.7.4.2.3 Hours Alarm 2 Register (HRA2REG)............................................. 124
6.7.4.2.4 Date of Month Alarm 2 Register (DOMA2REG)............................. 124
6.7.4.2.5 Month Alarm 2 Register (MONA2REG) ......................................... 124
6.7.4.3 RTC I/O Register ................................................................................................... 124
6.7.4.3.1 RTC Index Register of Bank 0 (RIRB0) ......................................... 124
6.7.4.3.2 RTC Data Register of Bank 0 (RDRB0)......................................... 124
6.7.4.3.3 RTC Index Register of Bank 1 (RIRB1) ......................................... 125
6.7.4.3.4 RTC Data Register of Bank 1 (RDRB1)......................................... 125
7. EC Domain Functions ................................................................................................................................ 127
7.1 8032 Embedded Controller (EC)..................................................................................................... 127
7.1.1 Overview............................................................................................................................. 127
7.1.2 Features ............................................................................................................................. 127
7.1.3 General Description............................................................................................................ 127
7.1.4 Functional Description....................................................................................................... 127
7.1.5 Memory Organization ......................................................................................................... 128
7.1.6 On-Chip Peripherals........................................................................................................... 129
7.1.7 Timer / Counter................................................................................................................... 131
7.1.8 Idle and Doze/Sleep Mode ................................................................................................. 142
7.1.9 EC Internal Register Description........................................................................................ 143
7.1.9.1 Port 0 Register (P0R) ............................................................................................ 143
7.1.9.2 Stack Pointer Register (SPR) ................................................................................ 143
7.1.9.3 Data Pointer Low Register (DPLR)........................................................................ 143
7.1.9.4 Data Pointer High Register (DPHR) ...................................................................... 144
7.1.9.5 Data Pointer 1 Low Register (DP1LR)................................................................... 144
7.1.9.6 Data Pointer 1 High Register (DP1HR) ................................................................. 144
7.1.9.7 Data Pointer Select Register (DPSR).................................................................... 144
7.1.9.8 Power Control Register (PCON)............................................................................ 144
7.1.9.9 Timer Control Register (TCON)............................................................................. 146
7.1.9.10 Timer Mode Register (TMOD) ............................................................................... 146
7.1.9.11 Timer 0 Low Byte Register (TL0R) ........................................................................ 147
7.1.9.12 Timer 1 Low Byte Register (TL1R) ........................................................................ 147
7.1.9.13 Timer 0 High Byte Register (TH0R)....................................................................... 147
7.1.9.14 Timer 1 Low Byte Register (TH1R) ....................................................................... 147
7.1.9.15 Clock Control Register (CKCON) .......................................................................... 147
7.1.9.16 Port 1 Register (P1R) ............................................................................................ 148
7.1.9.17 Serial Port Control Register (SCON) ..................................................................... 148
7.1.9.18 Serial Port Buffer Register (SBUFR) ..................................................................... 149
7.1.9.19 Port 2 Register (P2R) ............................................................................................ 149
7.1.9.20 Interrupt Enable Register (IE) ................................................................................ 149
7.1.9.21 Port 3 Register (P3R) ............................................................................................ 149
7.1.9.22 Interrupt Priority Register (IP)................................................................................ 150
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7.1.9.23 Status Register (STATUS) ................................................................................... 150
7.1.9.24 Timer 2 Control Register (T2CON)........................................................................ 150
7.1.9.25 Timer Mode Register (T2MOD) ............................................................................. 151
7.1.9.26 Timer 2 Capture Low Byte Register (RCAP2LR) ..................................................151
7.1.9.27 Timer 2 Capture High Byte Register (RCAP2HR) ................................................. 151
7.1.9.28 Timer 2 Low Byte Register (TL2R) ........................................................................ 151
7.1.9.29 Timer 2 High Byte Register (TH2R)....................................................................... 152
7.1.9.30 Program Status Word Register (PSW) .................................................................. 152
7.1.9.31 Watch Dog Timer Control Register (WDTCON).................................................... 152
7.1.9.32 Accumulator Register (ACC) ................................................................................. 153
7.1.9.33 Power Down Control Register (PDCON)............................................................... 153
7.1.9.34 B Register (BR)...................................................................................................... 153
7.1.10 Programming Guide ........................................................................................................... 154
7.2 Interrupt Controller (INTC) .............................................................................................................. 155
7.2.1 Overview............................................................................................................................. 155
7.2.2 Features ............................................................................................................................. 155
7.2.3 Functional Description........................................................................................................ 155
7.2.3.1 Power Fail Interrupt ............................................................................................... 155
7.2.3.2 Programmable Interrupts....................................................................................... 155
7.2.4 EC Interface Registers ....................................................................................................... 156
7.2.4.1 Interrupt Status Register 0 (ISR0) ......................................................................... 157
7.2.4.2 Interrupt Status Register 1 (ISR1) ......................................................................... 157
7.2.4.3 Interrupt Status Register 2 (ISR2) ......................................................................... 158
7.2.4.4 Interrupt Status Register 3 (ISR3) ......................................................................... 158
7.2.4.5 Interrupt Enable Register 0 (IER0) ........................................................................ 158
7.2.4.6 Interrupt Enable Register 1 (IER1) ........................................................................ 159
7.2.4.7 Interrupt Enable Register 2 (IER2) ........................................................................ 159
7.2.4.8 Interrupt Enable Register 3 (IER3) ........................................................................ 159
7.2.4.9 Interrupt Edge/Level-Triggered Mode Register 0 (IELMR0).................................. 159
7.2.4.10 Interrupt Edge/Level-Triggered Mode Register 1 (IELMR1).................................. 159
7.2.4.11 Interrupt Edge/Level-Triggered Mode Register 2 (IELMR2).................................. 160
7.2.4.12 Interrupt Edge/Level-Triggered Mode Register 3 (IELMR3).................................. 160
7.2.4.13 Interrupt Polarity Register 0 (IPOLR0)................................................................... 160
7.2.4.14 Interrupt Polarity Register 1 (IPOLR1)................................................................... 160
7.2.4.15 Interrupt Polarity Register 2 (IPOLR2)................................................................... 162
7.2.4.16 Interrupt Polarity Register 3 (IPOLR3)................................................................... 162
7.2.4.17 Interrupt Vector Register (IVCT)............................................................................ 162
7.2.4.18 8032 INT0# Status (INT0ST)................................................................................. 162
7.2.4.19 Power Fail Register (PFAILR) ............................................................................... 163
7.2.5 INTC Interrupt Assignments ............................................................................................... 164
7.2.6 Programming Guide ........................................................................................................... 166
7.3 Wake-Up Control (WUC) ................................................................................................................ 167
7.3.1 Overview............................................................................................................................. 167
7.3.2 Features ............................................................................................................................. 167
7.3.3 Functional Description........................................................................................................ 167
7.3.4 EC Interface Registers ....................................................................................................... 167
7.3.4.1 Wake-Up Edge Mode Register (WUEMR1) .......................................................... 167
7.3.4.2 Wake-Up Edge Mode Register (WUEMR2) .......................................................... 168
7.3.4.3 Wake-Up Edge Mode Register (WUEMR3) .......................................................... 168
7.3.4.4 Wake-Up Edge Mode Register (WUEMR4) .......................................................... 168
7.3.4.5 Wake-Up Edge Sense Register (WUESR1).......................................................... 168
7.3.4.6 Wake-Up Edge Sense Register (WUESR2).......................................................... 169
7.3.4.7 Wake-Up Edge Sense Register (WUESR3).......................................................... 169
7.3.4.8 Wake-Up Edge Sense Register (WUESR4).......................................................... 169
7.3.4.9 Wake-Up Enable Register (WUENR1) .................................................................. 170
7.3.4.10 Wake-Up Enable Register (WUENR2) .................................................................. 170
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7.3.4.11 Wake-Up Enable Register (WUENR3) .................................................................. 170
7.3.4.12 Wake-Up Enable Register (WUENR4) .................................................................. 170
7.3.5 WUC Input Assignments .................................................................................................... 171
7.3.6 Programming Guide ........................................................................................................... 172
7.4 Keyboard Matrix Scan Controller .................................................................................................... 173
7.4.1 Overview............................................................................................................................. 173
7.4.2 Features ............................................................................................................................. 173
7.4.3 EC Interface Registers ....................................................................................................... 173
7.4.3.1 Keyboard Scan Out Low Byte Data Register (KSOLR)......................................... 173
7.4.3.2 Keyboard Scan Out High Byte Data Register (KSOHR) ....................................... 173
7.4.3.3 Keyboard Scan Out Control Register (KSOCTRLR) ............................................. 173
7.4.3.4 Keyboard Scan In Data Register (KSIR) ............................................................... 174
7.4.3.5 Keyboard Scan In Control Register (KSICTRLR).................................................. 174
7.5 General Purpose I/O Port (GPIO) ................................................................................................... 175
7.5.1 Overview............................................................................................................................. 175
7.5.2 Features ............................................................................................................................. 175
7.5.3 EC Interface Registers ....................................................................................................... 175
7.5.3.1 General Control Register (GCR) ........................................................................... 176
7.5.3.2 Port Data Registers A-I (GPDRA-GPDRI)............................................................. 176
7.5.3.3 Port Control n Registers (GPCRn, n = A0-I7)........................................................ 177
7.5.3.4 Output Type Registers A-I (GPOTA-GPOTI)......................................................... 177
7.5.4 Alternate Function Selection .............................................................................................. 179
7.5.5 Programming Guide ........................................................................................................... 181
7.6 EC Clock and Power Management Controller (ECPM) .................................................................. 182
7.6.1 Overview............................................................................................................................. 182
7.6.2 Features ............................................................................................................................. 182
7.6.3 EC Interface Registers ....................................................................................................... 182
7.6.3.1 Clock Frequency Select Register (CFSELR) ........................................................ 182
7.6.3.2 Clock Gating Control 1 Register (CGCTRL1R) ..................................................... 182
7.6.3.3 Clock Gating Control 2 Register (CGCTRL2R) ..................................................... 183
7.6.3.4 PLL Control (PLLCTRL) ........................................................................................ 183
7.7 SM Bus Interface (SMB) ................................................................................................................. 184
7.7.1 Overview............................................................................................................................. 184
7.7.2 Features ............................................................................................................................. 184
7.7.3 Functional Description........................................................................................................ 184
7.7.3.1 SMBUS Master Interface....................................................................................... 184
7.7.3.2 SMBUS Slave Interface ......................................................................................... 185
7.7.3.3 SMBUS Porting Guide ........................................................................................... 186
7.7.4 EC Interface Registers ....................................................................................................... 190
7.7.4.1 Host Status Register (HOSTA).............................................................................. 191
7.7.4.2 Host Control Register (HOCTL)............................................................................. 191
7.7.4.3 Host Command Register (HOCMD) ...................................................................... 192
7.7.4.4 Transmit Slave Address Register (TRASLA) ........................................................ 192
7.7.4.5 Data 0 Register (D0REG)...................................................................................... 192
7.7.4.6 Data 1 Register (D1REG)...................................................................................... 193
7.7.4.7 Host Block Data Byte Register (HOBDB) .............................................................. 193
7.7.4.8 Packet Error Check Register (PECERC)............................................................... 193
7.7.4.9 Receive Slave Address Register (RESLADR) ...................................................... 193
7.7.4.10 Slave Data Register (SLDA) .................................................................................. 193
7.7.4.11 SMBUS Pin Control Register (SMBPCTL) ............................................................ 194
7.7.4.12 Slave Status Register (SLSTA) ............................................................................. 194
7.7.4.13 Slave Interrupt Control Register (SICR) ................................................................ 195
7.7.4.14 Notify Device Address Register (NDADR)............................................................. 195
7.7.4.15 Notify Data Low Byte Register (NDLB).................................................................. 195
7.7.4.16 Notify Data High Byte Register (NDHB) ................................................................ 195
7.7.4.17 Host Control Register 2 (HOCTL2)........................................................................ 196
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7.7.4.18 4.7 µs Register (4P7USREG) ................................................................................ 196
7.7.4.19 4.0 µs Register (4P0USREG) ................................................................................ 196
7.7.4.20 300 ns Register (300NSREG) ............................................................................... 196
7.7.4.21 250 ns Register (250NSREG) ............................................................................... 197
7.7.4.22 25 ms Register (25MSREG).................................................................................. 197
7.7.4.23 45.3 µs Low Register (45P3USLREG) .................................................................. 197
7.7.4.24 45.3 µs High Register (45P3USHREG)................................................................. 197
7.8 PS/2 Interface ................................................................................................................................. 198
7.8.1 Overview............................................................................................................................. 198
7.8.2 Features ............................................................................................................................. 198
7.8.3 Functional Description........................................................................................................ 198
7.8.3.1 Hardware Mode Selected ...................................................................................... 198
7.8.3.2 Software Mode Selected ....................................................................................... 199
7.8.4 EC Interface Registers ....................................................................................................... 199
7.8.4.1 PS/2 Control Register 1-4 (PSCTL1-4) ................................................................. 200
7.8.4.2 PS/2 Interrupt Control Register 1-4 (PSINT1-4)................................................... 200
7.8.4.3 PS/2 Status Register 1-4 (PSSTS1-4)................................................................... 201
7.8.4.4 PS/2 Data Register 1-4 (PSDAT1-4) ..................................................................... 201
7.9 Digital To Analog Converter (DAC)................................................................................................. 202
7.9.1 Overview............................................................................................................................. 202
7.9.2 Feature ............................................................................................................................... 202
7.9.3 Functional Description........................................................................................................ 202
7.9.4 EC Interface Registers ....................................................................................................... 202
7.9.4.1 DAC Control Register (DACCTRL)........................................................................ 202
7.9.4.2 DAC Data Channel 0~3 Register (DACDAT0~3) .................................................. 203
7.10 Analog to Digital Converter (ADC) .................................................................................................. 204
7.10.1 Overview............................................................................................................................. 204
7.10.2 Features ............................................................................................................................. 204
7.10.3 Functional Description........................................................................................................ 204
7.10.3.1 ADC General Description ...................................................................................... 205
7.10.3.2 Voltage Measurement............................................................................................ 205
7.10.3.3 ADC Operation ...................................................................................................... 206
7.10.4 EC Interface Registers ....................................................................................................... 207
7.10.4.1 ADC Status Register (ADCSTS) ........................................................................... 207
7.10.4.2 ADC Configuration Register (ADCCFG)................................................................ 208
7.10.4.3 ADC Clock Control Register (ADCCTL) ................................................................ 208
7.10.4.4 ADC Delay Control Register (ADCDCTL) ............................................................. 209
7.10.4.5 Calibration Data Control Register (KDCTL) .......................................................... 209
7.10.4.6 Voltage Channel 1 Control Register (VCH1CTL) .................................................. 210
7.10.4.7 Volt Channel 1 Data Buffer LSB (VCH1DATL)...................................................... 212
7.10.4.8 Volt Channel 1 Data Buffer MSB (VCH1DATM).................................................... 212
7.10.4.9 Voltage Channel 2 Control Register (VCH2CTL) .................................................. 212
7.10.4.10 Volt Channel 2 Data Buffer LSB (VCH2DATL)...................................................... 212
7.10.4.11 Volt Channel 2 Data Buffer MSB (VCH2DATM).................................................... 212
7.10.4.12 Voltage Channel 3 Control Register (VCHN3CTL) ............................................... 213
7.10.4.13 Volt Channel 3 Data Buffer LSB (VCH3DATL)...................................................... 213
7.10.4.14 Volt Channel 3 Data Buffer MSB (VCH3DATM).................................................... 213
7.10.4.15 Volt High Scale Calibration Data Buffer LSB (VHSCDBL) .................................... 213
7.10.4.16 Volt High Scale Calibration Data Buffer MSB (VHSCDBM) .................................. 213
7.10.4.17 Volt High Scale Gain-Error Calibration Data Buffer LSB (VHSGCDBL) ............... 214
7.10.4.18 Volt High Scale Gain-Error Calibration Data Buffer MSB (VHSGCDBM) ............. 215
7.10.5 ADC Programming Guide................................................................................................... 215
7.11 PWM and SmartAuto Fan Control (PWM) ...................................................................................... 218
7.11.1 Overview............................................................................................................................. 218
7.11.2 Features ............................................................................................................................. 218
7.11.3 Functional Description........................................................................................................ 218
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7.11.3.1 General Description ............................................................................................... 218
7.11.3.2 SmartAuto Fan Control Mode................................................................................ 219
7.11.3.3 Manual Fan Control Mode ..................................................................................... 219
7.11.4 EC Interface Registers ....................................................................................................... 221
7.11.4.1 Channel 0 Clock Prescaler Register (C0CPRS) ................................................... 221
7.11.4.2 Cycle Time Register (CTR) ................................................................................... 222
7.11.4.3 PWM Duty Cycle Register 0 to 7(DCRi) ................................................................ 222
7.11.4.4 PWM Polarity Register (PWMPOL) ....................................................................... 222
7.11.4.5 Prescaler Clock Frequency Select Register (PCFSR) .......................................... 222
7.11.4.6 Prescaler Clock Source Select Group Low(PCSSGL) .......................................... 223
7.11.4.7 Prescaler Clock Source Select Group High(PCSSGh) ......................................... 224
7.11.4.8 Fan 1 Configuration Register (FAN1CNF)............................................................. 225
7.11.4.9 Fan 2 Configuration Register (FAN2CNF)............................................................. 225
7.11.4.10 SmartAuto Fan 1 Speed Range Register (AF1SRR) ............................................ 226
7.11.4.11 SmartAuto Fan 2 Speed Range Register (AF2SRR) ............................................ 226
7.11.4.12 Min/Off PWM Limit Register (MOPL)..................................................................... 226
7.11.4.13 Fan 1 Minimum PWM Duty Cycle Register (F1MPDCR) ...................................... 228
7.11.4.14 Fan 2 Minimum PWM Duty Cycle Register (F2MPDCR) ...................................... 228
7.11.4.15 Fan 1 Temperature LIMIT Register (F1TLIMITR) ................................................. 228
7.11.4.16 Fan 2 Temperature LIMIT Register (F2TLIMITR) ................................................. 228
7.11.4.17 Fan 1 Absolute Temperature LIMIT Register (F1ATLIMITR)................................ 229
7.11.4.18 Fan 2 Absolute Temperature LIMIT Register (F2ATLIMITR)................................ 229
7.11.4.19 Zone Hysteresis Register (ZHYSR)....................................................................... 229
7.11.4.20 Fan 1 Temperature Record Register (F1TRR)...................................................... 230
7.11.4.21 Fan 2 Temperature Record Register (F2TRR)...................................................... 230
7.11.4.22 Fan 1 Tachometer LSB Reading Register (F1TLRR) ........................................... 230
7.11.4.23 Fan 1 Tachometer MSB Reading Register (F1TMRR) ......................................... 230
7.11.4.24 Fan 2 Tachometer LSB Reading Register (F2TLRR) ........................................... 231
7.11.4.25 Fan 2 Tachometer MSB Reading Register (F2TMRR) ......................................... 231
7.11.4.26 Zone Interrupt Status Control Register (ZINTSCR)............................................... 231
7.11.4.27 Zone Temperature Interrupt Enable Register (ZTIER).......................................... 231
7.11.4.28 Channel 4 Clock Prescaler Register (C4CPRS) ................................................... 232
7.11.4.29 Channel 4 Clock Prescaler MSB Register (C4MCPRS)........................................ 232
7.11.4.30 Channel 6 Clock Prescaler MSB Register (C6MCPRS)........................................ 232
7.11.4.31 Channel 6 Clock Prescaler Register (C6CPRS) ................................................... 233
7.11.4.32 Channel 7 Clock Prescaler MSB Register (C7MCPRS)........................................ 233
7.11.4.33 Channel 7 Clock Prescaler Register (C7CPRS) ................................................... 233
7.11.5 PWM Programming Guide ................................................................................................. 234
7.12 EC Access to Host Controlled Modules (EC2I Bridge) ................................................................... 236
7.12.1 Overview............................................................................................................................. 236
7.12.2 Features ............................................................................................................................. 236
7.12.3 Functional Description........................................................................................................ 236
7.12.4 EC Interface Registers ....................................................................................................... 236
7.12.4.1 Indirect Host I/O Address Register (IHIOA)........................................................... 237
7.12.4.2 Indirect Host Data Register (IHD).......................................................................... 237
7.12.4.3 Lock Super I/O Host Access Register (LSIOHA) .................................................. 237
7.12.4.4 Super I/O Access Lock Violation Register (SIOLV)............................................... 238
7.12.4.5 EC to I-Bus Modules Access Enable Register (IBMAE)........................................ 238
7.12.4.6 I-Bus Control Register (IBCTL).............................................................................. 238
7.12.5 EC2I Programming Guide .................................................................................................. 239
7.13 Hardware Strap (HWS) ................................................................................................................... 242
7.13.1 Overview............................................................................................................................. 242
7.13.2 EC Interface Registers ....................................................................................................... 242
7.13.2.1 Hardware Strap Register (HWSR)......................................................................... 242
7.14 External Timer and External Watchdog (ETWD) ............................................................................ 243
7.14.1 Overview............................................................................................................................. 243
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7.14.2 Features ............................................................................................................................. 243
7.14.3 Functional Description........................................................................................................ 243
7.14.3.1 External Timer Operation ...................................................................................... 243
7.14.3.2 External WDT Operation ....................................................................................... 244
7.14.4 EC Interface Registers ....................................................................................................... 244
7.14.4.1 External Timer/WDT Configuration Register (ETWCFG) ...................................... 244
7.14.4.2 External Timer Prescaler Register (ETPSR) ......................................................... 245
7.14.4.3 External Timer Counter High Byte (ETCNTLHR) .................................................. 245
7.14.4.4 External Timer Counter Low Byte (ETCNTLLR) ................................................... 245
7.14.4.5 External Timer/WDT Control Register (ETWCTRL) .............................................. 245
7.14.4.6 External WDT Counter High Byte (EWDCNTLHR) ............................................... 246
7.14.4.7 External WDT Counter (EWDCNTLLR)................................................................. 246
7.14.4.8 External WDT Key Register (EWDKEYR)............................................................. 246
7.14.4.9 Reset Scratch Register (RSTSCR) ....................................................................... 246
7.14.4.10 Chip Version (ECHIPVER) .................................................................................... 247
7.15 Print Port (PP) ................................................................................................................................. 248
7.15.1 Overview............................................................................................................................. 248
7.15.2 Features ............................................................................................................................. 248
7.15.3 Functional Description........................................................................................................ 248
7.15.3.1 KBS Connection with Printer Port Connector........................................................ 248
7.15.3.2 In-System Programming Operation ....................................................................... 248
8. DC Characteristics ..................................................................................................................................... 251
Applied Voltage of VSTBY, VCC, AVCC, VBAT………….. 0.3V to +3.6V .................................................. 251
9. AC Characteristics ..................................................................................................................................... 253
10. Analog Device Characteristics................................................................................................................... 261
11. Package Information.................................................................................................................................. 263
12. Ordering Information.................................................................................................................................. 267
FIGURES
Figure 3-1. Host/Flash and EC/Flash Mapping (General)................................................................................... 6
Figure 3-2. Host/Flash and EC/Flash Mapping (Flash Size = 512k, EC Code = 64k, No User-Defined, a specific
example) ..................................................................................................................................................... 7
Figure 3-3. EC 8032 Data/Code Memory Map.................................................................................................... 9
Figure 5-1. Power State Transitions.................................................................................................................. 23
Figure 5-2. Clock Tree....................................................................................................................................... 31
Figure 5-3. LED connection............................................................................................................................... 37
Figure 6-1. Host View Register Map via Index-Data Pair ................................................................................. 47
Figure 6-2. Program Flow Chart for PNPCFG .................................................................................................. 68
Figure 6-3. Late Write and Early Write.............................................................................................................. 73
Figure 6-4. Fast Read and Normal Read .......................................................................................................... 73
Figure 6-5. Minimum Latency Timing of Flash Memory Read Cycle ................................................................ 74
Figure 6-6. Minimum Latency Timing of Flash Memory Read Cycle in LPC Burst........................................... 75
Figure 6-7. Minimum Latency Timing of Flash Memory Write Cycle ................................................................ 75
Figure 6-8. Wakeup Event and Gathering Scheme .......................................................................................... 86
Figure 6-9. KBRST# Output Scheme................................................................................................................ 89
Figure 6-10. GA20 Output Scheme................................................................................................................... 89
Figure 6-11. KBC Host Interface Block Diagram............................................................................................... 98
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Figure 6-12. IRQ Control in KBC Module.......................................................................................................... 99
Figure 6-13. PMC Host Interface Block Diagram............................................................................................ 105
Figure 6-14. EC Interrupt Request for PMC.................................................................................................... 106
Figure 6-15. IRQ/SCI#/SMI# Control in PMC Compatible Mode .................................................................... 107
Figure 6-16. IRQ/SCI#/SMI# Control in PMC Enhanced Mode ...................................................................... 108
Figure 6-17. Register Map of RTC .................................................................................................................. 117
Figure 7-1. Interrupt Control System Configuration ........................................................................................ 129
Figure 7-2. Interrupt Response Time .............................................................................................................. 131
Figure 7-3. Timer 0/1 in Mode 0 and Mode 1.................................................................................................. 131
Figure 7-4. Timer 0/1 in Mode 2, Auto-Reload................................................................................................ 132
Figure 7-5. Timer 0 in Mode 3 Two 8-bit Timers ............................................................................................. 132
Figure 7-6. Timer 2: Capture Mode................................................................................................................. 134
Figure 7-7. Timer 2: Auto Reload (DECN = 0) ................................................................................................ 135
Figure 7-8. Timer 2: Auto Reload Mode (DECN = 1) ...................................................................................... 135
Figure 7-9. Timer 2: Clock Out Mode.............................................................................................................. 136
Figure 7-10. Watchdog Timer.......................................................................................................................... 137
Figure 7-11. Serial Port Block Diagram........................................................................................................... 138
Figure 7-12. Mode 0 Timing ............................................................................................................................ 139
Figure 7-13. Data Frame (Mode 1, 2 and 3) ................................................................................................... 140
Figure 7-14. Timer 2 in Baud Rate Generator Mode ...................................................................................... 142
Figure 7-15. INTC Simplified Digram .............................................................................................................. 165
Figure 7-16. Program Flow Chart for INTC ..................................................................................................... 166
Figure 7-17. WUC Simplified Digram .............................................................................................................. 172
Figure 7-18. Program Flow Chart for WUC..................................................................................................... 172
Figure 7-19. GPIO Simplified Diagram............................................................................................................ 181
Figure 7-20. ADC Channels Control Diagram................................................................................................. 204
Figure 7-21. ADC Software Calibration Flow .................................................................................................. 216
Figure 7-22. ADC Software Calibration Flow in a Special Case ..................................................................... 217
Figure 7-23. SmartAuto Fan PWM output vs Temperature Reading .............................................................. 219
Figure 7-24. Program Flow Chart for PWM Channel Output .......................................................................... 234
Figure 7-25. Program Flow Chart for SmartAuto Fan Channel Output........................................................... 235
Figure 7-26. Program Flow Chart for EC2I Read............................................................................................ 240
Figure 7-27. Program Flow Chart for EC2I Write............................................................................................ 241
Figure 7-28. Simplified Diagram...................................................................................................................... 243
Figure 7-29. Parallel Port Female 25-Pin Connector ...................................................................................... 248
Figure 9-1. Reset Timing................................................................................................................................. 253
Figure 9-2. Warm Reset Timing ...................................................................................................................... 253
Figure 9-3. Wakeup from Doze Mode Timing ................................................................................................. 253
Figure 9-4. Wake Up from Sleep Mode Timing............................................................................................... 254
Figure 9-5. Asynchronous External Wakeup/Interrupt Source Edge Detected Timing................................... 254
Figure 9-6. LPC and SERIRQ Timing ............................................................................................................. 254
Figure 9-7. SWUC Wake Up Timing .............................................................................................................. 255
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Figure 9-8. Flash Read Cycle Timing............................................................................................................. 255
Figure 9-9. Flash Write Cycle Timing............................................................................................................. 256
Figure 9-10. PWM Output Timing .................................................................................................................. 257
Figure 9-11. PMC SMI#/SCI# Timing............................................................................................................. 257
Figure 9-12. PMC IBF/SCI# Timing ............................................................................................................... 258
Figure 9-13. PS/2 Receive/Transmit Timing .................................................................................................. 258
Figure 9-14. SMBUS Timing .......................................................................................................................... 259
TABLES
Table 3-1. Host/Flash Mapping ........................................................................................................................... 8
Table 3-2. EC/Flash Mapping ............................................................................................................................. 8
Table 3-3. Flash Read/Write Protection Controlled by EC Side ......................................................................... 8
Table 3-4. Flash Read/Write Protection Controlled by Host Side....................................................................... 8
Table 4-1. Pins Listed in Numeric Order (176-pin LQFP) ................................................................................. 14
Table 4-2. Pins Listed in Numeric Order (176-pin TFBGA) .............................................................................. 15
Table 4-3. Pins Listed in Alphabetical Order (176-pin LQFP/TFBGA).............................................................. 16
Table 5-1. Pin Descriptions of LPC Bus Interface............................................................................................. 17
Table 5-2. Pin Descriptions of External Flash Interface.................................................................................... 18
Table 5-3. Pin Descriptions of Keyboard Matrix Scan Interface ....................................................................... 18
Table 5-4. Pin Descriptions of SM Bus Interface .............................................................................................. 18
Table 5-5. Pin Descriptions of PS/2 Interface ................................................................................................... 18
Table 5-6. Pin Descriptions of PWM Interface .................................................................................................. 19
Table 5-7. Pin Descriptions of Wake Up Control Interface ............................................................................... 19
Table 5-8. Pin Descriptions of UART Interface ................................................................................................. 19
Table 5-9. Pin Descriptions of Parallel Port Interface ....................................................................................... 19
Table 5-10. Pin Descriptions of GPIO Interface ................................................................................................ 20
Table 5-11. Pin Descriptions of Hardware Strap............................................................................................... 21
Table 5-12. Pin Descriptions of NC................................................................................................................... 21
Table 5-13. Pin Descriptions of ADC Input Interface ........................................................................................ 21
Table 5-14. Pin Descriptions of DAC Output Interface ..................................................................................... 21
Table 5-15. Pin Descriptions of Clock ............................................................................................................... 22
Table 5-16. Pin Descriptions of Power/Ground Signals.................................................................................... 22
Table 5-17. Power States.................................................................................................................................. 23
Table 5-18. Quick Table of Power Plane for Pins ............................................................................................. 24
Table 5-19. Pin States of LPC Bus Interface .................................................................................................... 24
Table 5-20. Pin States of External Flash Interface............................................................................................ 25
Table 5-21. Pin States of Keyboard Matrix Scan Interface ............................................................................... 25
Table 5-22. Pin States of SM Bus Interface ...................................................................................................... 25
Table 5-23. Pin States of PS/2 Interface........................................................................................................... 25
Table 5-24. Pin States of PWM Interface.......................................................................................................... 26
Table 5-25. Pin States of Wake Up Control Interface ....................................................................................... 26
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Table 5-26. Pin States of UART Interface......................................................................................................... 26
Table 5-27. Pin States of GPIO Interface.......................................................................................................... 26
Table 5-28. Pin States of ADC Input Interface.................................................................................................. 26
Table 5-29. Pin States of DAC Output Interface ............................................................................................... 27
Table 5-30. Pin States of Clock......................................................................................................................... 27
Table 5-31. Reset Sources................................................................................................................................ 29
Table 5-32. Reset Types and Applied Module.................................................................................................. 29
Table 5-33. Clock Types ................................................................................................................................... 30
Table 5-34. Power Saving by EC Clock Operation Mode ................................................................................. 32
Table 5-35. Module Status in Each Power State/Clock Operation ...................................................................33
Table 5-36. Pins with Pull Function................................................................................................................... 34
Table 5-37. Pins with Schmitt-Trigger Function ................................................................................................ 35
Table 5-38. Signals with Open-Drain Function ................................................................................................. 35
Table 6-1. LPC/FWH Response........................................................................................................................ 40
Table 6-2. Host View Register Map, PNPCFG ................................................................................................. 44
Table 6-3. Host View Register Map, Logical Devices ....................................................................................... 45
Table 6-4. Host View Register Map via Index-Data I/O Pair, Standard Plug and Play Configuration Registers46
Table 6-5. Interrupt Request (IRQ) Number Assignment, Logical Device IRQ via SERIRQ ............................ 46
Table 6-6. Logical Device Number (LDN) Assignments ................................................................................... 47
Table 6-7. Host View Register Map via Index-Data I/O Pair, SWUC Logical Device ....................................... 53
Table 6-8. Host View Register Map via Index-Data I/O Pair, KBC / Mouse Interface Logical Device.............. 55
Table 6-9. Host View Register Map via Index-Data I/O Pair, KBC / Keyboard Interface Logical Device ......... 56
Table 6-10. Host View Register Map via Index-Data I/O Pair, SMFI Interface Logical Device ........................ 57
Table 6-11. Host View Register Map via Index-Data I/O Pair, RTC Logical Device......................................... 61
Table 6-12. Host View Register Map via Index-Data I/O, PM1 Logical Device ................................................ 63
Table 6-13. Host View Register Map via Index-Data I/O, PM2 Logical Device ................................................ 64
Table 6-14. Mapped Host Memory Address ..................................................................................................... 70
Table 6-15. M-bus Grant Behavior.................................................................................................................... 72
Table 6-16. EC View Register Map, SMFI ........................................................................................................ 76
Table 6-17. Host View Register Map, SMFI...................................................................................................... 83
Table 6-18. Host View Register Map, SWUC ................................................................................................... 90
Table 6-19. EC View Register Map, SWUC...................................................................................................... 93
Table 6-20. Host View Register Map, KBC ....................................................................................................... 99
Table 6-21. EC View Register Map, KBC ....................................................................................................... 101
Table 6-22. Host View Register Map, PMC .................................................................................................... 108
Table 6-23. EC View Register Map, PMC....................................................................................................... 110
Table 6-24. Host View Register Map, RTC ..................................................................................................... 116
Table 6-25. Host View Register Map via Index-Data I/O Pair, RTC Bank 0 ................................................... 118
Table 6-26. Host View Register Map via Index-Data I/O Pair, RTC Bank 1 ................................................... 118
Table 7-1. 8032 Port Usage ........................................................................................................................... 127
Table 7-2. System Interrupt Table................................................................................................................... 129
Table 7-3. Timer 2 Modes of Operation .......................................................................................................... 136
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IT8510E
Table 7-4. Serial Port Signals.......................................................................................................................... 138
Table 7-5. Selecting the Baud Rate Generator(s)........................................................................................... 141
Table 7-6. Internal RAM Map .......................................................................................................................... 143
Table 7-7. EC View Register Map, INTC ........................................................................................................ 156
Table 7-8. INTC Interrupt Assignments........................................................................................................... 164
Table 7-9. EC View Register Map, WUC ........................................................................................................ 167
Table 7-10. WUC Input Assignments.............................................................................................................. 171
Table 7-11. EC View Register Map, KB Scan................................................................................................. 173
Table 7-12. EC View Register Map, GPIO...................................................................................................... 175
Table 7-13. GPIO Alternate Function.............................................................................................................. 179
Table 7-14. EC View Register Map, ECPM .................................................................................................... 182
Table 7-15. EC View Register Map, SMBUS.................................................................................................. 190
Table 7-16. EC View Register Map, PS/2 ....................................................................................................... 199
Table 7-17. EC View Register Map, DAC ....................................................................................................... 202
Table 7-18. EC View Register Map, ADC ....................................................................................................... 207
Table 7-19. Detail Step of ADC Channel Conversion ..................................................................................... 215
Table 7-20. EC View Register Map, PWM ...................................................................................................... 221
Table 7-21. EC View Register Map, EC2I....................................................................................................... 237
Table 7-22. EC View Register Map, HWS ...................................................................................................... 242
Table 7-23. EC View Register Map, ETWD .................................................................................................... 244
Table 8-1. Power Consumption....................................................................................................................... 252
Table 9-1. Reset AC Table.............................................................................................................................. 253
Table 9-2. Warm Reset AC Table ................................................................................................................... 253
Table 9-3. Wakeup from Doze Mode AC Table .............................................................................................. 254
Table 9-4. Wake Up from Sleep Mode AC Table............................................................................................ 254
Table 9-5. Asynchronous External Wakeup/Interrupt Source Edge Detected AC Table................................ 254
Table 9-6. LPC and SERIRQ AC Table .......................................................................................................... 255
Table 9-7. SWUC Wake Up AC Table ............................................................................................................ 255
Table 9-8. Flash Read Cycle AC Table........................................................................................................... 256
Table 9-9. Flash Write Cycle AC Table........................................................................................................... 256
Table 9-10. PWM Output AC Table ................................................................................................................ 257
Table 9-11. PMC SMI#/SCI# AC Table........................................................................................................... 257
Table 9-12. PMC IBF/SCI# AC Table ............................................................................................................. 258
Table 9-13. PS/2 Receive/Transmit AC Table ................................................................................................ 258
Table 9-14. SMBUS AC Table ........................................................................................................................ 259
Table 10-1. ADC Characteristics..................................................................................................................... 261
Table 10-2. DAC Characteristics..................................................................................................................... 261
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s
Feature
1. Features
8032 Embedded Controller
− Twin Turbo version
− 1 instruction at 1 machine cycle
− Maximum 10 MHz for EC domain and 8032
− Instruction set compatible with standard 8051
LPC Bus Interface
− Compatible with the LPC specification v1.1
− Supports I/O read/write
− Supports Memory read/write
− Supports FWH read/write
− Serial IRQ
External Flash Interface
− Up to 4M bytes Flash space shared by the host
and EC side
− 8-bit data bus
SM Bus Controller
− SM Bus spec. 2.0
− SM Bus host and slave
System Wake Up Control
− Modem RI# wake up
− Telephone RING# wake up
− IRQ/SMI routing
EC Wake Up Control
− 32 external/internal wake up events
Interrupt Controller
− 32 interrupt events to EC
− Fixed priority
Timer / Watch Dog Timer
− 3 16-bit multi-function timers inside 8032, which
is based on EC clock
− 1 watch dog timer inside 8032, which is based
on EC clock
− 1 external timer in ETWD module, which is
based on RTC clock
− 1 external WDT in ETWD module, which is
based on RTC clock
UART
− Full duplex UART
− Supports power-switch circuit
− Supports two alarms
GPIO
− Supports 71-bit GPIO
− Programmable pull up/pull down
− Schmitt trigger for input
KBC Interface
− 8042 style KBC interface
− Legacy IRQ1 and IRQ12
− Fast A20G and KB reset
ADC
− 14 ADC channels (10 external)
− 10-bit ADC resolution (accuracy ±4LSB)
− Digital filter for noise reduction
− Conversion time for 14 channels within 100 ms
DAC
− 4 DAC channels
− 8-bit DAC
PWM with SmartAuto Fan Control
− 8 PWM channels
− SmartAuto Fan control
− Base clock frequency is 32.768KHz
− 2 Tachometers for measuring fan speed
PS/2 Interface
− 4 PS/2 interface
− Hardware/Software mode selection
KB Matrix Scan
− Hardware keyboard scan
− 16x8 keyboard matrix scan
In-System Programming
− ISP via parallel port interface on existing KBS
connector
− Fast flash programming with software provided
by ITE
Power Consumption
− Standby with Sleep mode current: 50 µA
Package
− 176 pin LQFP
ACPI Power Management Channel
− 2 Power Management channels
− Compatible and enhanced mode
RTC
− Supports 2 lockable memory areas
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ITPM-PN-200514
Specifications subject to Change without Notice By Jimmy Hou, 5/6/2005
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General Description
2. General Description
The IT8510 is a highly integrated embedded controller with system functions suitable for mobile system
applications. The IT8510 directly interfaces to the LPC bus and provides ACPI embedded controller function,
keyboard controller (KBC) and matrix scan, external flash interface for system BIOS and EC code, PWM, ADC
and SmartAuto Fan control for hardware monitor, PS/2 interface for external keyboard/mouse devices, RTC
and system wake up functions for system power management. It also supports the external flash ( or EPROM)
to be shared by the host and EC side.
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3. System Block Diagram
3.1 Block Diagram
LPC to I Bus / SERIRQ
Expansion Memory
M Bus
SMFI
Memory Bus
M Bus MUX
PNPCFG Regs
System Block Diagram
I Bus Arbiter RTC
Internal Bus(I Bus)
Print Port
PP
Internal SRAM
(Scratch)
GPIO
Smart-Fan
PWM
PS/2
signaling
EC (8032)
Digital Filter
ADC
EC2IINTC
EC Dedicated Bus (EC Bus)
DAC
EC
Wake-Up Ctrl
SM Bus
KBC SWUC PCM I/F
KB Scan
EC PMU
Clock Gen
ECPM
ETWD
• Host Domain:
LPC, PNPCFG, RTC logic device, host parts of SMFI/SWUC/KBC/PMC logical devices and host parts of
EC2I.
• EC Domain:
EC 8032, INTC, WUC KB Scan, GPIO, ECPM, SMB, PS/2, DAC, ADC, PWM, HWS, ETWD, PP, EC2I, EC
parts of SMFI/SWUC/KBC/PMC and EC parts of EC2I.
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IT8510E
3.2 Host/EC Mapped Memory Space
EC
Code Memory Space
Common Bank
32k
32k
(byte) (byte)
FFFF_FFFFh
FFFF_0000h
FFFE_FFFFh
FFFE_0000h
FFFD_FFFFh
Variable, not necessary
on 32k boundary
1_0000_0000h - Flash_Size
FFFF_FFFFh - Flash_Size
SHMBA+User_Defined_Size-1
SHMBA
000F_FFFFh
000F_0000h
000E_FFFFh
000E_0000h
000D_FFFFh
0000_0000h
Host Memory Space
4G Top Flash Space Top
RANGE 1
RANGE 2
64k
64k
RANGE 3
EC Code:
RANGE 4
Max 160k
Flash_Size
Flash_Size - 1
Flash_Size - 01_0000h
Flash_Size - 01_0001h
Flash_Size - 02_0000h
Flash_Size - 02_0001h
Variable, not necessary
on 32k boundary
00_0000h
Out of Range
These five banks are arragned in order and totally 160K mappe d.
RANGE 1
RANGE 2
RANGE 3
RANGE 4
User_Defined_Size
( Max Flash_Size )
If User_Defined_Size < Flash_Size,
only top of the flash space is mapped,
and the bottom is truncated.
Each bank is always mapped but it is only valid if it is used by EC code.
If EC code size <= 64K, Bank 0 is valid to be selected.
If EC code size <= 96K, Bank 0-1 are valid to be selected.
If EC code size <= 128K, Bank 0-2 are valid to be selected.
If EC code size <= 160K, Bank 0-3 are valid to be selected.
If EC code size is not mutiple of 32K, the remainder can be
used by host memory.
Out of Range
RANGE 1
RANGE 2
64k
64k
Out of Range
Expansion Flash Space
RANGE 1
RANGE 2
RANGE 3
RANGE 4
The range 4 shows space used by EC code and five banks are
all used.
The interface line will be lower if EC code size is smaller than 160K.
(byte)
Bank 3 (32k)
Bank 2 (32k)
Bank 1 (32k)
Bank 0 (32k)
Common Bank (32k)
FFFFh
Bank 0 Bank 1 Bank 3Bank 2
8000h
7FFFh
0000h
Bank 0, 1, 2 and 3 occupy the same code memory space.
Only one of these four banks can be selected at once time.
It is selected by ECBB or P1 register.
Figure 3-1. Host/Flash and EC/Flash Mapping (General)
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System Block Diagram
EC
Code Memory Space
Bank 0
Common Bank
32k
32k
FFFF_FFFFh
FFFF_0000h
FFFE_FFFFh
FFFE_0000h
FFFD_FFFFh
FFF8_FFFFh
FFF8_0000h
FFF7_FFFFh
Host Memory Space
4G Top Flash Space Top
RANGE 1
RANGE 2
RANGE 3
RANGE 4
Out of Range
64k
64k
512k
64k
(byte)(byte)
07_FFFFh
07_0000h
06_FFFFh
06_0000h
05_FFFFh
01_0000hFFF9_0000h
00_FFFFh
00_0000h
Expansion Flash Space
RANGE 1
RANGE 2
RANGE 3
RANGE 4
(byte)
Bank 0 (32k)
Common Bank (32k)
Bank 1-3 are not valid to be selected and are not shown.
FFFFh
8000h
7FFFh
0000h
000F_FFFFh
000F_0000h
000E_FFFFh
000E_0000h
000D_FFFFh
0000_0000h
RANGE 1
RANGE 2
Out of Range
64k
64k
Figure 3-2. Host/Flash and EC/Flash Mapping (Flash Size = 512k, EC Code = 64k, No User-Defined, a
specific example)
The flash memory space is shared between the host side and EC side, and it is shown in Figure 3-1.
An example of 512k flash size, 64k EC code size and no user-defined is shown in Figure 3-2.
The host memory 4G byte top is always mapped into the top of flash space and the host processor fetches the
first instruction after reset at FFFF_FFF0h in the host memory, which is 16 bytes below the uppermost flash
space.
The bottom of EC code is always mapped into the bottom of flash space and EC R8032TT micro-controller
fetches the first instruction after reset at 00_0000h in the EC code memory, which is 1 byte in the lowermost
flash space.
The interface line of host memory and EC code is variable and not necessary on 32k boundary.
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IT8510E
Table 3-1. Host/Flash Mapping
Host Memory Space
on LPC Bus (byte)
(1_0000_0000h–Flash_Size)~
FFFF_FFFFh
SHMBA ~
(SHMBA+User_Defined_Size-1)
000F_0000h ~
000F_FFFFh
000E_0000h ~
000E_FFFFh
Note: The host side can map all flash range regardless of EC code space.
Note: All host mappings are controlled by LPCMEN and FWHEN bit in SHMC register.
Note: Flash Size is defined in FMSSR register, and it may be 128k, 256k, 512k, 1M, 2M and the maximum 4M bytes.
Note: User_Defined_Size is defined in SHMUSZ register.
Expansion Flash Space (byte)
00_0000h~
(Flash_Size-1)
(Flash_Size-User_Defined_Size)~
(Flash_Size-1)
(Flash_Size-01_0000h)~
(Flash_Size-1)
(Flash_Size-02_0000h)~
(Flash_Size-01_0001h)
Mapped
Size
(byte)
Flash_Size
User_Defined_Size
( <= Flash_Size )
64k
64k
Mapping
Condition
Always
USRMEM=1
Always
BIOSEXTS=1
Table 3-2. EC/Flash Mapping
EC Code
Memory Space (byte)
Flash Address Range (byte)
Bank 3: 8000h ~ FFFFh 02_0000h ~ 02_7FFFh 32k Always
Bank 2: 8000h ~ FFFFh 01_8000h ~ 01_FFFFh 32k Always
Bank 1: 8000h ~ FFFFh 01_0000h ~ 01_7FFFh 32k Always
Bank 0: 8000h ~ FFFFh 00_8000h ~ 00_FFFFh 32k Always
Common Bank: 0000h ~ 7FFFh 00_0000h ~ 00_7FFFh 32k Always
Note: EC code can use the maximum 160k by banking.
Note: All EC code memory space is mapped to both EC and host side at the same time. The EC size is not necessary on
32k boundary.
Note: If BSO=1, ECBB is replaced with P1 register of 8032.
ECBB means ECBB field in FECBSR register.
BSO means BSO bit in FPCFG register.
Mapped
Size
(byte)
Mapping
Condition
Bank Selected
Condition
ECBB=11
ECBB=10
ECBB=01
ECBB=00
Always
Table 3-3. Flash Read/Write Protection Controlled by EC Side
Flash Address
Range (byte)
38_0000h ~ 3F_FFFFh ORP56 ~ 63 in SMECORPR9 ORP56 ~ 63 in SMECOWPR9
30_0000h ~ 37_FFFFh ORP48 ~ 55 in SMECORPR8 ORP48 ~ 55 in SMECOWPR8
28_0000h ~ 2F_FFFFh ORP40 ~ 47 in SMECORPR7 ORP40 ~ 47 in SMECOWPR7
20_0000h ~ 27_FFFFh ORP32 ~ 39 in SMECORPR6 ORP32 ~ 39 in SMECOWPR6
18_0000h ~ 1F_FFFFh ORP24 ~ 31 in SMECORPR5 ORP24 ~ 31 in SMECOWPR5
10_0000h ~ 17_FFFFh ORP16 ~ 23 in SMECORPR4 ORP16 ~ 23 in SMECOWPR4
08_0000h ~ 0F_FFFFh ORP8 ~ 15 in SMECORPR3 ORP8 ~ 15 in SMECOWPR3
02_0000h ~ 07_FFFFh ORP2 ~ 7 in SMECORPR2 ORP2 ~ 7 in SMECOWPR2
01_0000h ~ 01_FFFFh ORPLA8~15 in SMECORPR1 ORPLA8 ~ 15 in SMECOWPR1
00_0000h ~ 00_FFFFh ORPLA0 ~ 7 in SMECORPR0 ORPLA0 ~ 7 in SMECOWPR0
All ranges are write-control by
Read Control
Register Bits
Write Control
Register Bits
Note
Each bit controls
64K bytes
Each bit controls
8K bytes
HOSTWA, too.
Table 3-4. Flash Read/Write Protection Controlled by Host Side
Flash Address
Range (byte)
30_0000h ~ 3F_FFFFh HRP in SMHAPR4 HRW in SMHAPR4
20_0000h ~ 2F_FFFFh HRP in SMHAPR3 HRW in SMHAPR3
10_0000h ~ 1F_FFFFh HRP in SMHAPR2 HRW in SMHAPR2
00_0000h ~ 0F_FFFFh HRP in SMHAPR1 HRW in SMHAPR1
Read Control
Register Bits
Write Control
Register Bits
Note
Each index
controls
64K bytes
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3.3 EC Mapped Memory Space
EC Internal EC External EC
Data Memory Space Data Memory Space Code Mem o ry Space
FFFFh
System Block Diagram
(byte)
FFFFh
Scratch ROM 2KB
F800h
FFh
7fh
Direct & Indirect
00h
Indirect SF R
8000h
1F00h
1E00h
1D00h
1C00h
1B00h
1A00h
1900h
1800h
1700h
1600h
1500h
1400h
1300h
1200h
1100h
1000h
0800h
0000h
Reserved
Bank
HW S, ETW D 0,1,2 or 3
ECPM
KB Scan
SM Bus
WUC
DAC
ADC
PW M
PS/2
Be a RAM or ROM
at one time
GPIO
PMC
SW UC
KBC Comm on
EC2I Bank
INT C
SMFI
Reserved
Scratch RAM 2KB
corresponging move corresponging read/write corresponging read
instruction: MOV instruction: MOVX instruction: MOVC
Figure 3-3. EC 8032 Data/Code Memory Map
There is an internal Scratch SRAM which can be located at data space or code space but cannot be located at
both spaces at the same time. Where it is located depends on Scratch SRAM Map Control bit (SSMC) in
FBCFG register. It is called Scratch RAM when being located at data space (default after reset) and called
Scratch ROM when being located at code space.
The EC code space is 64k bytes and physically occupies the maximum 160 k bytes at the bottom of the flash
space. Refer to Figure 3-1 on page 6 for the details.
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IT8510E
3.4 Register Abbreviation
The register abbreviations and access rules are listed as follows:
R READ ONLY. If a register is read only, writing to this register has no effect.
W WRITE ONLY. If a register is write only, reading to this register returns all zero.
R/W READ/WRITE. A register with this attribute can be read and written.
RC READ CLEAR. If a register is read clear, reading to this register clears the register to ‘0’.
R/WC READ/WRITE CLEAR. A register bit with this attribute can be read and written. However,
writing 1 clears the corresponding bit and writing 0 has no effect.
BFNAME@REGNAME This abbreviation may be shown in figures to represent one bit in a register or one
field in a register.
The used radix indicator suffixes in this specification are listed below
Decimal number: "d" suffix or no suffix
Binary number: "b" suffix
Hexadecimal number: "h" suffix
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4. Pin Configuration
GPC5
TMRI1/WUI3/GPC6
GPI6
FCS#
176
175
174
45
46
VSS
VSTBY
173
4847505453
GPH0
CLKOUT/GPC0
CK32KOUT/GPC7
LPCPD#/WUI6/GPE6
CLKRUN#/WUI7/GPE7
LPCRST#/WUI4/GPD2
PWRSW/GPE4
FA20/GPG4
FA21/GPG5
GA20/GPB5
KBRST#/GPB6
SERIRQ
LFRAME#
LAD3
LAD2
LAD1
LAD0
VCC
VSS
LPCCLK
WRST#
ECSMI#
PWUREQ#
RI1#/WUI0/GPD0
LPC80HL/GPG6
LPC80LL/GPG7
RI2#/WUI1/GPD1
ECSCI#/GPD3
PWM0/GPA0
PWM1/GPA1
VSTBY
VSS
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/GPA6
GPD4
GINT/GPD5
PWM7/GPA7
WUI5/GPE5
1
2
3
4
5
6
7
8
NC
9
10
11
NC
12
NC
13
14
15
16
17
18
19
20
NC
21
NC
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TMRI0/WUI2/GPC4
SMDAT1/GPC2
GPC3
SMCLK1/GPC1
VSS
GPI5
RING#PWRFAIL#/LPCRST#/GPB7
VSTBY
SMDAT0/GPB4
GPB2
SMCLK0/GPB3
CK32KE
VBAT
VSS
VSTBY
CK32K
GP13
GP14
TXD/GPB1
GP12
RXD/GPB0
FRD#
FWR#
GPI1
FD7
GPI0
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
IT8510
E
Pinout
Top View
52
51
49
KSO2/PD2
KSO0/PD0
KSO1/PD1
56
55
GPH1
GPH2
KSO6/PD6
KSO5/PD5
KSO4/PD4
KSO3/PD3
59
585760
KSO7/PD7
KSO8/ACK#
62
61
646366
65
KSO14
KSO10/PE
KSO9/BUSY
KSO13
KSO12/SLCT
KSO11/ERR#
TACH1/GPD7
TACH0/GPD6
69
686770
GPH3
KSO15
72
71
747376
GPH4
KSI2/INIT#
KSI0/STB#
KSI1/AFD#
KSI3/SLIN#
Pin Configuration
FD5
FD6
FD4
FA9
FA8
FD2
FD3
FD1
VSS
FD0
VSTBY
FA11
FA10
FA7
146
145
144
143
142
141
140
139
138
137
136
135
134
133
82
81
79
787780
75
KSI6
KSI7
KSI4
KSI5
GPH6
GPH5
8483868887
85
NC
ADC3NCADC1
ADC2
ADC0
ADC4/GPE0
ADC5/GPE1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
FA6
FA5/SHBM
FA12
FA13
FA4/PPEN
FA3/BADDR1
FA2/BADDR0
FA1
FA0
VSTBY
VSS
FA14
FA15
PS2DAT3/GPF7
PS2CLK3/GPF6
PS2DAT2/GPF5
PS2CLK2/GPF4
PS2DAT1/GPF3
PS2CLK1/GPF2
FA16/GPG0
FA17/GPG1
PS2DAT0/GPF1
PS2CLK0/GPF0
NC
NC
NC
NC
GPH7
FA18/GPG2
FA19/GPG3
DAC3
DAC2
DAC1
DAC0
NC
NC
AVSS
AVCC
ADC9
ADC8
NC
NC
ADC7/GPE3
ADC6/GPE2
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IT8510E
IT8510G Top View
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TMRI1/
WU I3/G P C 6
CK32KOUT/
GPC7
FA2 0/GPG 4
CLKRUN#/
WU I7/G P E 7
LPC80LL/
GPG7
ECSCI#/
GPD3
PWM1/
GPA1
PWM3/
GPA3
PWM6/
GPA6
PWM7/
GPA7
WU I5/G P E 5
GPI6
GPC5 FA11FD1FD3 FA6GPC3FCS #
PWRSW/
GPE4
LAD3SERIRQ
LAD2LFRAME#
LAD0LAD1
VCCVCC
ECSMI#NC
RI1#/WUI0/
GPD0
RI2#/WUI1/
GPD1
PWM0/
GPA0
PWM2/
GPA2
PWM5/
GPA5
GINT/GPD5
GPH0
CLKOUT/
GPC0
TMRI0/
WU I2 /GP C4
SMDAT1/
GPC2
RING#/PWRFAIL#/
LPC RS T#/GPB 7
GPI5
FA2 1/GPG 5
KBRST#/
GPB6
LPCPD#/
WU I6/G P E 6
LPCRST#/
WU I4 /GP D2
PWM4/
GPA4
SMDAT0/
GPB4
SMCLK1/
GPC1
LPC80H L/
GPG6
KSO9/BUSYGPD4
KSO6/PD6KSO4/PD4
KSO7/PD7GPH2KSO3/PD3KSO0/PD0
SMCLK0/
GPB3
KSO11/
ERR#
TACH1/
GPD7
TACH0/
GPD6
KSO12/
SLCT
GPI1TXD/GPB1GP I4GPB2
FWR#GP I2GP I3
GPI0VSTBYVSTBYLPCCLKGA20/GPB5
PS2DAT3/
VSSVSTBYVSBTBYVSTBYPWUREQ#WRS T#
VSSVSSVSSVSTBY
FA1 7/GPG 1
VSSVSSVSSVSTBYKSO5/PD5
PS2CLK0/
VSSVSSVSSVSTBYVSTBY
KSI5KSI3/SLIN#KSO15
GPH6KSI0/STB#KSO14
KSI2/INIT# KSI4
KSI1/AFD#
FD7
FD6
FD4
GPF7
VSS
GPF0
GPH5
FA8
FA9
FA12FD5
FA3/
BADDR1
PS2CLK3/
GPF6
PS2DAT1/
GPF3
PS2DAT0/
GPF1
GPH7
FA1 9/GPG 3FA 18/GP G2
KSI7KSI6
FA10FD0FD2 FA7FRD#RXD/GPB0CK32KCK32KEVBAT
FA13FA5/SHBM
FA2FA4/PPEN
FA0FA 1
FA15FA 14
PS2CLK2/
PS2DAT2/
GPF4
GPF5
PS2CLK1/
FA16 /GPG0
GPF2
DAC3DAC2
DAC1DAC0
AVSSAVSS
AVCCAVCC
ADC8ADC9
NCNC
NCADC3ADC1 ADC6/GPE2GPH4KSO13KSO10/PEKSO8/ACK#GPH1KSO2/PD2KSO1/PD1
NCADC2ADC0 ADC4/GPE0GPH3
ADC7/GPE3
ADC5/GPE1
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IT8510G Bottom View
Pin Configuration
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FA10 FD0 FD2FA7 FRD# RXD/GPB0 CK32K CK32KE VBAT
FA1 3 FA5/S HB M
FA2 FA4/PPEN
FA0 FA 1
FA1 5 FA 14
PS2CLK2/
PS2DAT2/
GPF4
GPF5
PS2CLK1/
FA1 6/GPG 0
GPF2
DAC3 DAC2
DAC1 DAC0
AVSS AVSS
AVCC AVCC
ADC8 ADC9
NC NC
ADC7/GPE3
ADC5/GPE1
NC ADC3 ADC1ADC6/GPE2 GPH4 KSO13 KSO10/PE KSO8/ACK# GPH1 KSO2/PD2 KSO1/PD1
NC ADC2 ADC0ADC4/GPE0 GPH3
FA8
FD7
FA9
FD6
FA12 FD5
FA3 /
FD4
BADDR1
PS2CLK3/
PS2DAT3/
GPF6
GPF7
PS2DAT1/
VSS
GPF3
PS2DAT0/
FA1 7/GPG 1
GPF1
PS2CLK0/
GPH7
GPF0
FA19/GPG3FA18/GPG2
KSI7 KSI6
GPH5
GPI1 TX D/GPB1 GPI4 GP B2
FWR# GPI2 GP I3
GPI0 VSTBY VSTBY LPCCLK GA20/GPB5
VSS VSTBY VSBTBY VSTBY PWUREQ# WRST#
VSS VSS VSS VSTBY
VSS VSS VSS VSTBY KSO5/PD5
VSS VSS VSS VSTBY VSTBY
KSI5 KSI3/SLIN# KSO15
GPH6 KSI0/STB# KSO14
KSI2/INIT#KSI4
KSI1/AFD#
KSO12/
SLCT
SMCLK0/
GPB3
KSO11/
ERR#
TACH1/
GPD7
TACH0/
GPD6
RING#/PWRFAIL#/
LPC RS T#/GPB 7
SMDAT0/
GPI5
GPB4
SMCLK1/
FA2 1/GPG 5
GPC1
KBRST#/
GPB6
LPC80H L/
LPCPD#/
GPG6
WU I6/G P E 6
LPCRST#/
WU I4/G P D 2
PWM4/
GPA4
KSO9/BUSY GPD4
KSO6/PD6 KSO4/PD4
KSO7/PD7 GPH2 KSO3/PD3 KSO0/PD0
SMDAT1/
GPC2
TMRI0/
WU I2/G P C 4
GPI6
WU I3 /GP C6
CK32KOUT/
GPC5FA11 FD1 FD3FA6 GPC3 FCS#
PWRSW/
FA20 /GPG4
GPE4
LAD3 SERIRQ
LAD2 LFRAME#
LAD0 LA D1
VCC VCC
ECSMI# NC
RI1#/WUI0/
CLKRUN#/
GPD0
WU I7 /GP E7
RI2#/WUI1/
GPD1
PWM0/
GPA0
PWM2/
GPA2
PWM5/
GPA5
GINT/GPD5
GPH0
CLKOUT/
WU I5 /GP E5
GPC0
TMRI1/
GPC7
LPC80LL/
GPG7
ECSCI#/
GPD3
PWM1/
GPA1
PWM3/
GPA3
PWM6/
GPA6
PWM7/
GPA7
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