ISSI IS62LV2568LL User Manual
查询IS62LV2568LL-70H供应商
IS62LV2568LL ISSI
256K x 8 LOW POWER and LOW Vcc
APRIL 2000
CMOS STATIC RAM
®
FEATURES
• Access times of 70 and 85 ns
• CMOS low power operation:
— 120 mW (typical) operating
— 6 µW (typical) standby
• Low data retention voltage: 2V (min.)
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh required
• Single 2.5V to 3.0V power supply
• Available in 32-pin TSOP (Type I), STSOP (Type I),
and 36-pin mini BGA
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The
ISSI
IS62LV2568LL is a low voltage, 262,144 words
by 8 bits, CMOS SRAM. It is fabricated using
voltage, six transistor (6T),
targeted
technologies such as cell phones and pagers.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation
down with CMOS input levels. Additionally, easy memory
expansion is provided by using Chip Enable and Output
Enable inputs, CE and OE. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV2568LL is available in 32-pin TSOP (Type I),
STSOP (Type I), and 36-pin mini BGA.
to satisfy the demands of the state-of-the-art
CMOS technology.
ISS
I’s low
The device
can be reduced
is
A0-A17
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256K x 8
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
1
IS62LV2568LL ISSI
PIN CONFIGURATION
®
36-pin mini BGA (B)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
Vcc
I/O6
I/O7
A9
A1
A2
OE
A10
CE2
WE
NC
NC
CE1
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
Vcc
GND
I/O2
I/O3
A14
PIN DESCRIPTIONS
A0-A17 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
NC No Connection
Vcc Power
GND Ground
32-Pin TSOP (Type I), STSOP (Type I)
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
IS62LV2568LL ISSI
TRUTH TABLE
Mode W E CE1 CE2 OE I/O Operation Vcc Current
Not Selected X H X X High-Z ISB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.5V to 3.0V
Industrial –40°C to +85°C 2.5V to 3.0V
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
VCC Vcc related to GND –0.3 to +4.6 V
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.7 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
05/03/00
3
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