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IS61VPS51232-166TQ
Datasheet
24 pgs190.04 Kb0

ISSI IS61VPS10018-166TQ, IS61VPS10018-166BI, IS61VPS10018-166B, IS61VPS51232-200TQI, IS61VPS51232-200TQ Datasheet

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Integrated Silicon Solution, Inc. — 1-800-379-4774
1
ADVANCE INFORMATION Rev. 00A
05/31/01
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
IS61VPS51232 IS61VPS51236 IS61VPS10018
ISSI
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Linear burst sequence control using MODE input
•
Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Single +2.5V, ±5% operation
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
DESCRIPTION
The ISSI IS61VPS51232, IS61VPS51236, and IS61VPS10018 are high-speed, low-power synchronous static
RAMs
designed to provide burstable,
high-performance memory for communication and networking applications. The
IS61VPS51232
is organized as 524,288 words by 32 bits and the IS61VPS51236 is organized as 524,288 words by 36 bits. The IS61VPS10018 is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge­triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED, SINGLE-CYCLE DESELECT STATIC RAM
ADVANCE INFORMATION
MAY 2001
FAST ACCESS TIME
Symbol Parameter -200 -166 Units
tKQ Clock Access Time 3.1 3.5 ns tKC Cycle Time 5 6 ns
Frequency 200 166 MHz
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
BLOCK DIAGRAM
19/20
BINARY
COUNTER
BWa
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC ADSP
17/18 19/20
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
CE
CE2
CE2
BWb
BWc
512Kx32; 512Kx36;
1024Kx18
MEMORY ARRAY
32, 36,
or 18
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
4
OE
DQa - DQd
32, 36,
or 18
32, 36,
or 18
A19-A0 A18-A0
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
PIN CONFIGURATION
100-Pin TQFP
512K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the address bus.
A2-A18 Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock
DQa-DQd Synchronous Data Input/Output GND Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable VCC +2.5V Power Supply VCCQ Isolated Output Buffer Supply:
+2.5V
ZZ Snooze Enable
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC
A6
A7CECE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
NC DQc1 DQc2
VCCQ
GND DQc3 DQc4 DQc5 DQc6
GND
VCCQ
DQc7 DQc8
NC
VCC
NC
GND DQd1 DQd2
VCCQ
GND DQd3 DQd4 DQd5 DQd6
GND
VCCQ
DQd7 DQd8
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
A18
A17
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
A18
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
TMS
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
TDI
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
A11
TCK
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
TDO
A16
A17
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa
A6
A7CECE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
DQPc
DQc1 DQc2
VCCQ
GND DQc3 DQc4 DQc5 DQc6
GND
VCCQ
DQc7 DQc8
NC
VCC
NC
GND DQd1 DQd2
VCCQ
GND DQd3 DQd4 DQd5 DQd6
GND
VCCQ
DQd7 DQd8
DQPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
A18
A17
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
512K x 36
119-pin PBGA (Top View) 100-Pin TQFP
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the address bus.
A2-A18 Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output
DQPa-DQPd Parity Data Input/Output GND Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable TMS, TDI, JTAG Boundary Scan Pins
TCK, TDO VCC +2.5V Power Supply VCCQ Isolated Output Buffer Supply:
+2.5V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQb1
NC
VCCQ
NC
DQb4
VCCQ
NC
DQb6
VCCQ
DQb8
NC
NC
NC
VCCQ
A6
A19
A7
NC
DQb2
NC
DQb3
NC
VCC
DQb5
NC
DQb7
NC
DQPb
A5
A11
TMS
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A10
TDI
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
TCK
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
NC
A14
TDO
A16
A18
A15
DQPa
NC
DQa7
NC
DQa5
VCC
NC
DQa3
NC
DQa2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQa8
VCCQ
DQa6
NC
VCCQ
DQa4
NC
VCCQ
NC
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
1024K x 18
119-pin PBGA (Top View) 100-Pin TQFP
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the address bus.
A2-A19 Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output
DQPa-DQPb Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8 GND Ground GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable TMS, TDI, JTAG Boundary Scan Pins
TCK, TDO VCC +2.5V Power Supply VCCQ Isolated Output Buffer Supply:
+2.5V ZZ Snooze Enable
A17 NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC
A6
A7CECE2NCNC
BWb
BWa
CE2
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
NC NC NC
VCCQ
GND
NC
NC DQb1 DQb2
GND
VCCQ
DQb3 DQb4
NC
VCC
NC
GND DQb5 DQb6
VCCQ
GND DQb7 DQb8 DQPb
NC
GND
VCCQ
NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
A19
A18
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
TRUTH TABLE
(1-8)
(3CE option)
OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L XXXXL-HHigh-Z Deselect Cycle, Power-Down None L H X L L XXXXL-HHigh-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None XXXHXXXXXX High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L XXXHL-HHigh-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L HHHHLL-H Q Read Cycle, Suspend Burst Current X X X L HHHHHL-HHigh-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X HHHHL-HHigh-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
PARTIAL TRUTH TABLE
Function GW BWE BWa BWb BWc BWd
Read H H XXXX Read H L HHHH Write Byte 1 H L L H H H Write All Bytes H LLLLL Write All Bytes L XXXXX
TRUTH TABLE
(1-8)
(1CE option)
NEXT CYCLE ADDRESS CE ADSP ADSC ADV WRITE OE DQ
Deselected None H X L X X X High-Z Read, Begin External L L X X X L Q Read, Begin External L L X X X H High-Z Write, Begin Current L H L X Write X D Read, Begin External L H L X Read L Q Read, Begin External L H L X Read H High-Z Read, Burst Next X H H L Read L Q Read, Burst Next X H H L Read H High-Z Read, Burst Next H X H L Read L Q Read, Burst Next H X H L Read H High-Z Write, Burst Next X H H L Write X D Write, Burst Next H X H L Write X D Read, Suspend Current X H H H Read L Q Read, Suspend Current X H H H Read H High-Z Read, Suspend Current H X H H Read L Q Read, Suspend Current H X H H Read H High-Z Write, Suspend Current X H H H Write X D Write, Suspend Current H X H H Write X D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPS51232 IS61VPS51236
IS61VPS10018 ISSI
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
1,0
0,1A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C TSTG Storage Temperature –55 to +150 °C PD Power Dissipation 1.6 W IOUT Output Current (per I/O) 100 mA VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.5 V VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 3.2 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma­nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
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