ISSI IS61SP6464-133PQ, IS61SP6464-117TQI, IS61SP6464-117TQ, IS61SP6464-117PQ, IS61SP6464-100TQI Datasheet

®

IS61SP6464

64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM

FEATURES

• Fast access time:
– 133, 117, 100 MHz; 6 ns (83 MHz);

7 ns (75 MHz); 8 ns (66 MHz)

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and
control

• Pentium™ or linear burst sequence control
using MODE input

• Five chip enables for simple depth expansion
and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 128-Pin TQFP 14mm x 20mm
package

• Single +3.3V power supply

• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or VCCQ to alter their power-up state

ISSI

APRIL 2001

DESCRIPTION

The ISSI IS61SP6464 is a high-speed, low-power synchro­nous static RAM designed to provide a burstable, high­performance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 64 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con­trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49­I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input

Q

pins. Subsequent burst addresses can be generated inter­nally by the IS61SP6464 and controlled by the ADV (burst
address advance) input pin.

Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates
after the wake-up period. A LOW input, i.e., GND
pin selects LINEAR Burst. A VCCQ (or no connect) on MODE
pin selects INTERLEAVED Burst.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

Q, on MODE

1

IS61SP6464

BLOCK DIAGRAM

CLK

ADV

ADSC
ADSP

CLK

BINARY

COUNTER

CE

CLR

Q0

Q1

MODE

®

ISSI

A0

A1

A0'

A1'

64K x 64

MEMORY

ARRAY

A15-A0

GW

BWE

BW8

BW1

CE

CE2

CE2

CE3

CE3

16

D

ADDRESS

REGISTER

CE

D

DQ57-DQ64

BYTE WRITE

REGISTERS

D

BYTE WRITE

REGISTERS

D

REGISTER

CE

Q

CLK

Q

CLK

Q

DQ8-DQ1

CLK

Q

ENABLE

CLK

14 16

8

REGISTERS

64

INPUT

CLK

64

OUTPUT

REGISTERS

CLK

OE

64

DATA[64:1]

D

REGISTER

OE

2

Q

ENABLE

DELAY

CLK

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

IS61SP6464

PIN CONFIGURATION

128-Pin TQFP

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

VCCQ

1
2

33

3

34

4

35

5

36

6

37

7

38

8

39

9

40

10

41

11

42

12

43

13
14
15

44

16

45

17

46

18

47

19

48

20

49

21

50

22

51

23

52

24

53

25
26
27

54

28

55

29

56

30

57

31

58

32

59

33

60

34

61

35

62

36

63

37

64

38

GNDQ

VCCQ
GNDQ

VCCQ
GNDQ

VCCQ

CE3

CE2

CE3

CE2

GND

VCCCEBW8

BW7

BW6

BW5OECLK

BWEGWBW4

BW3

GND

VCC

BW2

BW1

ADSC

ADSP

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

39404142434445464748495051525354555657585960616263

ADV

104

GNDQ

103

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

64

VCCQ

32

I/O
I/O

31

I/O

30

I/O

29

I/O

28

I/O

27

I/O

26

I/O

25

I/O

24

I/O

23

I/O

22

GNDQ
VCCQ

21

I/O
I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

GNDQ
VCCQ

11

I/O
I/O

10

I/O

9

I/O

8

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

GNDQ

®

ISSI

A9

A15

GNDQNCMODE

A14

A13

VCC

GND

A12

A11

A10

A8NCA7A6A5A4A3

PIN DESCRIPTIONS

A0-A15 Address Inputs

CLK Clock

ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW8 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE, CE2, CE2, Synchronous Chip Enable

CE3, CE3
OE Output Enable

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

GND

VCCQ

ZZ

A2A1A0

VCC

I/O1-I/O64 Data Input/Output

ZZ Sleep Mode

MODE Burst Sequence Mode

VCC +3.3V Power Supply

GND Ground

VCCQ Isolated Output Buffer Supply:

+3.3V

NC No Connect

GNDQ Isolated Output Buffer Ground

3

IS61SP6464

ISSI

TRUTH TABLE

ADDRESS

OPERATION USED CE3 CE2 CE3 CE2 CE ADSP ADSC ADV WRITE OE CLK I/O

Deselected, Power-down None X X X X H X L X X X L-H High-Z

Deselected, Power-down None L X X X L L XXXXL-HHigh-Z

Deselected, Power-down None X L X X L L XXXXL-HHigh-Z

Deselected, Power-down None X X H X L L XXXXL-HHigh-Z

Deselected, Power-down None X X X H L L XXXXL-HHigh-Z

Deselected, Power-down None L X X X L H L X X X L-H High-Z

Deselected, Power-down None X L X X L H L X X X L-H High-Z

Deselected, Power-down None X X H X L H L X X X L-H High-Z

Deselected, Power-down None X X X H L H L X X X L-H High-Z

Read Cycle, Begin Burst External H H L L L L X X X L L-H Dout

Read Cycle, Begin Burst External H H L L L L X X X H L-H High-Z

Write Cycle, Begin Burst External H H L L L H L X L X L-H Din

Read Cycle, Begin Burst External H H L L L H L X H L L-H Dout

Read Cycle, Begin Burst External H H L L L H L X H H L-H High-Z

Read Cycle, Continue Burst Next X X X X X H H L H L L-H Dout

Read Cycle, Continue Burst Next X X X X X H H L H H L-H High-Z

Read Cycle, Continue Burst Next X X X X H X H L H L L-H Dout

Read Cycle, Continue Burst Next X X X X H X H L H H L-H High-Z

Write Cycle, Continue Burst Next X X X X X H H L L X L-H Din

Write Cycle, Continue Burst Next X X X X H X H L L X L-H Din

Read Cycle, Suspend Burst Current X X X X X HHHHLL-HDout

Read Cycle, Suspend Burst Current X X X X X HHHHHL-HHigh-Z

Read Cycle, Suspend Burst Current X X X X H X H H H L L-H Dout

Read Cycle, Suspend Burst Current X X X X H X HHHHL-HHigh-Z

Write Cycle, Suspend Burst Current X X X X X H H H L X L-H Din

Write Cycle, Suspend Burst Current X X X X H X H H L X L-H Din

Notes:

1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).

2. Wait states are inserted by suspending burst.

3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.

4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.

5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.

®

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

®

IS61SP6464

ISSI

ASYNCHRONOUS TRUTH TABLE

Operation ZZ OE I/O STATUS

Pipelined Read L L Dout
Pipelined Read L H High-Z
Write L L High-Z
Write L H Din

Deselect L X High-Z

Sleep H X High-Z

WRITE TRUTH TABLE

Operation GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1

Read HHXX XXXXXX

Read H LHH HHHHHH

Write all bytes H L L L L L L L L L

Write all bytes L X X X X X X X X X

Write Byte 1 H L H H H H H H H L

Write Byte 2 H L H H H H H H L H

Write Byte 3 H L H H H H H L H H

Write Byte 4 H L H H H H L H H H

Write Byte 5 H L H H H L H H H H

Write Byte 6 H L H H L H H H H H

Write Byte 7 H L H L H H H H H H

Write Byte 8 H L L H H H H H H H

INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

5

IS61SP6464

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

0,1A1’, A0’ = 1,1

1,0

®

ISSI

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.0 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 5.5 V

for Address and Control Inputs

VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

(1)

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V +10%, –5%

Industrial –40°C to +85°C 3.3V +10%, –5%

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01