ISSI IS61SP12832-5TQI, IS61SP12832-5TQ, IS61SP12832-166TQ, IS61SP12832-166B, IS61SP12832-150TQ Datasheet

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

ADVANCE INFORMATION SR038-0D
04/16/99

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and
control

• Pentium™ or linear burst sequence control
using MODE input

• Three chip enables for simple depth expansion
and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and
119-pin PBGA package

• Single +3.3V, +10%, –5% power supply

• Power-down snooze mode

DESCRIPTION

The ISSI IS61SP12832 is a high-speed, low-power synchro­nous static RAM designed to provide a burstable, high­performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 131,072
words by 32 bits, fabricated with ISSI's advanced CMOS
technology. The device integrates a 2-bit burst counter, high­speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1

controls DQa,

BW2

controls DQb,

BW3

controls DQc,

BW4

controls DQd, conditioned by

BWE

being LOW. A LOW

on GW input would cause all bytes to be written.
Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter­nally by the IS61SP12832 and controlled by the

ADV

(burst

address advance) input pin.
The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.

IS61SP12832

128K x 32 SYNCHRONOUS
PIPELINED STATIC RAM

ADVANCE INFORMATION

APRIL 1999

FAST ACCESS TIME

Symbol Parameter -166 -150 -133 -117 -5 Units

tKQ Clock Access Time 3.5 3.8 4 4 5 ns
tKC Cycle Time 6 6.7 7.5 8.5 10 ns

Frenquency 166 150 133 117 100 MHz

ISSI

®

IS61SP12832

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR038-0D

04/16/99

ISSI

®

BLOCK DIAGRAM

17

BINARY

COUNTER

A16-A0

BW1

GW

CLR

CE

CLK

Q0

Q1

MODE

A0’

A0

A1

A1’

CLK

ADV

ADSC
ADSP

15 17

ADDRESS

REGISTER

CE

D

CLK

Q

DQd

BYTE WRITE

REGISTERS

D

CLK

Q

DQc

BYTE WRITE

REGISTERS

D

CLK

Q

DQb

BYTE WRITE

REGISTERS

D

CLK

Q

DQa

BYTE WRITE

REGISTERS

D

CLK

Q

ENABLE

REGISTER

CE

D

CLK

Q

ENABLE

DELAY

REGISTER

D

CLK

Q

BWE

BW4

CE

CE2

CE2

BW2

BW3

128K x 32
MEMORY

ARRAY

32

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

32

OE

4

32

OE

DQ[31:0]

IS61SP12832

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

ADVANCE INFORMATION SR038-0D
04/16/99

ISSI

®

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin TQFP

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.
A2-A16 Synchronous Address Inputs
CLK Synchronous Clock

ADSP

Synchronous Processor Address

Status

ADSC

Synchronous Controller Address

Status

ADV

Synchronous Burst Address Advance

BW1-BW4

Synchronous Byte Write Enable

BWE

Synchronous Byte Write Enable

GW

Synchronous Global Write Enable

CE, CE2

, CE2 Synchronous Chip Enable

OE

Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:

+3.3V
ZZ Snooze Enable
GNDQ Isolated Output Buffer Ground

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

VCCQ

NC

NC

DQc1

DQc2

VCCQ

DQc5

DQc7

VCCQ

DQd1

DQd4

VCCQ

DQd6

DQd8

NC

NC

VCCQ

A6

CE2

A7

NC

DQc3

DQc4

DQc6

DQc8

VCC

DQd2

DQd3

DQd5

DQd7

NC

A5

NC

NC

A4

A3

A2

GND

GND

GND

BW3

GND

NC

GND

BW4

GND

GND

GND

MODE

A10

NC

ADSP

ADSC

VCC

NC

CE

OE

ADV

GW

VCC

CLK

NC

BWE

A1

A0

VCC

A11

NC

A8

A9

A12

GND

GND

GND

BW2

GND

NC

GND

BW1

GND

GND

GND

NC

A14

NC

A16

CE2

A15

NC

DQb6

DQb5

DQb4

DQb2

VCC

DQa7

DQa5

DQa4

DQa3

NC

A13

NC

NC

VCCQ

NC

NC

DQb8

DQb7

VCCQ

DQb3

DQb1

VCCQ

DQa8

DQa6

VCCQ

DQa2

DQa1

NC

ZZ

VCCQ

1 2 3 4 5 6 7

NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCC
DQa2
DQa1
NC

A6

A7CECE2

BW4

BW3

BW2

BW1

CE2

VCC

GND

CLK

GW

BWE

OE

ADSC



ADSPADV

A8

A9

NC
DQc1
DQc2

VCCQ

GND
DQc3
DQc4
DQc5
DQc6

GND

VCCQ

DQc7
DQc8

NC

VCC

NC

GND
DQd1
DQd2

VCCQ

GND
DQd3
DQd4
DQd5
DQd6

GND

VCCQ

DQd7
DQd8

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

A5A4A3A2A1

A0

NC

NC

GND

VCC

NC

NC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

IS61SP12832

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION SR038-0D

04/16/99

ISSI

®

TRUTH TABLE

Address

Operation Used

CECE

CECE

CE

CE2

CE2CE2

CE2CE2

CE2

ADSPADSP

ADSPADSP

ADSP

ADSCADSC

ADSCADSC

ADSC

ADVADV

ADVADV

ADV

WRITEWRITE

WRITEWRITE

WRITE

OEOE

OEOE

OE

DQ

Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None X X H H L X X X High-Z
Deselected, Power-down None X 0 X H L X X X High-Z
Read Cycle, Begin Burst External L H L L XXXXHigh-Z
Read Cycle, Begin Burst External L H L H 0 X Read X High-Z
Write Cycle, Begin Burst External L H L H L X Write X High-Z
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X High-Z
Write Cycle, Continue Burst Next H X X X H L Write X High-Z
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X High-Z
Write Cycle, Suspend Burst Current H X X X H H Write X High-Z

PARTIAL TRUTH TABLE

Function

GWGW

GWGW

GW

BWEBWE

BWEBWE

BWE

BW1BW1

BW1BW1

BW1

BW2BW2

BW2BW2

BW2

BW3BW3

BW3BW3

BW3

BW4BW4

BW4BW4

BW4

Read H H X X X X
Read H L H H H H
Write Byte 1 H L L H H H
Write All Bytes H LLLLL
Write All Bytes L XXXXX

IS61SP12832

Integrated Silicon Solution, Inc. — 1-800-379-4774

5

ADVANCE INFORMATION SR038-0D
04/16/99

ISSI

®

INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

1,0

0,1A1', A0' = 1,1

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V

for Address and Control Inputs

VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.