ISSI IS61SF51218D-8B, IS61SF51218D-8.5TQI, IS61SF51218D-8.5TQ, IS61SF51218D-10B, IS61SF25636T-9TQI Datasheet
...
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D
ISSI
®
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
•
Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O for SF
• 2.5V I/O for LF
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
PRELIMINARY INFORMATION
NOVEMBER 2000
FAST ACCESS TIME
Symbol Parameter -8* -8.5 -9 -10 Units
tKQ Clock Access Time 8 8.5 9 10 ns
tKC Cycle Time 10 11 15 15 ns
Frequency 100 90 66 66 MHz
*This speed available only in SF version
DESCRIPTION
The
ISSI
IS61SF25632, IS61SF25636, IS61SF51218,
IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, secondary cache for the
Pentium™, 680X0™, and PowerPC™ microprocessors.
The IS61SF25632 and IS61LF25632 are organized as
262,144 words by 32 bits and the IS61SF25636 and
IS61LF25636 are organized as 262,144 words by 36 bits.
The IS61SF51218 and IS61LF51218 are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers that are controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D ISSI
®
BLOCK DIAGRAM
BINARY
COUNTER
BWa
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
16/17
18/19
ADDRESS
REGISTER
CE
D
CLK
Q
DQd
BYTE WRITE
REGISTERS
D
CLK
Q
DQc
BYTE WRITE
REGISTERS
D
CLK
Q
DQb
BYTE WRITE
REGISTERS
D
CLK
Q
DQa
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BWd
CE (T,D)
CE2 (T)
CE2 (T,D)
BWb
BWc
256K x 32; 256K x 36;
512K x 18
MEMORY ARRAY
INPUT
REGISTERS
CLK
32, 36,
or 18
OE
4
OE
DQa - DQd
18/19
A17-A0
(61SF25632/36,
61LF25632/36)
A18-A0
(61SF51218,
61LF51218)
(x32/x36)
(x32/x36/x18)
(x32/x36)
(x32/x36/x18)
32, 36,
or 18
32, 36,
or 18
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D ISSI
®
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7
VCCQ A6 A4 ADSP A8 A16 VCCQ
NC CE2 A3 ADSC A9 A17 NC
NC A7 A2 VCC A12 A15 NC
DQc1 NC GND NC GND NC DQb8
DQc2 DQc3 GND CE GND DQb6 DQb7
VCCQ DQc4 GND OE GND DQb5 VCCQ
DQc5 DQc6 BWc ADV BWb DQb4 DQb3
DQc7 DQc8 GND GW GND DQb2 Dqb1
VCCQ VCC NC VCC NC VCC VCCQ
DQd1 DQd2 GND CLK GND DQa7 DQa8
DQd4 DQd3 BWd NC BWa DQa5 DQa6
VCCQ DQd5 GND BWE GND DQa4 VCCQ
DQd6 DQd7 GND A1 GND DQa3 DQa2
DQd8 NC GND A0 GND NC DQa1
NC A 5 M ODE VC C GND A 13 NC
NC NC A10 A11 A14 NC ZZ
VCCQ NC NC NC NC NC VCCQ
256K x 32
119-pin PBGA (Top View) 100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6A7CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D ISSI
®
PIN CONFIGURATION
256K x 32
100-Pin TQFP (T Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6A7CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D ISSI
®
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7
VCCQ A6 A4 ADSP A8 A16 VCCQ
NC CE2 A3 ADSC A9 A17 NC
NC A7 A2 VCC A12 A15 NC
DQc1 DQPc GND NC GND DQPb DQb8
DQc2 DQc3 GND CE GND DQb6 DQb7
VCCQ DQc4 GND OE GND DQb5 VCCQ
DQc5 DQc6 BWc ADV BWb DQb4 DQb3
DQc7 DQc8 GND GW GND DQb2 Dqb1
VCCQ VCC NC VCC NC VCC VCCQ
DQd1 DQd2 GND CLK GND DQa7 DQa8
DQd4 DQd3 BWd NC BWa DQa5 DQa6
VCCQ DQd5 GND BWE GND DQa4 VCCQ
DQd6 DQd7 GND A1 GND DQa3 DQa2
DQd8 DQPd GND A 0 GND DQPa DQa1
NC A 5 M ODE VCC G ND A1 3 NC
NC NC A10 A11 A14 NC ZZ
VCCQ NC NC NC NC NC VCCQ
256K x 36
119-pin PBGA (Top View) 100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
A6A7CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D ISSI
®
PIN CONFIGURATION
256K x 36
100-Pin TQFP (T Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPd Parity Data I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
A6A7CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
PRELIMINARY INFORMATION Rev. 00A
04/17/01
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D ISSI
®
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7CECE2NCNC
BWb
BWa
A18
VCC
GND
CLK
GW
BWEOEADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
GND
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQb1
NC
VCCQ
NC
DQb4
VCCQ
NC
DQb6
VCCQ
DQb8
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQb2
NC
DQb3
NC
VCC
DQb5
NC
DQb7
NC
DQPb
A5
A11
NC
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BWa
GND
GND
GND
GND
A14
NC
A16
CE2
A15
DQPa
NC
DQa7
NC
DQa5
VCC
NC
DQa3
NC
DQa2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQa8
VCCQ
DQa6
NC
VCCQ
DQa4
NC
VCCQ
NC
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
512K x 18
119-pin PBGA (Top View) 100-Pin TQFP (D Version)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BWa-BWb Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQb Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply: 3.3V or 2.5V
ZZ Snooze Enable
DQPa-DQPb Parity Data I/O DQPa is parity for
DQa1-a8; DQPb is parity for DQb1-b8
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