ISSI IS61SF25618-10TQ, IS61SF25618-10B, IS61SF25616-8TQ, IS61SF25616-8.5TQ, IS61SF25616-8.5B Datasheet

IS61SF25616

IS61SF25618 ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. A

04/17/01

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

FEATURES

• Fast access times: 8 ns, 8.5 ns, 10 ns, and 12 ns

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data inputs
and control signals

• Pentium

TM

or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion
and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and
119-pin PBGA package

• Single +3.3V +10%, –5% power supply

• Power-down snooze mode

256K x 16, 256K x 18 SYNCHRONOUS
FLOW-THROUGH STATIC RAM

APRIL 2001

FAST ACCESS TIME

Symbol Parameter 8 8.5 10 12 Units

tKQ Clock Access Time 8 8.5 10 12 ns
tKC Cycle Time 10 11 15 15 ns

Frequency 100 90 66 66 MHz

DESCRIPTION

The ISSI IS61SF25616 and IS61SF25618 is a high-speed,
low-power synchronous static RAM designed to provide
a burstable, high-performance memory for high speed
networking and communication applications. It is organized
as 262,144 words by 16 bits and 18 bits, fabricated with

ISSI's advanced CMOS technology. The device integrates

a 2-bit burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.

Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by BWE being LOW. A LOW on GW input would cause all
bytes to be written.

Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61SF25616 and controlled by the ADV
(burst address advance) input pin.

The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.

IS61SF25616

IS61SF25618 ISSI

®

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

BLOCK DIAGRAM

BURST

COUNTER

A2-A17

A1
A0

GW

MODE

ADSC

ADSP

ADDRESS

REGISTER

BW1

BYTE WRITE

REGISTER

BW2

BYTE WRITE

REGISTER

ENABLE

REGISTER

ENABLE

REGISTER

BWE

BW1

BW2

256K x 16, 256K x 18

MEMORY ARRAY

16

or

18

DATA INPUT

REGISTER

CLK

16

or

18

2

ADV

CLK

2 18

18

16

2

CLK2

CLK2

CLK

OE

CE1

CE2

CE2

CLR

DQ1-DQ16

or

DQ1-DQ18

IS61SF25616

IS61SF25618 ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. A

04/17/01

PIN CONFIGURATION

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the
address bus.

A2-A17 Synchronous Address Inputs

CLK Synchronous Clock
ADSP Synchronous Processor Address

Status

ADSC Synchronous Controller Address

Status

ADV Synchronous Burst Address Advance
BW1-BW2 Synchronous Byte Write Enable

BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable

DQ1-DQ16 Synchronous Data Input/Output

MODE Burst Sequence Mode Selection

VCC +3.3V Power Supply

GND Ground

VCCQ Isolated Output Buffer Supply: +3.3V

ZZ Snooze Enable

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

VCCQ

NC

NC

DQ9

NC

VCCQ

NC

DQ12

VCCQ

NC

DQ14

VCCQ

DQ16

NC

NC

NC

VCCQ

A6

CE2

A7

NC

DQ10

NC

DQ11

NC

VCC

DQ13

NC

DQ15

NC

NC

A5

A11

NC

A4

A3

A2

GND

GND

GND

BW2

GND

NC

GND

GND

GND

GND

GND

MODE

A10

NC

ADSP

ADSC

VCC

NC

CE

OE

ADV

GW

VCC

CLK

NC

BWE

A1

A0

VCC

NC

NC

A8

A9

A12

GND

GND

GND

GND

GND

NC

GND

BW1

GND

GND

GND

GND

A14

NC

A16

CE2

A15

NC

NC

DQ7

NC

DQ5

VCC

NC

DQ3

NC

DQ2

NC

A13

A17

NC

VCCQ

NC

NC

NC

DQ8

VCCQ

DQ6

NC

VCCQ

DQ4

NC

VCCQ

NC

DQ1

NC

ZZ

VCCQ

1 2 3 4 5 6 7

A17
NC
NC
VCCQ
GND
NC
NC
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC

A6

A7CECE2NCNC

BW2

BW1

CE2

VCC

GND

CLK

GW

BWEOEADSC

ADSP

ADV

A8

A9

NC
NC
NC

VCCQ

GND

NC
NC

DQ9

DQ10

GND

VCCQ

DQ11
DQ12

GND

VCC

NC

GND
DQ13
DQ14

VCCQ

GND
DQ15
DQ16

NC
NC

GND

VCCQ

NC
NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

A5A4A3A2A1

A0

NC

NC

GND

VCC

NC

NC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

256K x 16

119-pin PBGA (Top View) 100-Pin TQFP

IS61SF25616

IS61SF25618 ISSI

®

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the
address bus.

A2-A17 Synchronous Address Inputs

CLK Synchronous Clock
ADSP Synchronous Processor Address

Status

ADSC Synchronous Controller Address

Status

ADV Synchronous Burst Address Advance
BW1-BW2 Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable

GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable

DQ1-DQ16 Synchronous Data Input/Output

MODE Burst Sequence Mode Selection

VCC +3.3V Power Supply

GND Ground

VCCQ Isolated Output Buffer Supply: 3.3V

ZZ Snooze Enable

DQP1-DQP2 Parity Data I/O DQP1 is parity for

DQ1-8; DQP2 is parity for DQ9-16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

VCCQ

NC

NC

DQ9

NC

VCCQ

NC

DQ12

VCCQ

NC

DQ14

VCCQ

DQ16

NC

NC

NC

VCCQ

A6

CE2

A7

NC

DQ10

NC

DQ11

NC

VCC

DQ13

NC

DQ15

NC

DQP2

A5

A11

NC

A4

A3

A2

GND

GND

GND

BW2

GND

NC

GND

GND

GND

GND

GND

MODE

A10

NC

ADSP

ADSC

VCC

NC

CE

OE

ADV

GW

VCC

CLK

NC

BWE

A1

A0

VCC

NC

NC

A8

A9

A12

GND

GND

GND

GND

GND

NC

GND

BW1

GND

GND

GND

GND

A14

NC

A16

CE2

A15

DQP1

NC

DQ7

NC

DQ5

VCC

NC

DQ3

NC

DQ2

NC

A13

A17

NC

VCCQ

NC

NC

NC

DQ8

VCCQ

DQ6

NC

VCCQ

DQ4

NC

VCCQ

NC

DQ1

NC

ZZ

VCCQ

1 2 3 4 5 6 7

A17
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC

A6

A7CECE2NCNC

BW2

BW1

CE2

VCC

GND

CLK

GW

BWEOEADSC

ADSP

ADV

A8

A9

NC
NC
NC

VCCQ

GND

NC
NC

DQ9

DQ10

GND

VCCQ

DQ11
DQ12

GND

VCC

NC

GND
DQ13
DQ14

VCCQ

GND
DQ15
DQ16

DQP2

NC

GND

VCCQ

NC
NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

A5A4A3A2A1

A0

NC

NC

GND

VCC

NC

NC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

256K x 18

119-pin PBGA (Top View) 100-Pin TQFP

IS61SF25616

IS61SF25618 ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774

5

Rev. A

04/17/01

TRUTH TABLE

Address

Operation Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ

Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L X X X X High-Z
Deselected, Power-down None L L X L X X X X High-Z
Deselected, Power-down None X X H H L X X X High-Z
Deselected, Power-down None X L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X X Q
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D

PARTIAL TRUTH TABLE

Function GW BWE BW1 BW2

Read H H X X
Read H L H H
Write Byte 1 H L L H
Write All Bytes H L L L
Write All Bytes L X X X