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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
256K x 36 and 512K x 18
9Mb, PIPELINE 'NO WAIT' STATE BUS
SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119ball PBGA packages
• Power supply:
NVP: V
NLP: V
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
DD 2.5V (± 5%), VDDQ 2.5V (± 5%)
DD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
DESCRIPTION
The 9 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
®
ISSI
MAY 2005
FAST ACCESS TIME
Symbol Parameter -250 -200 Units
tKQ Clock Access Time 2.6 3.1 ns
tKC Cycle Time 4 5 n s
Frequency 250 200 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
1
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
BLOCK DIAGRAM
®
x 36: A [0:17] or
x 18: A [0:18]
CLK
CKE
CE
CE2
CE2
ADV
WE
BW
Ÿ
X
(X=a,b,c,d or a,b)
OE
ZZ
CONTROL
LOGIC
}
ADDRESS
REGISTER
K
CONTROL
REGISTER
DQx/DQPx
A2-A17 or A2-A18
MODE
A0-A1 A'0-A'1
WRITE
ADDRESS
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
36 or 18
256Kx36;
512Kx18
MEMORY ARRAY
K
DATA-IN
REGISTER
K
DATA-IN
REGISTER
K
OUTPUT
REGISTER
BUFFER
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Bottom View
119-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 7 x 17 Ball Array
®
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
3
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
PIN CONFIGURATION — 256K X 36, 165-Ball PBGA (TOP VIEW)
1234567891011
ANC A CE BWc BWb CE2 CKE ADV A A NC
B N C A CE2 BWd BWa CLK WE OE NC A NC
C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
HNC NC NC VDD VSS VSS VSS VDD NC NC ZZ
J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
N DQPd NC VDDQ VSS NC NC NC VSS VDDQ NC DQPa
®
P N C NC A A TDI A1* TDO A A A NC
R MODE NC A A TMS A0* TCK A A A A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CL K Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d) Synchronous Byte Write Inputs
MODE Burst Sequence Selection
TCK, TDI JTAG Pins
TDO, TMS
VDD 3.3V/2.5V Power Supply
N C No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ Isolated output Power Supply
3.3V/2.5V
VSS Ground
OE Output Enable
ZZ Power Sleep Mode
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
119-PIN PBGA PACKAGE CONFIGURATION 256K x 36 (TOP VIEW)
1234567
®
A
B
C
D
E
F
G
H
M
N
P
R
V
DDQ
NC
NC
A
CE2
A
DQc DQPc Vss
DQc DQc Vss
V
DDQ
DQc
DQc DQc
DQc DQc
J
K
L
V
DDQ
V
DD
DQd DQd
DQd DQd
V
DDQ
DQd
DQd DQd
DQd
NC
T
NC
DQPd
A
NC
A
A
A
V
SS
SS
V
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
NC
ADV
DD
V
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
A
A
A
A
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
DDQ
V
DQa
DQa
DDQ
V
DQa
DQa
NCA
ZZ
U
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
V
DDQ
TMS TDI
TCK
TDO
NC
V
DDQ
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CL K Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE 2 Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
VDD Power Supply
VSS Ground
N C No Connect
DQa-DQd Data Inputs/Outputs
DQPa-Pd Parity Data I/O
VDDQ Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
5
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
165-PIN PBGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
1234567891011
®
A
BNC
CNC
DNC
ENC
F
GNC
HNC
J
K
L
M DQb NC Vss
N DQPb
PNC
R MODE
NC
NC DQb NC
DQb
DQb
DQb
A
A
NC Vss
DQb
DQb
CE
CE2
V
DDQ
VDDQ
VDDQ
VDDQ
DQb
NC
NC
NC
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
VDDQ
A
A
BWb
NC
V
V
V
V
V
V
DD
V
DD
V
V
Vss
DD
DD
DD
DD
DD
DD
DD
A
A
NC
BWa
Vss
CE2
CLK
Vss
Vss Vss NC
Vss Vss Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
1
* TDO
A
0
*
CKE
WE
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TCK
ADV
OE
Vss
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
Vss
A
A
V
V
V
V
V
NC
V
V
V
V
V
A
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CL K Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDI JTAG Pins
TDO, TMS
VDD 3.3V/2.5V Power Supply
N C No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ Isolated output Power Supply
3.3V/2.5V
VSS Ground
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
119-PIN PBGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
1234567
®
A
B
C
D
E
F
G
H
M
N
P
R
V
DDQ
NC
NC
DQb Vss
NC
V
DDQ
NC
DQb
J
K
L
V
DDQ
NC
DQb
V
DDQ
A
CE2
A
NC
DQb Vss
NC
DQb
NC
V
DD
DQb
NC
DQb
DQb NC
NC
NC
T
NC
DQPb
A
A
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
MODE
A
NC
ADV
V
DD
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
1
*
A
0
*
A
V
DD
NC
A
A
A
Vss
NC
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
A
CE2
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
DDQ
V
DQa
NC
DDQ
V
NC
DQa
NCA
ZZ
U
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
V
DDQ
TMS TDI
TCK
TDO
NC
V
DDQ
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CL K Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE 2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
VDD Power Supply
VSS Ground
N C No Connect
DQa-DQb Data Inputs/Outputs
DQPa-Pb Parity Data I/O
VDDQ Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
7
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
PIN CONFIGURATION
100-Pin TQFP
A ACE
CE2
BWd
BWc
BWb
BWa
CE2
VDDVss
DQPc
DQc
DQc
DDQ
V
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
V
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
CLKWECKEOEADVNCAAA
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
DD
15
16
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AAA
MODE
A
A1
A0
NC
NC
Vss
DD
NC
NC
V
AAAAAAA
80
DQPb
79
DQb
78
DQb
77
V
DDQ
76
Vss
75
DQb
74
DQb
73
DQb
72
DQb
71
Vss
70
DDQ
V
69
DQb
68
DQb
67
Vss
66
NC
65
V
DD
ZZ
64
DQa
63
DQa
62
61
V
DDQ
60
Vss
59
DQa
58
DQa
57
DQa
56
DQa
Vss
55
V
DDQ
54
53
DQa
DQa
52
DQPa
51
V
DDQ
Vss
DQb
DQb
Vss
DDQ
V
DQb
DQb
V
Vss
DQb
DQb
DDQ
V
Vss
DQb
DQb
DQPb
Vss
DDQ
V
NC
NC
NC
NC
NC
NC
DD
NC
NC
NC
NC
NC
AACE
CE2NCNC
BWbBWaCE2
VDDVss
CLKWECKEOEADVNCAAA
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
AAA
A
A1
A0
NC
NC
Vss
DD
NC
NC
V
AAAAAAA
80
A
79
NC
78
NC
77
DDQ
V
76
Vss
75
NC
74
DQPa
73
DQa
72
DQa
71
Vss
70
DDQ
V
69
DQa
68
DQa
67
Vss
66
NC
65
DD
V
ZZ
64
DQa
63
DQa
62
61
DDQ
V
60
Vss
59
DQa
58
DQa
57
NC
56
NC
55
Vss
54
DDQ
V
53
NC
NC
52
NC
51
®
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CL K Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
Vss Ground for Core
N C Not Connected
8
Integrated Silicon Solution, Inc. — www.issi.com —
512K x 18
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
DQPa-DQPd Parity Data I/O
MODE Burst Sequence Selection
VDD +3.3V/2.5V Power Supply
VSS Ground for output Buffer
VDDQ
ZZ Snooze Enable
Isolated Output Buffer Supply: +3.3V/2.5V
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
STATE DIAGRAM
READ
®
READ
READ
BURST
BEGIN
READ
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE
WRITE
READ WRITE
DESELECT
DS
DS
WRITE
(1)
DSDS
BURST
DS
READ
BEGIN
WRITE
BURST
BURST
WRITE
WRITE
WRITE
BURST
Address
Operation Used
CECE
CE CE2
CECE
CECE
CE2 ADV
CECE
WEWE
WE
WEWE
BWBW
BWx
BWBW
OEOE
OE
OEOE
CKECKE
CKE CLK
CKECKE
Not Selected N/A H X X L X X X L ↑
Not Selected N/A X L X L X X X L ↑
Not Selected N/A X X H L X X X L ↑
Not Selected Continue N/A X X X H X X X L ↑
Begin Burst Read External Address L H L L H X L L ↑
Continue Burst Read Next Address X X X H X X L L ↑
NOP/Dummy Read External Address L H L L H X H L ↑
Dummy Read Next Address X X X H X X H L ↑
Begin Burst Write External Address L H LLLLXL↑
Continue Burst Write Next Address X X X H X L X L ↑
NOP/Write Abort N/A L H L L L H X L ↑
Write Abort Next Address X X X H X H X L ↑
Ignore Clock Current Address X X X X X X X H ↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
9
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
®
ASYNCHRONOUS TRUTH TABLE
Operation ZZ
(1)
OEOE
OE I/O STATUS
OEOE
Sleep Mode H X High-Z
Read
LL DQ
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WEWE
WE
WEWE
READ H X X
WRITE BYTE a L L H
WRITE BYTE b L H L
WRITE ALL BYTEs L L L
WRITE ABORT/NOP L H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
BWBW
BWa
BWBW
BWBW
BWb
BWBW
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
WRITE TRUTH TABLE (x36)
®
Operation
READ H X X X X
WRITE BYTE a L L H H H
WRITE BYTE b L H L H H
WRITE BYTE c L H H L H
WRITE BYTE d L H H H L
WRITE ALL BYTEs L L L L L
WRITE ABORT/NOP L H H H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WEWE
WE
WEWE
BWBW
BWa
BWBW
BWBW
BWb
BWBW
BWBW
BWc
BWBW
BWBW
BWd
BWBW
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
11
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
0,1A1', A0' = 1,1
1,0
®
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TSTG Storage Temperature –65 to +150 ° C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 10 0 mA
VIN, VOUT Voltage Relative to VSS for I/O Pins –0.5 to VDDQ + 0.3 V
VIN Voltage Relative to VSS for –0.3 to 4.6 V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,
precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.
This device contains circuitry that will ensure the output devices are in High-Z at power up.
3.
(1)
OPERATING RANGE (IS61NLPx)
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 3.3V ± 5% 3.3V / 2.5V ± 5%
Industrial -40°C to +85°C 3.3V ± 5% 3.3V / 2.5V ± 5%
OPERATING RANGE (IS61NVPx)
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 2.5V ± 5% 2.5V ± 5%
Industrial -40°C to +85°C 2.5V ± 5% 2.5V ± 5%
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V 2.5V
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
V
OH Output HIGH Voltage IOH = –4.0 mA (3.3V) 2.4 — 2.0 — V
IOH = –1.0 mA (2.5V)
VOL Output LOW Voltage IOL = 8.0 mA (3.3V) — 0.4 — 0.4 V
IOL = 1.0 mA (2.5V)
VIH Input HIGH Voltage 2.0 VDD + 0.3 1.7 VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.8 –0.3 0.7 V
ILI Input Leakage Current VSS ≤ VIN ≤ VDD
ILO Output Leakage Current VSS ≤ VOUT ≤ VDDQ, OE = VIH –5 5 –5 5 µA
(1)
–5 5 –5 5 µA
®
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-250 -200
MAX MAX
Symbol Parameter Test Conditions
Temp. range x18 x36 x18 x36 Uni
t
ICC AC Operating Device Selected, Com. 280 280 270 270 mA
Supply Current OE = VIH, ZZ ≤ VIL, Ind. 300 300 280 280
All Inputs ≤ 0.2V or ≥ VDD – 0.2V,
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 100 100 100 100 mA
TTL Input VDD = Max., Ind. 100 100 100 100
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
ISBI Standby Current Device Deselected, Com. 70 70 70 70 mA
CMOS Input VDD = Max., Ind. 80 80 80 80
VIN ≤ VSS + 0.2V or ≥VDD – 0.2V
f = 0
ISB2 Sleep Mode ZZ>VIH Com. 45 45 45 45 mA
Ind. 50 50 50 50
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
SS + 0.2V or ≥ VDD – 0.2V.
V
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
®
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
Zo= 50Ω
OUTPUT
50Ω
1.5V
Figure 1
+3.3V
OUTPUT
351 Ω
317 Ω
5 pF
Including
jig and
scope
Figure 2
14
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
ZO = 50Ω
OUTPUT
50Ω
1.25V
+2.5V
OUTPUT
1,538 Ω
5 pF
Including
jig and
scope
®
Figure 3
Figure 4
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-250 -200
Symbol Parameter Min. Max. Min. Max. Unit
fmax Clock Frequency — 25 0 — 20 0 MHz
tKC Cycle Time 4.0 — 5 — ns
tKH Clock High Time 1 .7 — 2 — ns
tKL Clock Low Time 1.7 — 2 — ns
tKQ Clock Access Time — 2.6 — 3.1 ns
(2)
tKQX
tKQLZ
tKQHZ
(2,3)
(2,3)
Clock High to Output Invalid 0.8 — 1.5 — ns
Clock High to Output Low-Z 0. 8 — 1 — ns
Clock High to Output High-Z — 2. 6 — 3.1 ns
tOEQ Output Enable to Output Valid — 2.6 — 3.1 ns
(2,3)
tOELZ
tOEHZ
(2,3)
Output Enable to Output Low-Z 0 — 0 — ns
Output Disable to Output High-Z — 2.6 — 3.0 ns
tAS Address Setup Time 1.2 — 1.4 — ns
tWS Read/Write Setup Time 1.2 — 1.4 — ns
tCES Chip Enable Setup Time 1. 2 — 1.4 — ns
tSE Clock Enable Setup Time 1.2 — 1.4 — ns
tADVS Address Advance Setup Time 1.2 — 1.4 — ns
tDS Data Setup Time 1.2 — 1.4 — ns
tAH Address Hold Time 0.3 — 0.4 — ns
tHE Clock Enable Hold Time 0.3 — 0.4 — ns
tWH Write Hold Time 0 .3 — 0.4 — ns
tCEH Chip Enable Hold Time 0.3 — 0.4 — ns
tADVH Address Advance Hold Time 0.3 — 0.4 — ns
tDH Data Hold Time 0.3 — 0.4 — ns
tPDS ZZ High to Power Down — 2 — 2 cyc
tPUS ZZ Low to Power Down — 2 — 2 cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
16
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
ISB2 Current during SLEEP MODE ZZ ≥ VIH 60 mA
tPDS ZZ active to input ignored 2 cycle
tPUS ZZ inactive to input sampled 2 cycle
tZZI ZZ active to SLEEP current 2 cycle
tRZZI ZZ inactive to exit SLEEP current 0 ns
SLEEP MODE TIMING
CLK
t
ZZ
PDS
ZZ setup cycle ZZ recovery cycle
t
ZZI
t
PUS
®
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
Deselect or Read Only
High-Z
RZZI
t
Deselect or Read Only
Normal
operation
cycle
Don't Care
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
READ CYCLE TIMING
t
KH
t
KL
CLK
t
KC
A3
ADV
Address
WRITE
CKE
t
ADVS
t
t
t
WS
CES
t
ADVH
AS
t
AH
A1
t
t
WH
CEH
A2
t
SE
t
HE
®
CE
OE
Data Out
t
t
OEQ
t
OEHZ
t
OEHZ
Q1-1
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
KQ
t
DS
Q3-3 Q3-4Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
t
KQHZ
Don't Care
Undefined
18
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
WRITE CYCLE TIMING
t
KL
t
KH
CLK
t
KC
ADV
®
Address
WRITE
CKE
CE
OE
Data In
Data Out
A1
t
SE
t
HE
Q0-3 Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
t
OEHZ
A2
A3
t
DS
t
DH
D3-3 D3-4D3-2D3-1D2-4D2-3D2-2D2-1D1-1
Don't Care
Undefined
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
SINGLE READ/WRITE CYCLE TIMING
tKH t
KL
CLK
tSE t
HE
CKE
t
KC
®
Address
WRITE
CE
ADV
OE
Data Out
Data In
A1 A2 A3 A4 A5 A6 A7 A8 A9
t
OEQ
t
OELZ
Q1 Q3 Q4 Q6 Q7
t
DS
t
DH
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
Don't Care
Undefined
20
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
CKE CKE
CKE OPERATION TIMING
CKE CKE
tKH t
KL
CLK
tSE t
HE
CKE
t
KC
®
Address
A1 A2 A3 A4 A5 A6
WRITE
CE
ADV
OE
t
KQ
t
Data Out
KQLZ
Q1 Q3 Q4
Data In
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
t
KQHZ
t
DS
t
DH
D2
Don't Care
Undefined
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
CECE
CE OPERATION TIMING
CECE
tKH t
KL
CLK
tSE t
HE
CKE
t
KC
®
Address
WRITE
CE
ADV
OE
Data Out
Data In
A1 A2 A3 A4 A5
t
t
OEQ
OELZ
t
KQHZ
Q1 Q2 Q4
t
DS
t
DH
D3
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
t
t
KQLZ
KQ
D5
Don't Care
Undefined
22
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
®
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61NLP and IS61NVP have a serial boundary scan
Test Access Port (TAP) in the PBGA package only. (Not
available in TQFP package.) This port operates in accordance with
include all functions required for full 1149.1 compliance.
These functions from the
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
IEEE
Standard 1149.1-1900, but does not
IEEE specification
are excluded
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (VSS) to
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left disconnected. On power-up, the device will start in a
reset state which will not interfere with the device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2 1 0
Instruction Register
Selection Circuitry Selection Circuitry TDOTDI
31 30 29
Identification Register
x
TCK
. . . . .
Boundary Scan
. . .
Register*
2 1 0
2 1 0
TMS
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TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB) of
any register.
TAP
state machine (see
TAP
Controller State
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the
TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the
Block Diagram) At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with
the IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
TDI
and
TDO
pins. (See
TAP
Controller
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the
SRAM
with minimal delay. The bypass register
is set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the
to the
Shift-DR
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
SRAM
. Several no connect
TDI
and
TDO
pins when the controller is moved
state. The EXTEST, SAMPLE/PRELOAD
(NC)
pins are
Scan Register Sizes
Register Bit Size Bit Size
Name (x18) (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan 75 75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
®
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field Description 256K x 36 512K x 18
Revision Number (31:28) Reserved for version number. xxxx xxxx
Device Depth (27:23) Defines depth of SRAM. 256K or 512K 00111 01000
Device Width (22:18) Defines width of the SRAM. x36 or x18 00100 00011
ISSI Device ID (17:12) Reserved for future use. xxxxx xxxxx
ISSI JEDEC ID (11:1) Allows unique identification of SRAM vendor. 00011010101 00011010101
ID Register Presence (0) Indicate the presence of an ID register. 1 1
24
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®
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the
buffers. The
mands
SAMPLE/PRELOAD
Inputs and Output
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.
SRAM
EXTEST
does not implement the
or
INTEST
; instead it performs a capture of the
ring when these instructions are executed.
or the
PRELOAD
RESERVED
Input
or
1149.1
portion of
Output
com-
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the
EXTEST places the SRAM outputs in a High-Z state.
SAMPLE/PRELOAD
instruction,
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster.
Because of the clock frequency differences, it is possible
that during the Capture-DR state, an input or output will
under-go a transition. The TAP may attempt a signal
capture while in transition (metastable state). The device
will not be harmed, but there is no guarantee of the value
that will be captured or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be
stabilized long enough to meet the TAP controller’s
capture set-up plus hold times (tCS and tCH). To insure that
the SRAM clock input is captured correctly, designs need
a way to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is not an issue, it is possible
to capture all other signals and simply ignore the value of
the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the
implemented, putting the
state while performing a
will have the same effect as the Pause-DR command.
PRELOAD
TAP
into the
SAMPLE/PRELOAD
part of the command is not
Update
to the
Update-DR
instruction
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
INSTRUCTION CODES
Code Instruction Description
00 0 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between
the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001 IDCODE Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
01 1 RESERVED Do Not Use: This instruction is reserved for future use.
®
100
10 1 RESERVED Do Not Use: This instruction is reserved for future use.
11 0 RESERVED Do Not Use: This instruction is reserved for future use.
111 BYPASS Places the bypass register between TDI and TDO. This operation does not
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation. This instruction does not
1149.1 preload function and is therefore not 1149.1 compliant.
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
10
Run Test/Idle
11 1
Select DR
00
11
Capture DR
0
Shift DR
0
1
Exit1 DR
11
0
Select IR
0
Capture IR
0
Shift IR
1
Exit1 IR
0
0
implement
26
Pause DR
Exit2 DR
0
1
Update DR
0
0
Pause IR
0
1
Update IR
11
Exit2 IR
11
0
0
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IS61NLP51218A/IS61NVP51218A ISSI
®
TAP Electrical Characteristics Over the Operating Range
(1,2)
Symbol Parameter Test Conditions Min. Max. Units
VOH1 Output HIGH Voltage IOH = –2.0 mA 1.7 — V
VOH2 Output HIGH Voltage IOH = –100 µA 2.1 — V
VOL1 Output LOW Voltage IOL = 2.0 mA — 0.7 V
VOL2 Output LOW Voltage IOL = 100 µA — 0.2 V
VIH Input HIGH Voltage 1.7 VDD +0.3 V
VIL Input LOW Voltage –0. 3 0.7 V
IX Input Leakage Current VSS ≤ V I ≤ VDDQ –10 10
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: V
Undershoot: VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: V
TAP AC ELECTRICAL CHARACTERISTICS
IH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
IH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
(1,2)
(OVER OPERATING RANGE)
Symbol Parameter Min. Max. Unit
tTCYC TCK Clock cycle time 100 — ns
µ
A
fTF TCK Clock frequency — 10 MHz
tTH TCK Clock HIGH 4 0 — ns
tTL TCK Clock LOW 4 0 — ns
tTMSS TMS setup to TCK Clock Rise 10 — ns
tTDIS TDI setup to TCK Clock Rise 1 0 — ns
tCS Capture setup to TCK Rise 1 0 — ns
tTMSH
TMS hold after TCK Clock Rise
10 — ns
tTDIH TDI Hold after Clock Rise 1 0 — ns
tCH Capture hold after Clock Rise 10 — ns
tTDOV TCK LOW to TDO valid — 2 0 ns
tTDOX TCK LOW to TDO invalid 0 — n s
Notes:
1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
27
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
®
TAP AC TEST CONDITIONS (2.5V/3.3V)
Input pulse levels 0 to 2.5V/0 to 3.0V
Input rise and fall times 1ns
Input timing reference levels 1.25V/1.5V
Output reference levels 1.25V/1.5V
Test load termination supply voltage 1.25V/1.5V
Vtrig 1.25V/1.5V
TAP TIMING
TAP Output Load Equivalent
50Ω
Vtrig
TDO
Z0 = 50Ω
20 pF
GND
1 2 3 4 5 6
t
TCK
THTH
t
MVTH tTHMX
t
TLTH
t
THTL
TMS
t
DVTH tTHDX
TDI
t
TLOV
TDO
t
TLOX
DON'T CARE
UNDEFINED
28
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
165 PBGA BOUNDARY SCAN ORDER (x 36)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Name ID Bit # Na me ID Bit # Nam e ID Bit # Na me ID
1 MODE 1R 21 DQb 11G 41 NC 1A 61 DQd 1J
2 N C 6N 22 DQb 11F 4 2 CE2 6A 62 DQd 1K
3 NC 11P 23 DQb 11E 43 BWa 5B 63 DQd 1L
4 A 8P 24 DQb 11D 44 BWb 5A 64 DQd 1M
5 A 8R 25 DQb 10G 45 BWc 4A 65 DQd 2J
6 A 9R 26 DQb 10F 46 BWd 4B 66 DQd 2K
7 A 9P 27 DQb 10E 47 CE2 3B 67 DQd 2L
8 A 10P 28 DQb 10D 48 CE 3A 68 DQd 2M
9 A 10R 29 DQb 11C 49 A 2A 69 DQd 1N
10 A 11R 30 NC 11A 50 A 2B 70 A 3P
11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R
®
12 DQa 11N 32 A 10B 52 DQc 1C 72 A 4R
13 DQa 11M 33 A 9A 53 DQc 1D 73 A 4P
14 DQa 11L 34 NC 9B 54 DQc 1E 74 A1 6P
15 DQa 11K 35 ADV 8A 55 DQc 1F 75 A0 6R
16 DQa 11J 36 OE 8B 56 DQc 1G
17 DQa 10M 37 CKE 7A 57 DQc 2D
18 DQa 10L 38 WE 7B 58 DQc 2E
19 DQa 10K 39 CLK 6B 59 DQc 2F
20 DQa 10J 40 NC 11B 60 DQc 2G
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
29
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
119 BGA BOUNDARY SCAN ORDER (x 36)
®
30
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
165 PBGA BOUNDARY SCAN ORDER (x 18)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Name ID Bit # Na me ID Bit # Nam e ID Bit # Na me ID
1 MODE 1R 21 DQa 11G 41 NC 1A 61 DQb 1J
2 N C 6N 22 DQa 11F 4 2 CE2 6A 62 DQb 1K
3 NC 11P 23 DQa 11E 43 BWa 5B 63 DQb 1L
4 A 8P 24 DQa 11D 44 NC 5A 64 DQb 1M
5 A 8R 25 DQa 11C 45 BWb 4A 65 DQb 1N
6 A 9R 26 NC 10F 46 NC 4B 66 NC 2K
7 A 9P 27 NC 10E 47 CE2 3B 67 NC 2L
8 A 10P 28 N C 10D 48 CE 3A 68 NC 2M
9 A 10R 29 NC 10G 49 A 2A 69 NC 2J
10 A 11R 30 A 11A 50 A 2B 70 A 3P
11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R
®
12 NC 11N 32 A 10B 52 NC 1C 72 A 4R
13 NC 11M 33 A 9A 53 NC 1D 73 A 4P
14 NC 11L 34 NC 9B 54 NC 1E 74 A1 6P
15 NC 11K 35 ADV 8A 55 NC 1F 75 A0 6R
16 NC 11J 36 OE 8B 56 NC 1G
17 DQa 10M 37 CKE 7A 57 DQb 2D
18 DQa 10L 38 WE 7B 58 DQ b 2E
19 DQa 10K 39 CLK 6B 59 DQb 2F
20 DQa 10J 40 NC 11B 60 DQb 2G
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
31
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
119 BGA BOUNDARY SCAN ORDER (x 18)
®
32
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Access Time Order Part Number Package
256Kx36
250 IS61NLP25636A-250TQ 100 TQFP
IS61NLP25636A-250B3 165 PBGA
IS61NLP25636A-250B2 119 PBGA
200 IS61NLP25636A-200TQ 100 TQFP
IS61NLP25636A-200B3 165 PBGA
IS61NLP25636A-200B2 119 PBGA
512Kx18
250 IS61NLP51218A-250TQ 100 TQFP
IS61NLP51218A-250B3 165 PBGA
IS61NLP51218A-250B2 119 PBGA
200 IS61NLP51218A-200TQ 100 TQFP
IS61NLP51218A-200B3 165 PBGA
IS61NLP51218A-200B2 119 PBGA
®
Industrial Range: -40°C to +85°C
Access Time Order Part Number Package
250 IS61NLP25636A-250TQI 100 TQFP
200 IS61NLP25636A-200TQI 100 TQFP
250 IS61NLP51218A-250TQI 100 TQFP
200 IS61NLP51218A-200TQI 100 TQFP
256Kx36
IS61NLP25636A-250B3I 165 PBGA
IS61NLP25636A-250B2I 119 PBGA
IS61NLP25636A-200B3I 165 PBGA
IS61NLP25636A-200B2I 119 PBGA
512Kx18
IS61NLP51218A-250B3I 165 PBGA
IS61NLP51218A-250B2I 119 PBGA
IS61NLP51218A-200B3I 165 PBGA
IS61NLP51218A-200B2I 119 PBGA
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
33
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
ORDERING INFORMATION (VDD = 2.5V/VDDQ = 2.5V)
Commercial Range: 0°C to +70°C
Access Time Order Part Number Package
256Kx36
250 IS61NVP25636A-250TQ 100 TQFP
IS61NVP25636A-250B3 165 PBGA
IS61NVP25636A-250B2 119 PBGA
200 IS61NVP25636A-200TQ 100 TQFP
IS61NVP25636A-200B3 165 PBGA
IS61NVP25636A-200B2 119 PBGA
512Kx18
250 IS61NVP51218A-250TQ 100 TQFP
IS61NVP51218A-250B3 165 PBGA
IS61NVP51218A-250B2 119 PBGA
200 IS61NVP51218A-200TQ 100 TQFP
IS61NVP51218A-200B3 165 PBGA
IS61NVP51218A-200B2 119 PBGA
®
Industrial Range: -40°C to +85°C
Access Time Order Part Number Package
250 IS61NVP25636A-250TQI 100 TQFP
200 IS61NVP25636A-200TQI 100 TQFP
250 IS61NVP51218A-250TQI 100 TQFP
200 IS61NVP51218A-200TQI 100 TQFP
256Kx36
IS61NVP25636A-250B3I 165 PBGA
IS61NVP25636A-250B2I 119 PBGA
IS61NVP25636A-200B3I 165 PBGA
IS61NVP25636A-200B2I 119 PBGA
512Kx18
IS61NVP51218A-250B3I 165 PBGA
IS61NVP51218A-250B2I 119 PBGA
IS61NVP51218A-200B3I 165 PBGA
IS61NVP51218A-200B2I 119 PBGA
34
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
PACKAGING INFORMATION ISSI
Plastic Ball Grid Array
Package Code: B (119-pin)
φ
b (119X)
E
30ϒ
D2D
A
D1
e
7654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
®
A2
E2
A4
A3
MILLIMETERS INCHES
Sym. Min. Max. Min. Max.
N0.
Leads 119
A — 2.41 — 0.095
A1 0.50 0.70 0.020 0.028
A2 0.80 1.00 0.032 0.039
A3 1.30 1.70 0.051 0.067
A4 0.56 BSC 0.022 BSC
b 0.60 0.90 0.024 0.035
D 21.80 22.20 0.858 0.874
D1 20.32 BSC 0.800 BSC
D2 19.40 19.60 0.764 0.772
E 13.80 14.20 0.543 0.559
E1 7.62 BSC 0.300 BSC
E2 11.90 12.10 0.469 0.476
e 1.27 BSC 0.050 BSC
A1
SEATING PLANE
E1
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusion and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
02/12/03
1-800-379-4774
PACKAGING INFORMATION ISSI
Ball Grid Array
Package Code: B (165-pin)
®
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A2
TOP VIEW
A1 CORNER
1 2 3 4 5 6 7 8 9 10 11
BOTT OM VIEW
φ b (165X)
11 10 9 8 7 6 5 4 3 2 1
e
D
D1
A1 CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
e
E1
E
A
A1
BGA - 13mm x 15mm
Notes:
MILLIMETERS INCHES
Sym. Min. Nom. Max. Min. Nom. Max.
N0.
Leads 165 165
A — — 1.20 — — 0.047
A1 0.25 0.33 0.40 0.010 0.013 0.016
A2 — 0.79 — — 0.031 —
D 14.90 15.00 15.10 0.587 0.591 0.594
D1 13.90 14.00 14.10 0.547 0.551 0.555
E 12.90 13.00 13.10 0.508 0.512 0.516
E1 9.90 10.00 10.10 0.390 0.394 0.398
e—1.00 — — 0.039 —
b 0.40 0.45 0.50 0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
1. Controlling dimensions are in millimeters.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
06/11/03
1-800-379-4774
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
E
E1
N
®
ISSI
D
D1
1
A2
A1
e
b
Thin Quad Flat Pack (TQ)
Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 100 128
A — 1.60 — 0.063 — 1.60 — 0.063
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057
b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011
D 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874
D1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791
E 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638
E1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555
e 0.65 BSC 0.026 BSC 0.50 BSC 0.020 BSC
L 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030
L1 1.00 REF. 0.039 REF. 1.00 REF. 0.039 REF.
C0
o
o
7
o
0
o
7
o
0
o
7
o
0
7
C
SEATING
PLANE
A
Notes:
1. All dimensioning and
2. Dimensions D1 and E1 do
3. Controlling dimension:
o
L1
L
tolerancing conforms to
ANSI Y14.5M-1982.
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
millimeters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev. D 05/08/03
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