ISSI IS61NLP25636A, IS61NVP25636A, IS61NLP51218A, IS61NVP51218A User Manual
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
256K x 36 and 512K x 18
9Mb, PIPELINE 'NO WAIT' STATE BUS
SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119ball PBGA packages
• Power supply:
NVP: V
NLP: V
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
DD 2.5V (± 5%), VDDQ 2.5V (± 5%)
DD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
DESCRIPTION
The 9 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
®
ISSI
MAY 2005
FAST ACCESS TIME
Symbol Parameter -250 -200 Units
tKQ Clock Access Time 2.6 3.1 ns
tKC Cycle Time 4 5 n s
Frequency 250 200 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
1
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
BLOCK DIAGRAM
®
x 36: A [0:17] or
x 18: A [0:18]
CLK
CKE
CE
CE2
CE2
ADV
WE
BW
Ÿ
X
(X=a,b,c,d or a,b)
OE
ZZ
CONTROL
LOGIC
}
ADDRESS
REGISTER
K
CONTROL
REGISTER
DQx/DQPx
A2-A17 or A2-A18
MODE
A0-A1 A'0-A'1
WRITE
ADDRESS
REGISTER
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
36 or 18
256Kx36;
512Kx18
MEMORY ARRAY
K
DATA-IN
REGISTER
K
DATA-IN
REGISTER
K
OUTPUT
REGISTER
BUFFER
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Bottom View
119-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 7 x 17 Ball Array
®
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
3
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
PIN CONFIGURATION — 256K X 36, 165-Ball PBGA (TOP VIEW)
1234567891011
ANC A CE BWc BWb CE2 CKE ADV A A NC
B N C A CE2 BWd BWa CLK WE OE NC A NC
C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
HNC NC NC VDD VSS VSS VSS VDD NC NC ZZ
J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
N DQPd NC VDDQ VSS NC NC NC VSS VDDQ NC DQPa
®
P N C NC A A TDI A1* TDO A A A NC
R MODE NC A A TMS A0* TCK A A A A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CL K Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d) Synchronous Byte Write Inputs
MODE Burst Sequence Selection
TCK, TDI JTAG Pins
TDO, TMS
VDD 3.3V/2.5V Power Supply
N C No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ Isolated output Power Supply
3.3V/2.5V
VSS Ground
OE Output Enable
ZZ Power Sleep Mode
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
119-PIN PBGA PACKAGE CONFIGURATION 256K x 36 (TOP VIEW)
1234567
®
A
B
C
D
E
F
G
H
M
N
P
R
V
DDQ
NC
NC
A
CE2
A
DQc DQPc Vss
DQc DQc Vss
V
DDQ
DQc
DQc DQc
DQc DQc
J
K
L
V
DDQ
V
DD
DQd DQd
DQd DQd
V
DDQ
DQd
DQd DQd
DQd
NC
T
NC
DQPd
A
NC
A
A
A
V
SS
SS
V
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
NC
ADV
DD
V
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
A
1
*
A
0
*
V
DD
A
A
A
A
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
NC
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
DDQ
V
DQa
DQa
DDQ
V
DQa
DQa
NCA
ZZ
U
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
V
DDQ
TMS TDI
TCK
TDO
NC
V
DDQ
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CL K Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE 2 Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
VDD Power Supply
VSS Ground
N C No Connect
DQa-DQd Data Inputs/Outputs
DQPa-Pd Parity Data I/O
VDDQ Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
5
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
165-PIN PBGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
1234567891011
®
A
BNC
CNC
DNC
ENC
F
GNC
HNC
J
K
L
M DQb NC Vss
N DQPb
PNC
R MODE
NC
NC DQb NC
DQb
DQb
DQb
A
A
NC Vss
DQb
DQb
CE
CE2
V
DDQ
VDDQ
VDDQ
VDDQ
DQb
NC
NC
NC
NC
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
VDDQ
A
A
BWb
NC
V
V
V
V
V
V
DD
V
DD
V
V
Vss
DD
DD
DD
DD
DD
DD
DD
A
A
NC
BWa
Vss
CE2
CLK
Vss
Vss Vss NC
Vss Vss Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
1
* TDO
A
0
*
CKE
WE
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TCK
ADV
OE
Vss
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
Vss
A
A
V
V
V
V
V
NC
V
V
V
V
V
A
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CL K Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDI JTAG Pins
TDO, TMS
VDD 3.3V/2.5V Power Supply
N C No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ Isolated output Power Supply
3.3V/2.5V
VSS Ground
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
119-PIN PBGA PACKAGE CONFIGURATION 512K x 18 (TOP VIEW)
1234567
®
A
B
C
D
E
F
G
H
M
N
P
R
V
DDQ
NC
NC
DQb Vss
NC
V
DDQ
NC
DQb
J
K
L
V
DDQ
NC
DQb
V
DDQ
A
CE2
A
NC
DQb Vss
NC
DQb
NC
V
DD
DQb
NC
DQb
DQb NC
NC
NC
T
NC
DQPb
A
A
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
MODE
A
NC
ADV
V
DD
NC
CE
OE
A
WE
V
DD
CLK
NC
CKE
1
*
A
0
*
A
V
DD
NC
A
A
A
Vss
NC
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
A
CE2
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
DDQ
V
DQa
NC
DDQ
V
NC
DQa
NCA
ZZ
U
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
V
DDQ
TMS TDI
TCK
TDO
NC
V
DDQ
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CL K Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE 2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
VDD Power Supply
VSS Ground
N C No Connect
DQa-DQb Data Inputs/Outputs
DQPa-Pb Parity Data I/O
VDDQ Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
7
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
PIN CONFIGURATION
100-Pin TQFP
A ACE
CE2
BWd
BWc
BWb
BWa
CE2
VDDVss
DQPc
DQc
DQc
DDQ
V
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
V
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
CLKWECKEOEADVNCAAA
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
DD
15
16
NC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AAA
MODE
A
A1
A0
NC
NC
Vss
DD
NC
NC
V
AAAAAAA
80
DQPb
79
DQb
78
DQb
77
V
DDQ
76
Vss
75
DQb
74
DQb
73
DQb
72
DQb
71
Vss
70
DDQ
V
69
DQb
68
DQb
67
Vss
66
NC
65
V
DD
ZZ
64
DQa
63
DQa
62
61
V
DDQ
60
Vss
59
DQa
58
DQa
57
DQa
56
DQa
Vss
55
V
DDQ
54
53
DQa
DQa
52
DQPa
51
V
DDQ
Vss
DQb
DQb
Vss
DDQ
V
DQb
DQb
V
Vss
DQb
DQb
DDQ
V
Vss
DQb
DQb
DQPb
Vss
DDQ
V
NC
NC
NC
NC
NC
NC
DD
NC
NC
NC
NC
NC
AACE
CE2NCNC
BWbBWaCE2
VDDVss
CLKWECKEOEADVNCAAA
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
AAA
A
A1
A0
NC
NC
Vss
DD
NC
NC
V
AAAAAAA
80
A
79
NC
78
NC
77
DDQ
V
76
Vss
75
NC
74
DQPa
73
DQa
72
DQa
71
Vss
70
DDQ
V
69
DQa
68
DQa
67
Vss
66
NC
65
DD
V
ZZ
64
DQa
63
DQa
62
61
DDQ
V
60
Vss
59
DQa
58
DQa
57
NC
56
NC
55
Vss
54
DDQ
V
53
NC
NC
52
NC
51
®
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CL K Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
Vss Ground for Core
N C Not Connected
8
Integrated Silicon Solution, Inc. — www.issi.com —
512K x 18
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
DQPa-DQPd Parity Data I/O
MODE Burst Sequence Selection
VDD +3.3V/2.5V Power Supply
VSS Ground for output Buffer
VDDQ
ZZ Snooze Enable
Isolated Output Buffer Supply: +3.3V/2.5V
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
STATE DIAGRAM
READ
®
READ
READ
BURST
BEGIN
READ
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE
WRITE
READ WRITE
DESELECT
DS
DS
WRITE
(1)
DSDS
BURST
DS
READ
BEGIN
WRITE
BURST
BURST
WRITE
WRITE
WRITE
BURST
Address
Operation Used
CECE
CE CE2
CECE
CECE
CE2 ADV
CECE
WEWE
WE
WEWE
BWBW
BWx
BWBW
OEOE
OE
OEOE
CKECKE
CKE CLK
CKECKE
Not Selected N/A H X X L X X X L ↑
Not Selected N/A X L X L X X X L ↑
Not Selected N/A X X H L X X X L ↑
Not Selected Continue N/A X X X H X X X L ↑
Begin Burst Read External Address L H L L H X L L ↑
Continue Burst Read Next Address X X X H X X L L ↑
NOP/Dummy Read External Address L H L L H X H L ↑
Dummy Read Next Address X X X H X X H L ↑
Begin Burst Write External Address L H LLLLXL↑
Continue Burst Write Next Address X X X H X L X L ↑
NOP/Write Abort N/A L H L L L H X L ↑
Write Abort Next Address X X X H X H X L ↑
Ignore Clock Current Address X X X X X X X H ↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
9
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
®
ASYNCHRONOUS TRUTH TABLE
Operation ZZ
(1)
OEOE
OE I/O STATUS
OEOE
Sleep Mode H X High-Z
Read
LL DQ
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WEWE
WE
WEWE
READ H X X
WRITE BYTE a L L H
WRITE BYTE b L H L
WRITE ALL BYTEs L L L
WRITE ABORT/NOP L H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
BWBW
BWa
BWBW
BWBW
BWb
BWBW
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
WRITE TRUTH TABLE (x36)
®
Operation
READ H X X X X
WRITE BYTE a L L H H H
WRITE BYTE b L H L H H
WRITE BYTE c L H H L H
WRITE BYTE d L H H H L
WRITE ALL BYTEs L L L L L
WRITE ABORT/NOP L H H H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WEWE
WE
WEWE
BWBW
BWa
BWBW
BWBW
BWb
BWBW
BWBW
BWc
BWBW
BWBW
BWd
BWBW
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. A
05/04/05
1-800-379-4774
11
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ISSI
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
0,1A1', A0' = 1,1
1,0
®
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TSTG Storage Temperature –65 to +150 ° C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 10 0 mA
VIN, VOUT Voltage Relative to VSS for I/O Pins –0.5 to VDDQ + 0.3 V
VIN Voltage Relative to VSS for –0.3 to 4.6 V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however,
precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance
circuit.
This device contains circuitry that will ensure the output devices are in High-Z at power up.
3.
(1)
OPERATING RANGE (IS61NLPx)
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 3.3V ± 5% 3.3V / 2.5V ± 5%
Industrial -40°C to +85°C 3.3V ± 5% 3.3V / 2.5V ± 5%
OPERATING RANGE (IS61NVPx)
Range Ambient Temperature VDD VDDQ
Commercial 0°C to +70°C 2.5V ± 5% 2.5V ± 5%
Industrial -40°C to +85°C 2.5V ± 5% 2.5V ± 5%
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
05/04/05
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