ISSI IS61LV256AL User Manual
IS61LV256AL ISSI
®
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FEATURES
• High-speed access times:
— 10 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 60 µW (typical) CMOS standby
— 65 mW (typical) operating
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Lead-free available
MARCH 2006
DESCRIPTION
The ISSI IS61LV256AL is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61LV256AL is available in the JEDEC standard 28pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VDD
GND
I/O0-I/O7
CE
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
1
IS61LV256AL ISSI
®
PIN CONFIGURATION
28-Pin SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP (Type I)
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
CECE
CE
CECE
OEOE
OE I/O Operation VDD Current
OEOE
VDD Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VDD Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
IS61LV256AL ISSI
OPERATING RANGE
Range Ambient Temperature Speed (ns) VDD
Commercial 0°C to +70°C 10 3.3V, +10%, –5%
Industrial –40°C to +85°C 10 3.3V + 10%, –5%
Note: 1. If operated at 12ns, VDD range is 3.3V + 10%.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –2.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 4.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
(1)
(1)
–0.3 0.8 V
Ind. –2 2
®
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –1 1 µA
Ind. –2 2
Notes:
IL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
1. V
VIH (max.) = VDD + 0.5V (DC); VIH (max.) = VDD + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
3
IS61LV256AL ISSI
®
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
Sym. Parameter Test Conditions Min. Max. Unit
ICC1VDD Operating VDD = Max., CE = VIL Com. — 20 mA
Supply Current I OUT = 0 mA, f = 1 MHz Ind. — 25
ICC2VDD Dynamic Operating VDD = Max., CE = VIL Com. — 30 mA
Supply Current I OUT = 0 mA, f = fMAX Ind. — 35
(2)
typ.
SB1 TTL Standby Current VDD = Max., Com. — 1 mA
I
20
(TTL Inputs) VIN = VIH or VIL Ind. — 1
CE ≥ VIH , f = 0
I
SB2 CMOS Standby VDD = Max., Com. — 40 µA
Current (CMOS Inputs) CE ≤ V DD – 0.2V, Ind. — 50
VIN ≥ V DD – 0.2V, or typ.
(2)
2
VIN ≤ 0.2V, f = 0
Notes:
1. At f = f
2. Typical values are measured at V
CAPACITANCE
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DD = 3.3V, TA = 25
(1,2)
o
C and not 100% tested.
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
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