ISSI IS61LV256-20TI, IS61LV256-20T, IS61LV256-20JI, IS61LV256-20J, IS61LV256-15T Datasheet

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. I

11/09/99

IS61LV256 ISSI

®

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

FEATURES

• High-speed access times:

-- 8, 10, 12, 15, 20 ns

• Automatic power-down when chip is deselected

• CMOS low power operation

-- 345 mW (max.) operating

-- 7 mW (max.) CMOS standby

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh
required

• Three-state outputs

DESCRIPTION

The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using

ISSI's high-performance CMOS technology. This highly

reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.

The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil SOJ and the 450-mil TSOP (Type I) package.

32K x 8 LOW VOLTAGE
CMOS STATIC RAM OCTOBER 1999

FUNCTIONAL BLOCK DIAGRAM

A0-A14

CE
OE
WE

256 X 1024

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

IS61LV256 ISSI

®

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. I

11/09/99

PIN CONFIGURATION

28-Pin SOJ

22
23
24
25
26
27
28
1
2
3
4
5
6
7

21
20
19
18
17
16
15
14
13
12
11
10

9
8

OE

A11

A9
A8

A13

WE

VCC

A14
A12

A7
A6
A5
A4
A3

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

PIN CONFIGURATION

28-Pin TSOP (Type I)

PIN DESCRIPTIONS

A0-A14 Address Inputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Input/Output
Vcc Power
GND Ground

TRUTH TABLE

Mode WE CE OE I/O Operation Vcc Current

Not Selected X H X High-Z ISB1, ISB2
(Power-down)

Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VCC Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias Com. –10 to +85 °C

Ind. –45 to +90
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1 W
IOUT DC Output Current ±20 mA

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IS61LV256 ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. I

11/09/99

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage

(1)

–0.3 0.8 V

I

LI Input Leakage GND ≤ VIN ≤ VCC Com. –11µA

Ind. –55

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –11µA

Ind. –55

Notes:

1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
V

IH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

CAPACITANCE

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc = 3.3V.

OPERATING RANGE

Range Ambient Temperature Speed VCC

Commercial 0°C to +70°C 8, 10, 12 3.3V, +10%, –5%

15, 20 3.3V ± 10%

Industrial –40°C to +85°C All 3.3V + 10%, –5%

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

(2)

-10 ns

(2)

-12 ns -15 ns -20 ns

Sym. Parameter Test Conditions

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 120 — 110 — 100 — 90 — 80 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. —— —120 — 110 — 100 — 90

ISB1 TTL Standby Current VCC = Max., Co m. — 15 — 10 — 10 — 10 — 10 mA

(TTL Inputs) VIN = VIH or VIL Ind. —— —20 — 20 — 20 — 20

CE ≥ VIH, f = 0

ISB2 CMOS Standby VCC = Max., Co m. — 2 — 2 — 2 — 2 — 2mA

Current (CMOS Inputs) CE ≤ VCC – 0.2V, Ind. —— — 5 — 5 — 5 — 5

VIN > VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

Notes:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

2. Shaded area = PREPRODUCTION AVAILABILITY.