ISSI IS61C64B-15T, IS61C64B-15J, IS61C64B-12N, IS61C64B-12J, IS61C64B-10T Datasheet
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IS61C64B ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. C
07/17/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
• High-speed access time: 10, 12, and 15 ns
• Automatic power-down when chip is
deselected
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• One Chip Enables (CE) for increased speed
8K x 8 HIGH-SPEED CMOS STATIC RAM
DESCRIPTION
The ISSI IS61C64B is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields
access times as fast as 10 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using one Chip
Enable input, CE. The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS61C64B is packaged in the JEDEC standard 28-pin,
300-mil DIP and SOJ, and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
CE
OE
WE
256 X 256
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
JULY 2001
IS61C64B ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/17/01
PIN CONFIGURATION
28-Pin DIP and SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
*
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A12 Address Inputs
CE Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
* Must be tied to either
Vcc or GND
Vcc Power
GND Ground
TRUTH TABLE
Mode WE CE OE I/O Operation Vcc Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down) X X X High-Z ISB1, ISB2
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
*
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN CONFIGURATION
28-Pin TSOP (Type 1)
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C 10 ns 5V ± 5%
12 ns 5V ± 10%
15 ns 5V ± 10%
1
2
3
4
5
6
7
8
9
10
11
12
IS61C64B ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. C
07/17/01
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage
(1)
–0.5 0.8 V
ILI Input Leakage GND - VIN - VCC –22µA
ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –22µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns -12 ns -15 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., — 185 — 175 — 135 mA
Supply Current IOUT = 0 mA, f = fMAX
ISB1 TTL Standby Current VCC = Max., — 30 — 30 — 30 mA
(TTL Inputs) VIN = VIH or VIL
CE1 • VIH or
CE2 - VIL, f = 0
ISB2 CMOS Standby VCC = Max., — 10 — 10 — 10 mA
Current (CMOS Inputs) CE1 • VCC – 0.2V,
CE2 - 0.2V,
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
Notes:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 10 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 5.0V.
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