ISSI IS61C256AH-25TI, IS61C256AH-25T, IS61C256AH-25N, IS61C256AH-25JI, IS61C256AH-25J Datasheet
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®
IS61C256AH
ISSI
32K x 8 HIGH-SPEED CMOS STATIC RAM MAY 1999
FEATURES
• High-speed access time: 10, 12, 15, 20, 25 ns
• Low active power: 400 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
— 55 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
DESCRIPTION
The
ISSI
IS61C256AH is a very high-speed, low power,
32,768 word by 8-bit static RAMs. They are fabricated using
ISSI
's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
The IS61C256AH is pin compatible with other 32K x 8 SRAMs
and are available in 28-pin PDIP, SOJ, and TSOP (Type I)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
1
IS61C256AH
®
ISSI
PIN CONFIGURATION
28-Pin DIP and SOJ
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A12
I/O0
I/O1
I/O2
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP
22
OE
A9
A8
A7
A6
A5
A4
A3
23
24
25
26
27
28
1
2
3
4
5
6
7
A11
A13
WE
VCC
A14
A12
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE
OE
Chip Enable Input
Output Enable Input
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
CECE
CE
CECE
Output Disabled H L H High-Z ICC
WE
I/O0-I/O7 Bidirectional Ports
Write Enable Input
Read H L L DOUT ICC
Write L L X DIN ICC
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OEOE
OE
I/O Operation Vcc Current
OEOE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
IS61C256AH
ISSI
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C -10, -12 5V ± 5%
-15, -20, -25 5V ± 10%
Industrial –40°C to +85°C -12 5V ± 5%
-15, -20, -25 5V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –5 5 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Com. –5 5 µA
(1)
Outputs Disabled Ind. –10 10
–0.5 0.8 V
Ind. –10 10
®
Note:
IL = –3.0V for pulse width less than 10 ns.
1. V
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 165 — 155 — 145 — 135 — 125 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 165 — 155 — 145 — 135
ISB1 TTL Standby Current VCC = Max., Com. — 25 — 25 — 25 — 25 — 25 mA
(TTL Inputs) VIN = VIH or VIL Ind. — — — 30 — 30 — 30 — 30
CE
≥ VIH, f = 0
ISB2 CMOS Standby VCC = Max., Com. — 2 — 2 — 2 — 2 — 2 mA
Current (CMOS Inputs)CE ≥ VCC – 0.2V, Ind. — — — 10 — 10 — 10 — 10
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
CAPACITANCE
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
(1)
(Over Operating Range)
-10 -12 -15 -20 -25
COUT Output Capacitance VOUT = 0V 10 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
3
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