ISSI IS41C16257A, IS41LV16257A User Manual

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IS41C16257A

IS41LV16257A ISSI

®

256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE

FEATURES

• Fast access and cycle time

• TTL compatible inputs and outputs

• Refresh Interval: 512 cycles/8 ms

•

Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
and Hidden

• JEDEC standard pinout

• Single power supply:

-- 5V ± 10% (IS41C16257A)

-- 3.3V ± 10% (IS41LV16257A)

• Byte Write and Byte Read operation via two CAS

• Lead-free available

APRIL 2005

DESCRIPTION

The ISSI IS41C16257A and the IS41LV16257A are
262,144 x 16-bit high-performance CMOS Dynamic
Random Access Memories. Fast Page Mode allows
512 random accesses within a single row with access
cycle time as short as 12 ns per 16-bit word. The Byte
Write control, of upper and lower byte, makes these
devices ideal for use in 16- and 32-bit wide data bus
systems.

These features make the IS41C16257A and the
IS41LV16257A ideally suited for high band-width
graphics, digital signal processing, high-performance
computing systems, and peripheral applications.

The IS41C16257A and the IS41LV16257A are
packaged in a 40-pin, 400-mil SOJ and TSOP (Type II).

KEY TIMING PARAMETERS

Parameter -35 -60 Unit

Max. RAS Access Time (tRAC)3560ns
Max. CAS Access Time (tCAC)1115ns
Max. Column Address Access Time (tAA)1830ns
Min. Fast Page Mode Cycle Time (tPC)1425ns
Min. Read/Write Cycle Time (tRC) 60 110 ns

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

1

IS41C16257A

E

L

IS41LV16257A

FUNCTIONAL BLOCK DIAGRAM

O
WE

®

ISSI

CAS

UCAS

RAS

A0-A8

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS
BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

262,144 x 16

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O15

DATA I/O BUFFERS

PIN CONFIGURATIONS
40-Pin TSOP (Type II)

40

GND

39

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

I/O11

33

I/O10

32

I/O9

31

I/O8

30

NC

29

LCAS

28

UCAS

27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

GND

NC
NC

WE

NC

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

VCC

I/O0
I/O1
I/O2
I/O3

VCC

I/O4
I/O5
I/O6
I/O7

RAS

VCC

40-Pin SOJ

1

VCC

2

I/O0

3

I/O1

4

I/O2

5

I/O3

VCC

6

I/O4

7

I/O5

8

I/O6

9

I/O7

10

NC

11

NC

12

WE

13

RAS

14

NC

15

A0

16

A1

17

A2

18

A3

19

VCC

20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND

PIN DESCRIPTIONS

A0-A8 Address Inputs
I/O0-I/O15 Data Inputs/Outputs

WE Write Enable
OE Output Enable
RAS Row Address Strobe

UCAS Upper Column Address

Strobe

LCAS Lower Column Address

Strobe
Vcc Power
GND Ground
NC No Connection

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

IS41C16257A
IS41LV16257A

TRUTH TABLE

®

ISSI

Function

Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT

Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z

Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN

Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z

Read-Write
Hidden Refresh

RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. At least one of the two CAS signals must be active (LCAS or UCAS).

(1,2)

2)

(3)

Read L∅H∅L L L H L ROW/COL DOUT
Write L∅H∅L L L L X ROW/COL DOUT

RASRAS

RAS

RASRAS

LLLH∅LL∅H ROW/COL DOUT, DIN

H∅L L L X X X High-Z

LCASLCAS

LCAS

LCASLCAS

UCASUCAS

UCAS

UCASUCAS

WEWE

WE

WEWE

OEOE

OE Address tR/tC I/O

OEOE

Upper Byte, High-Z

Upper Byte, DOUT

Upper Byte, High-Z

Upper Byte, DIN

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

3

IS41C16257A
IS41LV16257A

FUNCTIONAL DESCRIPTION

®

ISSI

The IS41C16257A and the IS41LV16257A are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is used
to latch the first nine bits and CAS is used to latch the latter
nine bits.

The IS41C16257A and the IS41LV16257A has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generate a CAS signal functioning in an identical
manner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE and
WE and RAS). LCAS controls I/O0 - I/O7 and UCAS
controls I/O8 - I/O15.

The IS41C16257A and the IS41LV16257A CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16257A both BYTE READ and BYTE
WRITE cycle capabilities.

Memory Cycle

A memory cycle is initiated by bringing RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tRAS time has expired. A new cycle
must not be initiated until the minimum precharge time tRP,
tCP has elapsed.

on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs last.

Refresh Cycle

To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:

1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad­dressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle, an
internal 9-bit counter provides the row addresses and the

external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.

Power-On

After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a RAS signal).

During power-on, it is recommended that RAS track with VCC
or be held at a valid VIH to avoid current surges.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

IS41C16257A
IS41LV16257A

®

ISSI

ABSOLUTE MAXIMUM RATINGS

Symbol Parameters Rating Unit

T Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V

V

V

CC Supply Voltage 5V –1.0 to +7.0 V

IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Operation Temperature Com. 0 to +70 °C
TSTG Storage Temperature –55 to +125 °C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

(1)

3.3V –0.5 t0 +4.6

3.3V –0.5 t0 +4.6

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)

Symbol Parameter Voltage Min. Typ. Max. Unit

VCC Supply Voltage 5V 4.5 5.0 5.5 V
VCC Supply Voltage 3.3V 3.0 3.3 3.6 V

VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
VIH Input High Voltage 3.3V 2 .0 — VCC + 0.3 V
VIL Input Low Voltage 5V –1 .0 — 0.8 V
VIL Input Low Voltage 3.3 – 0.3 — 0.8 V

TA Ambient Temperature Com. 0 — 70 ° C

CAPACITANCE

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A8 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

(1,2)

A = 25°C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V ± 10%.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

5

IS41C16257A
IS41LV16257A

®

ISSI

ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current Any input 0V < VIN < Vcc –10 10 µA

IIO Output Leakage Current Output is disabled (Hi-Z) –1 0 10 µA

VOH Output High Voltage Level IOH = –2 mA 2.4 — V
VOL Output Low Voltage Level IOL = +2 mA — 0.4 V

ICC1 Stand-by Current: TTL RAS, LCAS, UCAS ≥ VIH Com. 5V — 4 mA
ICC1 Stand-by Current: TTL RAS, LCAS, UCAS ≥ VIH Com. 3.3V — 4 mA
ICC2 Stand-by Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V 5 V — 2 mA
ICC2 Stand-by Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V 3.3V — 1 mA
ICC3 Operating Current: RAS, LCAS, UCAS, -35 — 230 mA

Random Read/Write
Average Power Supply Current

ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -35 — 220 mA

Fast Page Mode
Average Power Supply Current

ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -35 — 230 mA

RAS-Only
Average Power Supply Current

ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -35 — 230 mA

CBR
Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper
device operation is assured.The eight RAS cycles wake-up should be repeated any time the t
exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each fast page cycle.

5. Enables on-chip refresh and address counters.

(2,3)

(2,3,5)

(2,3,4)

(2,3,4)

(1)

(Recommended Operation Conditions unless otherwise noted.)

Other inputs not under test = 0V

0V < VOUT < Vcc

Address Cycling, tRC = tRC (min.) -6 0 — 17 0

Cycling tPC = tPC (min.) -60 — 160

tRC = tRC (min.) -6 0 — 170

tRC = tRC (min.) -6 0 — 170

REF

refresh requirement is

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05