ISSI IS41LV16256B User Manual

查询IS41C85120供应商

IS41LV16256B ISSI

256K x 16 (4-MBIT) DYNAMIC RAM APRIL 2005
WITH EDO PAGE MODE

®

FEATURES

• TTL compatible inputs and outputs

• Refresh Interval: 512 cycles/8 ms

• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
and Hidden

• JEDEC standard pinout

• Single power supply: 3.3V ± 10%

• Byte Write and Byte Read operation via two CAS

• Lead-free available

DESCRIPTION

The

ISSI

IS41LV16256B is 262,144 x 16-bit high-perfor­mance CMOS Dynamic Random Access Memory. Both prod­ucts offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row
with access cycle time as short as 10ns per 16-bit word. The
Byte Write control, of upper and lower byte, makes the
IS41LV16256B ideal for use in 16 and 32-bit wide data bus
systems.

These features make the IS41LV16256B ideally
high

band-width

graphics,

digital signal processing, high-

performance computing systems, and peripheral applications.
The IS41LV16256B is packaged in 40-pin 400-mil SOJ and

KEY TIMING PARAMETERS

TSOP (Type II).

Parameter -35 -60 Unit

Max. RAS Access Time (tRAC)3560ns
Max. CAS Access Time (tCAC)1115ns
Max. Column Address Access Time (tAA)18 30 ns
Min. EDO Page Mode Cycle Time (tPC)1425ns
Min. Read/Write Cycle Time (tRC) 60 110 ns

suited for

PIN CONFIGURATIONS

40-Pin TSOP (Type II) 40-Pin SOJ

1

VDD

2

I/O0

3

I/O1

4

I/O2

5

I/O3

6

VDD

7

I/O4

8

I/O5

9

I/O6

10

I/O7

11

NC

12

NC

13

WE

14

RAS

15

NC

16

A0

17

A1

18

A2

19

A3

20

VDD

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

40

GND

39

I/O15

38

I/O14

37

I/O13

36

I/O12

35

GND

34

I/O11

33

I/O10

32

I/O9

31

I/O8

30

NC

29

LCAS

28

UCAS

27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

GND

VDD

I/O0
I/O1
I/O2
I/O3

VDD

I/O4
I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC

LCAS
UCAS
OE

A8
A7
A6
A5
A4
GND

PIN DESCRIPTIONS

A0-A8 Address Inputs
I/O0-15

WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS
LCAS

VDD Power
GND Ground
NC No Connection

Data Inputs/Outputs

Upper Column Address Strobe
Lower Column Address Strobe

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

1

IS41LV16256B ISSI

E

L

FUNCTIONAL BLOCK DIAGRAM

O
WE

®

CAS

UCAS

RAS

A0-A8

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS
BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

262,144 x 16

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O15

DATA I/O BUFFERS

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

IS41LV16256B ISSI

TRUTH TABLE

®

Function

RASRAS

RAS

RASRAS

LCASLCAS

LCAS

LCASLCAS

UCASUCAS

UCAS

UCASUCAS

WEWE

WE

WEWE

OEOE

OE Address tR/tC I/O

OEOE

Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT

Upper Byte, High-Z

Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z

Upper Byte, DOUT
Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN

Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z

Upper Byte, DIN
Read-Write
EDO Page-Mode Read

(1,2)

LLLH→LL→H ROW/COL DOUT, DIN

(2)

1st Cycle: L H→LH→L H L ROW/COL DOUT

2nd Cycle: L H→LH→L H L NA/COL DOUT

Any Cycle: L L→HL→H H L NA/NA DOUT

EDO Page-Mode Write

(1)

1st Cycle: L H→LH→L L X ROW/COL DIN

2nd Cycle: L H→LH→L L X NA/COL DIN

EDO Page-Mode 1st Cycle: L H→LH→LH→LL→H ROW/COL DOUT, DIN
Read-Write

Hidden Refresh

(1,2)

2nd Cycle: L H→LH→LH→LL→H NA/COL DOUT, DIN

2)

Read L→H→L L L H L ROW/COL DOUT

Write L→H→L L L L X ROW/COL DOUT
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. At least one of the two CAS signals must be active (LCAS or UCAS).

(3)

H→L L L X X X High-Z

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

3

IS41LV16256B ISSI

®

Functional Description

The IS41LV16256B is a CMOS DRAM optimized for high­speed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 18 address bits. These are entered nine bits (A0-A8)
at a time. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter nine bits.

The IS41LV16256B has two CAS controls, LCAS and
UCAS. The LCAS and UCAS inputs internally generates
a CAS signal functioning in an identical manner to the
single CAS input on the other 256K x 16 DRAMs. The key
difference is that each CAS controls its corresponding I/O
tristate logic (in conjunction with OE and WE and RAS).
LCAS controls I/O0 through I/O7 and UCAS controls I/O8
through I/O15.

The IS41LV16256B CAS function is determined by the
first CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16256B both BYTE READ and BYTE WRITE
cycle capabilities.

Refresh Cycle

To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.

1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the ad­dressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad­dresses and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Extended Data Out Page Mode

EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci­fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever
occurs last.

In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There­fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.

In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.

The EDO page mode allows both read and write opera­tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.

Power-On

After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight initial­ization cycles (any combination of cycles containing a
RAS signal).

During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

IS41LV16256B ISSI

®

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

VT Voltage on Any Pin Relative to GND 3.3V -0.5 to 4.6 V
VDD Supply Voltage 3.3V -0.5 to 4.6 V
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Commercial Operation Temperature 0 to +70 °C
TSTG Storage Temperature –55 to +125 °C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VDD Supply Voltage 3.3V 3.0 3.3 3.6 V

VIH Input High Voltage 3.3V 2.0 — VDD + 0.3 V

VIL Input Low Voltage 3.3V –0.3 — 0.8 V

TA Commercial Ambient Temperature 0 — +70 °C

CAPACITANCE

(1,2)

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A8 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz,

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

5

IS41LV16256B ISSI

®

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IL Input Leakage Current Any input 0V ≤ VIN ≤ VDD –10 10 µA

I

Other inputs not under test = 0V

I

IO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA

0V ≤ VOUT ≤ VDD
VOH Output High Voltage Level IOH = –2 mA 2.4 — V
VOL Output Low Voltage Level IOL = +2 mA — 0.4 V
ICC1 Stand-by Current: TTL RAS, LCAS, UCAS ≥ VIH Commercial 3V — 4 mA
ICC2 Stand-by Current: CMOS RAS, LCAS, UCAS ≥ VDD – 0.2V 3V — 1 mA

CC3 Operating Current: RAS, LCAS, UCAS, -35 — 230 mA

I

Random Read/Write
Average Power Supply Current

ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -35 — 220 mA

EDO Page Mode
Average Power Supply Current

ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -35 — 230 mA

RAS-Only

(2,3)

Average Power Supply Current

(2,3,4)

(2,3,4)

Address Cycling, tRC = tRC (min.) -60 — 170

Cycling tPC = tPC (min.) -60 — 160

tRC = tRC (min.) -6 0 — 170

ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -3 5 — 230 mA

(2,3,5)

CBR

tRC = tRC (min.) -6 0 — 170

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

REF refresh requirement is exceeded.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

IS41LV16256B ISSI

®

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-35 -60

Symbol Parameter Min. Max. Min. Max. Units

tRC Random READ or WRITE Cycle Time 7 0 — 1 1 0 — ns

(26)

(9, 25)

(6, 7)

(6, 8, 15)

(10, 20)

(20)

(20)

35 — 60 — ns
—11 —15 ns

(6)

—18 —30 ns

6 10K 10 10K ns

6— 10— ns
35 — 60 — ns
13 24 20 45 ns

0— 0— ns

6— 10— ns

tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Column-Address
tRAS RAS Pulse Width 35 10K 60 10K n s
tRP RAS Precharge Time 2 5 — 4 0 — ns
tCAS CAS Pulse Width
tCP CAS Precharge Time
tCSH CAS Hold Time

(21)

tRCD RAS to CAS Delay Time
tASR Row-Address Setup Time 0 — 0 — ns
tRAH Row-Address Hold Time 6 — 10 — ns
tASC Column-Address Setup Time
tCAH Column-Address Hold Time
tAR Column-Address Hold Time 30 — 4 5 — ns

(referenced to RAS)

tRAD RAS to Column-Address Delay Time

(11)

10 20 15 30 ns

tRAL Column-Address to RAS Lead Time 1 8 — 30 — ns
tRPC RAS to CAS Precharge Time 0 — 0 — ns
tRSH RAS Hold Time
tCLZ CAS to Output in Low-Z
tCRP CAS to RAS Precharge Time
tOD Output Disable Time
tOE / tOEA Output Enable Time

(27)

(15, 29)

(19, 28, 29)

(15, 16)

(21)

10 — 15 — ns

3— 3— ns

5— 5— ns

315 315 ns

011 —15 ns

tOEHC OE HIGH Hold Time from CAS HIGH 8 — 8 — ns
tOEP OE HIGH Pulse Width 8 — 8 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 7 — ns
tRCS Read Command Setup Time

(17, 20)

0— 0— ns

tRRH Read Command Hold Time 0 — 0 — ns

(referenced to RAS)

(12)

tRCH Read Command Hold Time 0 — 0 — ns

(referenced to CAS)

tWCH Write Command Hold Time

(12, 17, 21)

(17, 27)

5— 10— ns

tWCR Write Command Hold Time 3 0 — 5 0 — ns

(referenced to RAS)

(17)

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/28/05

7