Datasheet IS41LV16105-60TI, IS41LV16105-60TE, IS41LV16105-60T, IS41LV16105-60K, IS41LV16105-50TI Datasheet (ISSI)
...
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
03/03/00
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
IS41C16105
IS41LV16105 ISSI
®
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
— 1,024 cycles/16 ms
• Refresh Mode:
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
— 5V ± 10% (IS41C16105)
— 3.3V ± 10% (IS41LV16105)
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30
o
C to 85oC
• Industrail Temperature Range -40
o
C to 85oC
DESCRIPTION
The ISSI IS41C16105 and IS41LV16105 are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1,024 random accesses within a single
row with access cycle time as short as 20 ns per 16-bit word. The
Byte Write control, of upper and lower byte, makes the IS41C16105
ideal for use in 16-, 32-bit wide data bus systems.
These features make the IS41C16105 and IS41LV16105 ideally
suited for high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral applications.
The IS41C16105 and IS41LV16105 are packaged in a
42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II).
1M x 16 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
Max. RAS Access Time (tRAC)5060ns
Max. CAS Access Time (tCAC)1315ns
Max. Column Address Access Time (tAA)25 30 ns
Min. Fast Page Mode Cycle Time (tPC)20 25 ns
Min. Read/Write Cycle Time (tRC) 84 104 ns
PIN CONFIGURATIONS
44(50)-Pin TSOP (Type II) 42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-15 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
Vcc Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
FEBRUARY 2000
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
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Rev. A
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IS41C16105
IS41LV16105 ISSI
®
TRUTH TABLE
Function RAS LCAS UCAS WE OE Address tR/t
C
I/O
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL D
OUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, D
OUT
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, D
OUT
Write: Word (Early Write) LLLLXROW/COL D
IN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, D
IN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, D
IN
Read-Write
(1,2)
LLLH→LL→H ROW/COL D
OUT
, D
IN
Hidden Refresh Read
(2)
L→H→L L L H L ROW/COL D
OUT
Write
(1,3)
L→H→L L L L X ROW/COL D
OUT
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
(4)
H→L L L X X X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
Functional Description
The IS41C16105 and IS41LV16105 is a CMOS DRAM
optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
ten bits (A0-A9) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
nine bits.
The IS41C16105 and IS41LV16105 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C16105 and IS41LV16105 CAS function is determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16105 and IS41LV16105 both
BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
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Rev. A
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IS41C16105
IS41LV16105 ISSI
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
V
CC Supply Voltage 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
IOUT Output Current 50 mA
PD Power Dissipation 1 W
T
A Commercial Operation Temperature 0 to +70 °C
Extended Temperature –30 to +85 °C
Industrail Temperature –40 to +85 °C
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TA Commercial Ambient Temperature 0 — 70 °C
Extended Ambient Temperature –30 — 85 °C
Industrail Ambient Temperature –40 — 85 °C
CAPACITANCE
(1,2)
Symbol Parameter Max. Unit
CIN1 Input Capacitance: A0-A9 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz,
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –55µA
Other inputs not under test = 0V
I
IO Output Leakage Current Output is disabled (Hi-Z) –55µA
0V ≤ VOUT ≤ Vcc
V
OH Output High Voltage Level IOH = –5.0 mA (5V) 2.4 — V
IOH = –2.0 mA (3.3V)
V
OL Output Low Voltage Level IOL = 4.2 mA (5V) — 0.4 V
IOL = 2.0 mA (3.3V)
ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH
Commerical 5V — 3mA
3.3V — 3
Extended/Idustrial 5V — 4mA
3.3V — 4
ICC2 Standby Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
5V — 2mA
3.3V — 2
ICC3 Operating Current: RAS, LCAS, UCAS, -50 — 160 mA
Random Read/Write
(2,3,4)
Address Cycling, tRC = tRC (min.) -60 — 145
Average Power Supply Current
ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -50 — 90 mA
Fast Page Mode
(2,3,4)
Cycling tPC = tPC (min.) -60 — 80
Average Power Supply Current
ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 — 160 mA
RAS-Only
(2,3)
tRC = tRC (min.) -60 — 145
Average Power Supply Current
ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -50 — 160 mA
CBR
(2,3,5)
tRC = tRC (min.) -60 — 145
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
REF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
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Rev. A
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IS41C16105
IS41LV16105 ISSI
®
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 84 — 104 — ns
tRAC Access Time from RAS
(6, 7)
— 50 — 60 ns
tCAC Access Time from CAS
(6, 8, 15)
— 13 — 15 ns
tAA Access Time from Column-Address
(6)
— 25 — 30 ns
tRAS RAS Pulse Width 50 10K 60 10K ns
tRP RAS Precharge Time 30 — 40 — ns
tCAS CAS Pulse Width
(26)
8 10K 10 10K ns
tCP CAS Precharge Time
(9, 25)
9 — 9 — ns
tCSH CAS Hold Time
(21)
38 — 40 — ns
tRCD RAS to CAS Delay Time
(10, 20)
12 37 14 45 ns
tASR Row-Address Setup Time 0 — 0 — ns
tRAH Row-Address Hold Time 8 — 10 — ns
tASC Column-Address Setup Time
(20)
0 — 0 — ns
tCAH Column-Address Hold Time
(20)
8 — 10 — ns
tAR Column-Address Hold Time 30 — 40 — ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time
(11)
10 25 12 30 ns
tRAL Column-Address to RAS Lead Time 25 — 30 — ns
tRPC RAS to CAS Precharge Time 5 — 5 — ns
tRSH RAS Hold Time
(27)
8 — 10 — ns
tRHCP RAS Hold Time from CAS Precharge 37 — 37 — ns
tCLZ CAS to Output in Low-Z
(15, 29)
0 — 0 — ns
tCRP CAS to RAS Precharge Time
(21)
5 — 5 — ns
tOD Output Disable Time
(19, 28, 29)
315 315 ns
tOE Output Enable Time
(15, 16)
— 13 — 15 ns
tOED Output Enable Data Delay (Write) 20 — 20 — ns
tOEHC OE HIGH Hold Time from CAS HIGH 5 — 5 — ns
tOEP OE HIGH Pulse Width 10 — 10 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns
tRCS Read Command Setup Time
(17, 20)
0 — 0 — ns
tRRH Read Command Hold Time 0 — 0 — ns
(referenced to RAS)
(12)
tRCH Read Command Hold Time 0 — 0 — ns
(referenced to CAS)
(12, 17, 21)
tWCH Write Command Hold Time
(17, 27)
8 — 10 — ns
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
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IS41C16105
IS41LV16105 ISSI
®
AC CHARACTERISTICS (Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
t
WCR Write Command Hold Time 40 — 50 — ns
(referenced to RAS)
(17)
tWP Write Command Pulse Width
(17)
8 — 10 — ns
tWPZ WE Pulse Widths to Disable Outputs 10 — 10 — ns
tRWL Write Command to RAS Lead Time
(17)
13 — 15 — ns
tCWL Write Command to CAS Lead Time
(17, 21)
8 — 10 — ns
tWCS Write Command Setup Time
(14, 17, 20)
0 — 0 — ns
tDHR Data-in Hold Time (referenced to RAS)39— 39 — ns
tACH Column-Address Setup Time to CAS 15 — 15 — ns
Precharge during WRITE Cycle
tOEH OE Hold Time from WE during 8 — 10 — ns
READ-MODIFY-WRITE cycle
(18)
tDS Data-In Setup Time
(15, 22)
0 — 0 — ns
tDH Data-In Hold Time
(15, 22)
8 — 10 — ns
tRWC READ-MODIFY-WRITE Cycle Time 108 — 133 — ns
tRWD RAS to WE Delay Time during 64 — 77 — ns
READ-MODIFY-WRITE Cycle
(14)
tCWD CAS to WE Delay Time
(14, 20)
26 — 32 — ns
tAWD Column-Address to WE Delay Time
(14)
39 — 47 — ns
tPC Fast Page Mode READ or WRITE 20 — 25 — ns
Cycle Time
(24)
tRASP RAS Pulse Width 50 100K 60 100K ns
tCPA Access Time from CAS Precharge
(15)
— 30 — 35 ns
tPRWC READ-WRITE Cycle Time
(24)
56 — 68 — ns
tCOH Data Output Hold after CAS LOW 5 — 5 — ns
tOFF Output Buffer Turn-Off Delay from 1.6 12 1.6 15 ns
CAS or RAS
(13,15,19, 29)
tWHZ Output Disable Delay from WE 310 310 ns
tCLCH Last CAS going LOW to First CAS 10 — 10 — ns
returning HIGH
(23)
tCSR CAS Setup Time (CBR REFRESH)
(30, 20)
5 — 5 — ns
tCHR CAS Hold Time (CBR REFRESH)
(30, 21)
8 — 10 — ns
tORD OE Setup Time prior to RAS during 0 — 0 — ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period (1,024 Cycles) — 16 — 16 ms
tT Transition Time (Rise or Fall)
(2, 3)
150 150 ns
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Rev. A
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IS41C16105
IS41LV16105 ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
REF refresh requirement is exceeded.
2. V
IH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
V
IL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
4. If CAS and RAS = V
IH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
RCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
8. Assumes that t
RCD • tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer, CAS and RAS must be pulsed for t
CP.
10. Operation with the t
RCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified t
RCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified t
RAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either t
RCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. t
WCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • t RWD (MIN),
tAWD • t AWD (MIN) and tCWD • t CWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to V
IH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after t
OEH is met.
19. The I/Os are in open during READ cycles once t
OD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
10
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Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
FAST-PAGE-MODE READ CYCLE
Note:
1. t
OFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS
tRC
tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP
tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC
tOFF
(1)
tRAC
tCLC
tOES
tOE tOD
Don’t Care
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Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
OUT
tAR
tRWD
tAWD
I/O0-I/O15
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Column Column
tAR
tCSH
tCAS tCAS tCAS
tRASP
tRSHtPRWC
tRCD
tCWD tCWD tCWD
tCRP
tASR
tRAD
tRCS
tASC
tASC
tASC
tRAL
tCAH
tCP tCP
tRP
tCAH
tAWD tAWD
tCAC
tAA
tDH
tCLZ
tRAC
tDH tDH
tOEA
tCLZ
tCAC
tOEA
tCAC
tOEA
OUT
OUT ININ IN
tOEZ tOEZ
tOED tOED
tDS
tOEZ
tOED
tDStCLZ
tAA
tAA
tWP
tRAH
tWP
tWP
tCWL
tCWL
tCWL
tRWL
tCPWD
tCPWD
tCAH
tCRP
tDS
Don’t Care
12
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Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O
Open Open
Valid D
OUT
Valid D
IN
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
FAST PAGE MODE EARLY WRITE CYCLE
tAR
I/O0-I/O15
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Column Column
tAR
tCWL
tWCR
tDHR
tCSH
tCAS tCAS tCAS
tRASP
tRSH
tRHCP
tPC
tRCD
tCRP
tASR
tWCS
tDS
tRAD
tASC
tASC
tASC
tRAL
tCAH
tWCH
tDH
tDS
tDS
tDH tDH
tCP
tCP
tRP
tCAH
tRAH
tCAH
tCRP
tCWL
tWCS
tWCS
tWCH
tWP tWP
tCWL
tWCH
tWP
Valid DIN Valid DIN
Valid DIN
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
AC WAVEFORMS
READ CYCLE
(With WE-Controlled Disable)
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column
Open Open
Valid Data
tCSH
tCAS
tCRP
tRCD tCP
tRAHtASR
tRCH tRCStRCS
tAA
tCAC
tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
UCAS/LCAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don’t Care
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
HIDDEN REFRESH CYCLE
(1)
(WE = HIGH; OE = LOW)
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. t
OFF
is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RAS
t
RP
t
RP
I/O
UCAS/LCAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
UCAS/LCAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS
Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O
Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
ORDERING INFORMATION : 5V
Commercial Range: 0
⋅⋅
⋅⋅
⋅C to 70
⋅⋅
⋅⋅
⋅C
Speed (ns) Order Part No. Package
50 IS41C16105-50K 400-mil SOJ
IS41C16105-50T 400-mil TSOP (Type II)
60 IS41C16105-60K 400-mil SOJ
IS41C16105-60T 400-mil TSOP (Type II)
Extended Range: -30
⋅⋅
⋅⋅
⋅C to 85
⋅⋅
⋅⋅
⋅C
Speed (ns) Order Part No. Package
50 IS41C16105-50KE 400-mil SOJ
IS41C16105-50TE 400-mil TSOP (Type II)
60 IS41C16105-60KE 400-mil SOJ
IS41C16105-60TE 400-mil TSOP (Type II)
Industrial Range: -40
⋅⋅
⋅⋅
⋅C to 85
⋅⋅
⋅⋅
⋅C
Speed (ns) Order Part No. Package
50 IS41C16105-50KI 400-mil SOJ
IS41C16105-50TI 400-mil TSOP (Type II)
60 IS41C16105-60KI 400-mil SOJ
IS41C16105-60TI 400-mil TSOP (Type II)
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/03/00
IS41C16105
IS41LV16105 ISSI
®
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION : 3.3V
Commercial Range: 0
⋅⋅
⋅⋅
⋅C to 70
⋅⋅
⋅⋅
⋅C
Speed (ns) Order Part No. Package
50 IS41LV16105-50K 400-mil SOJ
IS41LV16105-50T 400-mil TSOP (Type II)
60 IS41LV16105-60K 400-mil SOJ
IS41LV16105-60T 400-mil TSOP (Type II)
Extended Range: -30
⋅⋅
⋅⋅
⋅C to 85
⋅⋅
⋅⋅
⋅C
Speed (ns) Order Part No. Package
50 IS41LV16105-50KE 400-mil SOJ
IS41LV16105-50TE 400-mil TSOP (Type II)
60 IS41LV16105-60KE 400-mil SOJ
IS41LV16105-60TE 400-mil TSOP (Type II)
Industrial Range: -40
⋅⋅
⋅⋅
⋅C to 85
⋅⋅
⋅⋅
⋅C
Speed (ns) Order Part No. Package
50 IS41LV16105-50KI 400-mil SOJ
IS41LV16105-50TI 400-mil TSOP (Type II)
60 IS41LV16105-60KI 400-mil SOJ
IS41LV16105-60TI 400-mil TSOP (Type II)
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