ISSI IS41LV16100A User Manual

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IS41LV16100A ISSI

1M x 16 (16-MBIT) DYNAMIC RAM

®

WITH EDO PAGE MODE

FEATURES

• TTL compatible inputs and outputs; tristate I/O

• Refresh Interval:

— Auto refresh Mode

—

RAS-Only, CAS-before-RAS (CBR), and Hidden

• JEDEC standard pinout

• Single power supply:
— 3.3V ± 10% (IS41LV16100A)

• Byte Write and Byte Read operation via two CAS

• Industrial Temperature Range: -40

• Lead-free available

PIN CONFIGURATIONS

50(44)-Pin TSOP (Type II) 42-Pin SOJ

: 1,024 cycles /16 ms

o

C to +85oC

MARCH 2005

DESCRIPTION

The ISSI IS41LV16100A is 1,048,576 x 16-bit high-perfor-
mance CMOS Dynamic Random Access Memories. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1,024 random ac­cesses within a single row with access cycle time as short
as 20 ns per 16-bit word.

These features make the IS41LV16100A ideally suited for
high-bandwidth graphics, digital signal processing, high ­performance computing systems, and peripheral
applications.

The IS41LV16100A is packaged in a 42-pin 400-mil SOJ
and 400-mil 50- (44-) pin TSOP (Type II).

KEY TIMING PARAMETERS

Parameter -50 -60 Unit

Max. RAS Access Time (tRAC) 5060ns
Max. CAS Access Time (tCAC) 1415ns
Max. Column Address Access Time (tAA)2530ns

VDD

I/O0
I/O1
I/O2
I/O3

VDD

I/O4
I/O5
I/O6
I/O7

NC

NC
NC

WE

RAS

NC
NC

VDD

1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16
17

A0

18

A1

19

A2

20

A3

21
22

44

GND

43

I/O15

42

I/O14

41

I/O13

40

I/O12

39

GND

38

I/O11

37

I/O10

36

I/O9

35

I/O8

34

NC

33

NC

32

LCAS

31

UCAS

30

OE

29

A9

28

A8

27

A7

26

A6

25

A5

24

A4

23

GND

VDD

I/O0
I/O1
I/O2
I/O3

VDD

I/O4
I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC
NC

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42

GND

41

I/O15

40

I/O14

39

I/O13

38

I/O12

37

GND

36

I/O11

35

I/O10

34

I/O9

33

I/O8

32

NC

31

LCAS

30

UCA

29

OE

28

A9

27

A8

26

A7

25

A6

24

A5

23

A4

22

GND

Min. EDO Page Mode Cycle Time (tPC)3040ns
Min. Read/Write Cycle Time (tRC) 85 110 n s

PIN DESCRIPTIONS

A0-A9 Address Inputs
I/O0-15 Data Inputs/Outputs

WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe

VDD Power
GND Ground
N C No Connection

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. B

03/02/05

1-800-379-4774

1

IS41LV16100A

E

L

FUNCTIONAL BLOCK DIAGRAM

O
WE

®

ISSI

CAS

UCAS

RAS

A0-A9

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS

BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

1,048,576 x 16

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O15

DATA I/O BUFFERS

2

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. B

03/02/05

IS41LV16100A

TRUTH TABLE

®

ISSI

Function

RASRAS

RAS

RASRAS

LCASLCAS

LCAS

LCASLCAS

UCASUCAS

UCAS

UCASUCAS

WEWE

WE

WEWE

OEOE

OE Address tR/t

OEOE

C

I/O

Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL D
Read: Lower Byte L L H H L ROW/COL Lower Byte, D

OUT

OUT

Upper Byte, High-Z

Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z

Upper Byte, D

Write: Word (Early Write) L L L L X ROW/COL D

IN

Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, D

OUT

IN

Upper Byte, High-Z

Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z

Read-Write
EDO Page-Mode Read

(1,2)

LLLH→LL→H ROW/COL D

(2)

1st Cycle: L H→LH→L H L ROW/COL D
2nd Cycle: L H→LH→L H L NA/COL D
Any Cycle: L L→HL→H H L NA/NA D

EDO Page-Mode Write

(1)

1st Cycle: L H→LH→L L X ROW/COL D
2nd Cycle: L H→LH→L L X NA/COL D

EDO Page-Mode

(1,2)

1st Cycle: L H→LH→LH→LL→H ROW/COL D

Read-Write 2nd Cycle: L H→LH→LH→LL→H NA/COL D

Write

(1,3)

(2)

L→H→L L L H L ROW/COL D
L→H→L L L L X ROW/COL D

Hidden Refresh Read

Upper Byte, D

OUT

, D

OUT
OUT
OUT

IN
IN

OUT

, D

OUT

, D

OUT
OUT

IN

IN

IN
IN

RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

(4)

H→L L L X X X High-Z

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Rev. B

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3

IS41LV16100A

®

ISSI

Functional Description

The IS41LV16100A is a CMOS DRAM optimized for
speed bandwidth,
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS).
and CAS is used to latch the latter nine bits.

The IS41LV16100A has two CAS controls, LCAS and

UCAS.
CAS signal functioning in an identical manner to the single CAS

input on the other 1M x 16 DRAMs.
each CAS controls its corresponding I/O tristate logic (
conjunction with OE and WE and RAS). LCAS controls I/O0
through I/O7 and UCAS controls I/O8 through I/O15.

The IS41LV16100A CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16100A both BYTE READ and BYTE WRITE cycle
capabilities.

The LCAS and UCAS inputs internally generates a

low power applications. During READ or

RAS is used to latch the first nine bits

The key difference is that

high-

in

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs first.

Auto Refresh Cycle

To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1,024 row addresses (A0 through A9)
with RAS at least once every 128 ms. Any read, write, read-
modify-write or RAS-only cycle refreshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad­dresses and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.

In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There­fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.

In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.

The EDO page mode allows both read and write opera­tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.

Power-On

After application of the VDD supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain­ing a RAS signal).

During power-on, it is recommended that RAS track with
VDD or be held at a valid VIH to avoid current surges.

4

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Rev. B

03/02/05

IS41LV16100A

®

ISSI

ABSOLUTE MAXIMUM RATINGS

Symbol Parameters Rating Unit

VT Voltage on Any Pin Relative to GND 3.3V –0.5 to +4.6 V
VDD Supply Voltage 3.3V –0.5 to +4.6 V
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Commercial Operation Temperature 0 to +70 °C

Industrial Operation Temperature -40 to +85 ° C

TSTG Storage Temperature –55 to +125 ° C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

(1)

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VDD Supply Voltage 3.3V 3.0 3.3 3.6 V

VIH Input High Voltage 3.3V 2.0 — VDD + 0.3 V
VIL Input Low Voltage 3.3V –0.3 — 0.8 V

TA Commercial Ambient Temperature 0 — 70 °C

Industrial Ambient Temperature –4 0 — 85 °C

CAPACITANCE

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A9 5 pF
CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

(1,2)

A = 25°C, f = 1 MHz.

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Rev. B

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IS41LV16100A

®

ISSI

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IL Input Leakage Current Any input 0V ≤ VIN ≤ VDD –10 10 µA

I

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) –1 0 10 µA

0V ≤ VOUT ≤ VDD
VOH Output High Voltage Level IOH = –2.0 mA (3.3V) 2.4 — V
VOL Output Low Voltage Level IOL = 2.0 mA (3.3V) — 0.4 V
ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commercial 3.3V — 3 mA

Industrial 3.3V — 4 mA
ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VDD – 0.2V 3.3V — 2 mA
I

CC3 Operating Current: RAS, LCAS, UCAS, -50 — 180 mA

Random Read/Write

(2,3,4)

Address Cycling, tRC = tRC (min.) -6 0 — 170

Average Power Supply Current

ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -50 — 180 mA

EDO Page Mode

(2,3,4)

Cycling tPC = tPC (min.) -60 — 170

Average Power Supply Current

ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 — 180 mA

RAS-Only

(2,3)

tRC = tRC (min.) -6 0 — 17 0

Average Power Supply Current

ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -50 — 18 0 mA

(2,3,5)

CBR

tRC = tRC (min.) -6 0 — 17 0

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

REF refresh requirement is exceeded.

6

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1-800-379-4774

Rev. B

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IS41LV16100A

®

ISSI

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50 -60

Symbol Parameter Min. Max. Min. Max. Units

tRC Random READ or WRITE Cycle Time 85 — 11 0 — ns
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Column-Address

(6, 7)

(6, 8, 15)

—50 —60 ns
—14 —15 ns

(6)

—25 —30 ns
tRAS RAS Pulse Width 5 0 10K 6 0 10K ns
tRP RAS Precharge Time 3 0 — 4 0 — ns

(21)

(26)

(9, 25)

(10, 20)

8 10K 10 10K ns

9— 10— ns
50 — 60 — ns
12 37 20 45 ns

tCAS CAS Pulse Width
tCP CAS Precharge Time
tCSH CAS Hold Time
tRCD RAS to CAS Delay Time
tASR Row-Address Setup Time 0 — 0 — ns
tRAH Row-Address Hold Time 8 — 10 — ns

(20)

(20)

0— 0— ns

8— 10— ns

tASC Column-Address Setup Time
tCAH Column-Address Hold Time
tAR Column-Address Hold Time 30 — 4 0 — ns

(referenced to RAS)

tRAD RAS to Column-Address Delay Time

(11)

14 25 15 30 ns

tRAL Column-Address to RAS Lead Time 2 5 — 30 — ns
tRPC RAS to CAS Precharge Time 5 — 5 — ns
tRSH RAS Hold Time
tCLZ CAS to Output in Low-Z
tCRP CAS to RAS Precharge Time
tOD Output Disable Time
tOE/tOEA Output Enable Time

(27)

(15, 29)

(19, 28, 29)

(15, 16)

(21)

14 — 15 — ns

0— 0— ns

5— 5— ns

312 312 ns
—14 —15 ns

tOEHC OE HIGH Hold Time from CAS HIGH 1 5 — 1 5 — ns
tOEP OE HIGH Pulse Width 1 0 — 10 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns
tRCS Read Command Setup Time

(17, 20)

0— 0— ns

tRRH Read Command Hold Time 0 — 0 — ns

(referenced to RAS)

(12)

tRCH Read Command Hold Time 0 — 0 — ns

(referenced to CAS)

tWCH Write Command Hold Time

(12, 17, 21)

(17, 27)

8— 10— ns

tWCR Write Command Hold Time 4 0 — 50 — ns

(referenced to RAS)

(17)

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