ISSI IS41C85120A, IS41LV85120A User Manual

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IS41C85120A

IS41LV85120A ISSI

512K x 8 (4-MBIT) DYNAMIC RAM

APRIL 2005

WITH EDO PAGE MODE

®

FEATURES

• TTL compatible inputs and outputs

• Refresh Interval: 1024 cycles/16 ms

• Refresh Mode : RAS-Only, CAS-before-RAS (CBR),
and Hidden

• JEDEC standard pinout

• Single power supply
5V ± 10% (IS41C85120A)

3.3V ± 10% (IS41LV85120A)

• Lead-free available

KEY TIMING PARAMETERS

Parameter -60 Unit

Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)

60 ns
15 ns
30 ns
40 ns

110 ns

PIN DESCRIPTIONS

A0-A9 Address Inputs
I/O0-I/O7 Data Inputs/Outputs

WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe

VCC Power
GND Ground

DESCRIPTION

The

ISSI

IS41C85120A and IS41LV85120A are 524,288 x 8­bit high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access EDO
Page Mode. EDO Page Mode allows 512 random accesses
within a single row with access cycle time as short as 10ns per
8-bit word. The Byte Write control, of upper and lower byte,
makes the IS41C85120A and IS41LV85120A ideal for use in
16 and 32-bit wide data bus systems.

These features make the IS41C85120A and IS41LV85120A
ideally

suited for high
processing, high-performance computing systems, and periph­eral applications.

The IS41C85120A and IS41LV85120A are available in a
28-pin, 400-mil SOJ package.

band-width

graphics,

digital signal

PIN CONFIGURATION
28-Pin SOJ

VCC
I/O0
I/O1
I/O2
I/O3

NC

WE

RAS

A9
A0
A1
A2
A3

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

GND
I/O7
I/O6
I/O5
I/O4

CAS
OE

NC
A8
A7
A6
A5
A4
GND

NC No Connection

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

1

IS41C85120A

E

IS41LV85120A ISSI

FUNCTIONAL BLOCK DIAGRAM

O
WE

®

CAS

RAS

A0-A9

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS

BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

COLUMN DECODERS

SENSE AMPLIFIERS

ROW DECODER

OE

CONTROL

LOGIC

OE

DATA I/O BUS

I/O0-I/O7

DATA I/O BUFFERS

MEMORY ARRAY

524,288 x 8

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

IS41C85120A

IS41LV85120A ISSI

TRUTH TABLE

®

Function

RASRAS

RAS

RASRAS

CASCAS

CAS

CASCAS

WEWE

WE

WEWE

OEOE

OE Address tR/tC I/O

OEOE

Standby H H X X X High-Z
Read: Word L L H L ROW/COL DOUT
Read: Lower Byte L L H L ROW/COL Lower Byte, DOUT

Upper Byte, High-Z

Read: Upper Byte L H H L ROW/COL Lower Byte, High-Z

Upper Byte, DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L L X ROW/COL Lower Byte, DIN

Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L X ROW/COL Lower Byte, High-Z

Upper Byte, DIN
Read-Write
EDO Page-Mode Read

(1,2)

LLH→LL→H ROW/COL DOUT, DIN

(2)

1st Cycle: L H→L H L ROW/COL

DOUT

2nd Cycle: L H→L H L NA/COL DOUT
Any Cycle: L L→H H L NA/NA DOUT

EDO Page-Mode Write

(1)

1st Cycle: L H→L L X ROW/COL DIN

2nd Cycle: L H→L L X NA/COL DIN

EDO Page-Mode 1st Cycle: L H→LH→LL→H ROW/COL
DOUT, DIN
Read-Write

Hidden Refresh

(1,2)

2nd Cycle: L H→LH→LL→H NA/COL DOUT, DIN

2)

Read L→H→L L H L ROW/COL

DOUT

Write L→H→L L L X ROW/COL

DOUT
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. At least one of the two CAS signals must be active (LCAS or UCAS).

(3)

H→L L X X X High-Z

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

3

IS41C85120A

IS41LV85120A ISSI

®

Functional Description

The IS41C85120A and IS41LV85120A is a CMOS DRAM
optimized for high-speed bandwidth, low power applica­tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 19 address bits. The first ten
address bits (A0-A9) are entered as row address and
latter nine bits nine address bits (A0-A8) are entered as
column address. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter nine bits.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci­fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever
occurs last.

CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

Extended Data Out Page Mode

EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.

In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. There­fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.

In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.

The EDO page mode allows both read and write opera­tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.

Power-On

After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial­ization cycles (any combination of cycles containing a
RAS signal).

During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.

Refresh Cycle

To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re­freshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ig­nored.

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

IS41C85120A

IS41LV85120A ISSI

®

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V

3.3V -0.5 to 4.6 V

CC Supply Voltage 5V –1.0 to +7.0 V

V

3.3V -0.5 to 4.6 V
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Commercial Operation Temperature 0 to +70 °C
TSTG Storage Temperature –55 to +125 ° C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 5V 4.5 5.0 5.5 V

3.3V 3.0 3.3 3.6

VIH Input High Voltage 5V 2.4 — VCC + 1.0 V

3.3V 2.0 — VCC + 0.3

VIL Input Low Voltage 5V –1.0 — 0.8 V

3.3V –0.3 — 0.8

TA Commercial Ambient Temperature 0 — 7 0 °C

CAPACITANCE

(1,2)

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A9 5 pF
CIN2 Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O7 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz,

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

5

IS41C85120A

IS41LV85120A ISSI

®

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –10 10 µA

I

Other inputs not under test = 0V

I

IO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA

0V ≤ VOUT ≤ Vcc
VOH Output High Voltage Level IOH = –2 mA 2.4 — V
VOL Output Low Voltage Level IOL = +2 mA — 0.4 V
ICC1 Stand-by Current: TTL RAS, CAS ≥ VIH Commercial 5V — 2 mA
ICC1 Stand-by Current: TTL RAS, CAS ≥ VIH Commercial 3V — 2 mA

CC2 Stand-by Current: CMOS RAS, CAS ≥ VCC – 0.2V 5V — 2 mA

I

3V — 2

ICC3 Operating Current: RAS, CAS, -60 — 170 mA

Random Read/Write
Average Power Supply Current

ICC4 Operating Current: RAS = VIL, CAS, -60 — 170 mA

EDO Page Mode
Average Power Supply Current

(2,3,4)

(2,3,4)

Address Cycling, tRC = tRC (min.)

Cycling tPC = tPC (min.)

ICC5 Refresh Current: RAS Cycling, CAS ≥ VIH -60 — 170 mA

RAS-Only

(2,3)

tRC = tRC (min.)

Average Power Supply Current

ICC6 Refresh Current: RAS, CAS Cycling -60 — 170 mA

(2,3,5)

CBR

tRC = tRC (min.)

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

REF refresh requirement is exceeded.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

IS41C85120A

IS41LV85120A ISSI

®

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-60

Symbol Parameter Min. Max. Units

tRC Random READ or WRITE Cycle Time 11 0 — ns

(26)

(9, 25)

(6, 7)

(6, 8, 15)

(10, 20)

(20)

(20)

60 — ns
—15 ns

(6)

—30 ns

10 10K ns
10 — ns
60 — ns
20 45 ns

0— ns

10 — ns

tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Column-Address
tRAS RAS Pulse Width 6 0 10K ns
tRP RAS Precharge Time 40 — ns
tCAS CAS Pulse Width
tCP CAS Precharge Time
tCSH CAS Hold Time

(21)

tRCD RAS to CAS Delay Time
tASR Row-Address Setup Time 0 — ns
tRAH Row-Address Hold Time 10 — ns
tASC Column-Address Setup Time
tCAH Column-Address Hold Time
tAR Column-Address Hold Time 40 — ns

(referenced to RAS)

tRAD RAS to Column-Address Delay Time

(11)

15 30 ns
tRAL Column-Address to RAS Lead Time 3 0 — ns
tRPC RAS to CAS Precharge Time 5 — ns
tRSH RAS Hold Time
tCLZ CAS to Output in Low-Z
tCRP CAS to RAS Precharge Time
tOD Output Disable Time
tOE / tOEA Output Enable Time

(27)

(15, 29)

(19, 28, 29)

(15, 16)

(21)

15 10K ns

0— ns
5— ns
312 ns

—15 ns
tOEHC OE HIGH Hold Time from CAS HIGH 1 5 — ns
tOEP OE HIGH Pulse Width 1 0 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — ns
tRCS Read Command Setup Time

(17, 20)

0— ns

tRRH Read Command Hold Time 0 — ns

(referenced to RAS)

(12)

tRCH Read Command Hold Time 0 — ns

(referenced to CAS)

tWCH Write Command Hold Time

(12, 17, 21)

(17, 27)

10 — ns
tWCR Write Command Hold Time 5 0 — ns

(referenced to RAS)

(17)

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

04/22/05

7