ISSI IS41C16257, IS41LV16257 User Manual

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IS41C16257

®

IS41LV16257

256K x 16 (4-MBIT) DYNAMIC RAM
WITH F AST PAGE MODE

FEATURES

• Fast access and cycle time

• TTL compatible inputs and outputs

• Refresh Interval: 512 cycles/8 ms

•

Refresh Mode:
and Hidden

• JEDEC standard pinout

• Single power supply:

-- 5V ± 10% (IS41C16257)

-- 3.3V ± 10% (IS41LV16257)

• Byte Write and Byte Read operation via two

• Industrial temperature available

RAS

-Only,

CAS

-before-

RAS

(CBR),

CAS

DESCRIPTION

The ISSI IS41C16257 and the IS41LV16257 are 262,144
x 16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 512 random accesses
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
byte, makes these devices ideal for use in 16- and 32-bit
wide data bus systems.

These features make the IS41C16257 and the IS41LV16257
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.

The IS41C16257 and the IS41LV16257 are packaged in a
40-pin, 400-mil SOJ and TSOP (Type II).

ISSI

MAY 1999

KEY TIMING PARAMETERS

Parameter -35 -60 Unit

Max.

RAS

Access Time (tRAC)3560ns

Max.

CAS

Access Time (tCAC)1015ns
Max. Column Address Access Time (tAA)1830ns
Min. Fast Page Mode Cycle Time (tPC)1225ns
Min. Read/Write Cycle Time (tRC) 60 110 ns

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

DR004-1B
05/24/99

1

IS41C16257
IS41LV16257

FUNCTIONAL BLOCK DIAGRAM

OE
WE

®

ISSI

LCAS
UCAS

RAS

A0-A8

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS
BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

262,144 x 16

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O15

DATA I/O BUFFERS

PIN CONFIGURATIONS
40-Pin TSOP (Type II)

VCC

I/O0
I/O1
I/O2
I/O3

VCC

I/O4
I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC

A0
A1
A2
A3

VCC

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31

30
29
28
27
26
25
24
23
22
21

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8

NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND

40-Pin SOJ

1

VCC

2

I/O0

3

I/O1

4

I/O2

5

I/O3

6

VCC

7

I/O4

8

I/O5

9

I/O6

10

I/O7

11

NC

12

NC

13

WE

14

RAS

15

NC

16

A0

17

A1

18

A2

19

A3

20

VCC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND

PIN DESCRIPTIONS

A0-A8 Address Inputs
I/O0-I/O15 Data Inputs/Outputs

WE
OE
RAS

UCAS Upper Column Address

LCAS

Vcc Power
GND Ground
NC No Connection

Write Enable
Output Enable
Row Address Strobe

Strobe
Lower Column Address

Strobe

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

DR004-1B

05/24/99

IS41C16257
IS41LV16257

TRUTH TABLE

®

ISSI

Function

Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT

Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z

Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN

Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z

Read-Write
Hidden Refresh

RAS

CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either

2. These READ cycles may also be BYTE READ cycles (either

3. At least one of the two CAS signals must be active (

(1,2)

2)

-Only Refresh L H H X X ROW/NA High-Z

(3)

Read L→H→L L L H L ROW/COL DOUT

Write L→H→LLLLXROW/COLDOUT

RASRAS

RAS

RASRAS

LLLH→LL→H ROW/COL DOUT, DIN

H→L L L X X X High-Z

LCASLCAS

LCAS

LCASLCAS

LCAS

UCASUCAS

UCAS

UCASUCAS

LCAS

or

UCAS

LCAS

WEWE

WE

WEWE

or

).

or

UCAS

OEOE

OE

OEOE

UCAS

active).

Address tR/tC I/O

Upper Byte, High-Z

Upper Byte, DOUT

Upper Byte, High-Z

Upper Byte, DIN

active).

Integrated Silicon Solution, Inc. — 1-800-379-4774

DR004-1B
05/24/99

3

IS41C16257
IS41LV16257

FUNCTIONAL DESCRIPTION

®

ISSI

The IS41C16257 and the IS41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (
latched by the Column Address Strobe (
to latch the first nine bits and
nine bits.

The IS41C16257 and the IS41LV16257 has two
controls,
internally generate a
manner to the single
DRAMs. The key difference is that each
corresponding I/O tristate logic (in conjunction with OE and

WE

controls I/O8 - I/O15.
The IS41C16257 and the IS41LV16257

determined by the first
LOW and the last transitioning back HIGH. The two
controls give the IS41C16257 both BYTE READ and BYTE
WRITE cycle capabilities.

and

LCAS

RAS

).

and

LCAS

RAS

). The column address is

CAS

).

RAS

CAS

is used to latch the latter

UCAS

. The

LCAS

and

UCAS

CAS

signal functioning in an identical

CAS

input on the other 256K x 16

CAS

controls its

controls I/O0 - I/O7 and

CAS

function is

CAS (LCAS

or

UCAS

) transitioning

is used

CAS

inputs

UCAS

CAS

Memory Cycle

A memory cycle is initiated by bringing
terminated by returning both
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tRAS time has expired. A new cycle
must not be initiated until the minimum precharge time tRP,
tCP has elapsed.

RAS

RAS

and

LOW and it is

CAS

HIGH. To

on the timing relationships between these parameters.

Write Cycle

A write cycle is initiated by the falling edge of
whichever occurs last. The input data must be valid at or
before the falling edge of

CAS

or WE, whichever occurs last.

CAS

and WE,

Refresh Cycle

To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:

1. By clocking each of the 512 row addresses (A0 through
A8) with
read-modify-write or
dressed row.

2. Using a

RAS

holding
internal 9-bit counter provides the row addresses and the

external address inputs are ignored.

CAS

-before­or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.

RAS

at least once every 8 ms. Any read, write,

RAS

-only cycle refreshes the ad-

CAS

-before-

refresh is activated by the falling edge of

CAS

LOW. In

RAS

is a refresh-only mode and no data access

RAS

refresh cycle.

CAS

-before-

CAS

RAS

refresh cycle, an

-before-

RAS

, while

Power-On

After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a

During power-on, it is recommended that
or be held at a valid VIH to avoid current surges.

RAS

RAS

track with VCC

signal).

Read Cycle

A read cycle is initiated by the falling edge of
whichever occurs last, while holding WE HIGH. The column
address must be held for a minimum time specified by tAR.
Data Out becomes valid only when tRAC, tAA, tCAC and tOEA
are all satisfied. As a result, the access time is dependent

4

CAS

or OE,

Integrated Silicon Solution, Inc. — 1-800-379-4774

DR004-1B

05/24/99

IS41C16257
IS41LV16257

®

ISSI

ABSOLUTE MAXIMUM RATINGS

Symbol Parameters Rating Unit

VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V

VCC Supply Voltage 5V –1.0 to +7.0 V

IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Operation Temperature Com. 0 to 70 °C

TSTG Storage Temperature –55 to +125 °C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

(1)

3.3V –0.5 t0 +4.6

3.3V –0.5 t0 +4.6

Ind. –40 to +85

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)

Symbol Parameter Voltage Min. Typ. Max. Unit

VCC Supply Voltage 5V 4.5 5.0 5.5 V
VCC Supply Voltage 3.3V 3.0 3.3 3.6 V

VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
VIH Input High Voltage 3.3V 2.0 — VCC + 0.3 V
VIL Input Low Voltage 5V –1.0 — 0.8 V
VIL Input Low Voltage 3.3 –0.3 — 0.8 V

TA Ambient Temperature Com. 0 — 70 °C

Ind. –40 — 85

CAPACITANCE

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A8 5 pF
CIN2 Input Capacitance:
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

Integrated Silicon Solution, Inc. — 1-800-379-4774

DR004-1B
05/24/99

(1,2)

RAS, UCAS, LCAS, WE, OE

A = 25°C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V ± 10%.

7pF

5

IS41C16257
IS41LV16257

®

ISSI

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current Any input 0V < VIN < Vcc –10 10 µA

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA

0V < VOUT < Vcc
VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V
VOL Output Low Voltage Level IOL = 2.1 mA — 0.4 V

ICC1 Stand-by Current: TTL

RAS, LCAS, UCAS

≥ VIH Com. 5V — 2 mA

Ind. 5V 3

ICC1 Stand-by Current: TTL

RAS, LCAS, UCAS

≥ VIH Com. 3.3V — 1 mA

Ind. 3.3V 2
ICC2 Stand-by Current: CMOS
ICC2 Stand-by Current: CMOS
ICC3 Operating Current:

Random Read/Write

(2,3,4)

RAS, LCAS, UCAS
RAS, LCAS, UCAS
RAS, LCAS, UCAS

≥ VCC – 0.2V 5V — 2 mA
≥ VCC – 0.2V 3.3V — 1 mA
, -35 — 230 mA

Address Cycling, tRC = tRC (min.) -60 — 170

Average Power Supply Current

ICC4 Operating Current:

Fast Page Mode

(2,3,4)

RAS

= VIL,

LCAS, UCAS

, -35 — 220 mA

Cycling tPC = tPC (min.) -60 — 160

Average Power Supply Current

ICC5 Refresh Current:

-Only

(2,3)

RAS

RAS

Cycling,

LCAS, UCAS

≥ VIH -35 — 230 mA

tRC = tRC (min.) -60 — 170

Average Power Supply Current

ICC6 Refresh Current:

(2,3,5)

CBR

RAS, LCAS, UCAS

Cycling -35 — 230 mA

tRC = tRC (min.) -60 — 170

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight

operation is assured.The eight

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each fast page cycle.

5. Enables on-chip refresh and address counters.

RAS

cycles wake-up should be repeated any time the t

RAS

refresh cycles (

RAS

-Only or CBR) before proper device

REF

refresh requirement is exceeded.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

DR004-1B

05/24/99