ISSI IS41C16128-60TI, IS41C16128-60T, IS41C16128-60K, IS41C16128-50TI, IS41C16128-50T Datasheet

IS41C16128

IS41C16128

ISSI

ISSI

®

®

128K x 16 (2-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE

FEATURES

•Extended Data-Out (EDO) Page Mode
access cycle

•TTL compatible inputs and outputs

•Refresh Interval: 512 cycles/8 ms

•Refresh Mode :

RAS

-Only,

CAS

-before-

RAS

(CBR), and Hidden

•JEDEC standard pinout

•Single +5V ± 10% power supply

•Byte Write and Byte Read operation via two

•Available in 40-pin SOJ and TSOP (Type II)

•Industrial temperature available

FUNCTIONAL BLOCK DIAGRAM

CAS

DESCRIPTION

The ISSI IS41C16128 is a 131,072 x 16-bit high-performance
CMOS Dynamic Random Access Memory. The IS41C16128
offers an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 256 random accesses within a
single row with access cycle time as short as 12 ns per 16­bit word. The Byte Write control, of upper and lower byte,
makes the IS41C16128 ideal for use in 16-, 32-bit wide data
bus systems.

These features make the IS41C16128 ideally suited for
high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.

The IS41C16128 is packaged in a 40-pin 400-mil SOJ and
TSOP (Type II).

AUGUST 1998

OE
WE

LCAS
UCAS

RAS

A0-A8

CAS

CLOCK

GENERATOR

RAS

CLOCK

GENERATOR

REFRESH
COUNTER

ADDRESS
BUFFERS

WE

CAS WE

RAS

CONTROL

LOGICS

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

131,072 x 16

ROW DECODER

OE

CONTROL

LOGIC

OE

I/O0-I/O15

DATA I/O BUFFERS

This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc.

PRELIMINARY DR002-1D

08/20/98

1

IS41C16128

KEY TIMING PARAMETERS

Parameter -35 -40 -45 -50 -60

Max.

RAS

Access Time (tRAC) 35 ns 40 ns 45 ns 50 ns 60 ns

Max.

CAS

Access Time (tCAC) 10 ns 12 ns 13 ns 14 ns 15 ns
Max. Column Address Access Time (tAA) 18 ns 20 ns 22 ns 25 ns 30 ns
Min. EDO Page Mode Cycle Time (tPC) 12 ns 15 ns 17 ns 20 ns 25 ns
Min. Read/Write Cycle Time (tRC) 60 ns 75 ns 80 ns 90 ns 110 ns

PIN CONFIGURATIONS

40-Pin TSOP (Type II)

40-Pin SOJ

®

ISSI

VCC

I/O0
I/O1
I/O2
I/O3

VCC

I/O4
I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC

A0
A1
A2
A3

VCC

1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31

30
29
28
27
26
25
24
23
22
21

PIN DESCRIPTIONS

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8

NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND

VCC

I/O0
I/O1
I/O2
I/O3

VCC

I/O4
I/O5
I/O6
I/O7

NC
NC

WE

RAS

NC

A0
A1
A2
A3

VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND

A0-A8 Address Inputs

I/O0-15 Data Inputs/Outputs

WE
OE
RAS
UCAS
LCAS

Write Enable

Output Enable

Row Address Strobe

Upper Column Address Strobe

Lower Column Address Strobe

Vcc Power
GND Ground
NC No Connection

2

Integrated Silicon Solution, Inc.

PRELIMINARY DR002-1D

08/20/98

IS41C16128

ISSI

TRUTH TABLE

Function

RASRAS

RAS

RASRAS

Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT

Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z

Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN

Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z

Read-Write
EDO Page-Mode Read

(1,2)

LLLH→LL→H ROW/COL DOUT, DIN

(2)

1st Cycle: L H→LH→L H L ROW/COL DOUT

2nd Cycle: L H→LH→L H L NA/COL DOUT

Any Cycle: L L→HL→H H L NA/NA DOUT

EDO Page-Mode Write

(1)

1st Cycle: L H→LH→L L X ROW/COL DIN

2nd Cycle: L H→LH→L L X NA/COL DIN

EDO Page-Mode 1st Cycle: L H→LH→LH→LL→H ROW/COL DOUT, DIN
Read-Write

Hidden Refresh

(1,2)

2nd Cycle: L H→LH→LH→LL→H NA/COL DOUT, DIN

2)

Read L→H→L L L H L ROW/COL DOUT
Write L→H→L L L L X ROW/COL DOUT

RAS

-Only Refresh L H H X X ROW/NA High-Z

CBR Refresh

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either

2. These READ cycles may also be BYTE READ cycles (either

3. At least one of the two

(3)

CAS

signals must be active (

H→L L L X X X High-Z

LCASLCAS

LCAS

LCASLCAS

LCAS

UCASUCAS

UCAS

UCASUCAS

or

LCAS
LCAS
UCAS

or

).

WEWE

WE

WEWE

or

UCAS

UCAS

active).

OEOE

OE

OEOE

active).

Address tR/tC I/O

Upper Byte, High-Z

Upper Byte, DOUT

Upper Byte, High-Z

Upper Byte, DIN

®

Integrated Silicon Solution, Inc.

PRELIMINARY DR002-1D

08/20/98

3

IS41C16128

®

ISSI

Functional Description

The IS41C16128 is a CMOS DRAM optimized for high­speed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 17 address bits. The row address is latched by the
Row Address Strobe (
latched by the Column Address Strobe (
used to latch the first nine bits and
latter nine bits.

The IS41C16128 has two
The

LCAS

and

UCAS

signal functioning in an identical manner to the single
input on the other 128K x 16 DRAMs. The key difference
is that each
logic (in conjunction with OE and WE and
controls I/O0 through I/O7 and
through I/O15.

The IS41C16128

CAS (LCAS

transitioning back HIGH. The two
IS41C16128 both BYTE READ and BYTE WRITE cycle
capabilities.

CAS

or

UCAS

RAS

). The column address is

CAS

).

RAS

is

CAS

is used to latch the

CAS

controls,

inputs internally generates a

controls its corresponding I/O tristate

CAS

function is determined by the first
) transitioning LOW and the last

LCAS

and

RAS

UCAS

controls I/O8

CAS

controls give the

UCAS

).

LCAS

CAS
CAS

Refresh Cycle

To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.

1. By clocking each of the 512 row addresses (A0 through
A8) with
read-modify-write or
dressed row.

2. Using a

.

RAS

while holding
cycle, an internal 9-bit counter provides the row ad­dresses and the external address inputs are ignored.

CAS

access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.

RAS

at least once every 8 ms. Any read, write,

RAS

-only cycle refreshes the ad-

CAS

-before-

refresh is activated by the falling edge of

CAS

-before-

RAS

is a refresh-only mode and no data

RAS

refresh cycle.

LOW. In

CAS

-before-

CAS

RAS

-before-

RAS

refresh

,

Extended Data Out Page Mode

EDO page mode operation permits all 256 columns within
a selected row to be randomly accessed at a high data
rate.

Memory Cycle

A memory cycle is initiated by bring
terminated by returning both
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.

RAS

RAS

and

CAS

LOW and it is

HIGH. To

Read Cycle

A read cycle is initiated by the falling edge of
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci­fied by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.

CAS

or OE,

Write Cycle

A write cycle is initiated by the falling edge of
whichever occurs last. The input data must be valid at or
before the falling edge of
last.

CAS

or WE, whichever occurs

CAS

and WE,

In EDO page mode read cycle, the data-out is held to the
next

CAS

cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
cycle time becomes shorter.

In EDO page mode, due to the extended data function, the

CAS

cycle time can be shorter than in the fast page mode

if the timing margin is the same.
The EDO page mode allows both read and write opera-

tions during one
equivalent to that of the fast page mode in that case.

CAS

cycle time becomes shorter. There-

RAS

cycle, but the performance is

CAS

Power-On

After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a

RAS

signal).

During power-on, it is recommended that
VCC or be held at a valid VIH to avoid current surges.

RAS

track with

4

Integrated Silicon Solution, Inc.

PRELIMINARY DR002-1D

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IS41C16128

®

ISSI

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

VT Voltage on Any Pin Relative to GND –1.0 to +7.0 V
VCC Supply Voltage –1.0 to +7.0 V
IOUT Output Current 50 mA
PD Power Dissipation 1 W
TA Operation Temperature Com. 0 to +70 °C

Ind. –40 to +85

TSTG Storage Temperature –55 to +125 °C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

VIH Input High Voltage 2.4 — VCC + 1.0 V
VIL Input Low Voltage –1.0 — +0.8 V

TA Ambient Temperature Com. 0 — +70 °C

Ind. –40 — +85

CAPACITANCE

(1,2)

Symbol Parameter Max. Unit

CIN1 Input Capacitance: A0-A8 5 pF
CIN2 Input Capacitance:

RAS, UCAS, LCAS, WE, OE

7pF

CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V + 10%.

Integrated Silicon Solution, Inc.

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IS41C16128

®

ISSI

ELECTRICAL CHARACTERISTICS

(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current Any input 0V < VIN < 5.5V –10 10 µA

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA

0V < VOUT < 5.5V
VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V
VOL Output Low Voltage Level IOL = +2.1 mA — 0.4 V

ICC1 Stand-by Current: TTL
ICC2 Stand-by Current: CMOS
ICC3 Operating Current:

Random Read/Write

(2,3,4)

RAS, LCAS, UCAS

RAS, LCAS, UCAS

RAS, LCAS, UCAS

≥ VIH —2mA
≥ VCC – 0.2V — 1 mA
, -35 — 230 mA

Address Cycling, tRC = tRC (min.) -40 — 130

Average Power Supply Current -45 — 120

-50 — 110

-60 — 100

ICC4 Operating Current:

EDO Page Mode

(2,3,4)

RAS

= VIL,

LCAS, UCAS

, -35 — 220 mA

Cycling tPC = tPC (min.) -40 — 90

Average Power Supply Current -45 — 85

-50 — 80

-60 — 70

ICC5 Refresh Current:

-Only

(2,3)

RAS

RAS

Cycling,

LCAS, UCAS

≥ VIH -35 — 230 mA

tRC = tRC (min.) -40 — 130

Average Power Supply Current -45 — 120

-50 — 100

-60 — 100

ICC6 Refresh Current:

(2,3,5)

CBR

RAS, LCAS, UCAS

Cycling -35 — 230 mA

tRC = tRC (min.) -40 — 130

Average Power Supply Current -45 — 120

-50 — 100

-60 — 100

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight
operation is assured. The eight

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

RAS

cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

RAS

refresh cycles (

6

RAS

-Only or CBR) before proper device

Integrated Silicon Solution, Inc.

PRELIMINARY DR002-1D

08/20/98

IS41C16128

®

ISSI

AC CHARACTERISTICS

(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-35 -40 -45 -50 -60

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

tRC Random READ or WRITE Cycle Time 60 — 75 — 80 — 90 — 110 — ns

(21)

RAS
CAS

(26)

(6, 7)
(6, 8, 15)

(9, 25)

(10, 20)

—35 —40 —45 —50 —60 ns
—10 —12 —13 —14 —15 ns

(6)

—18 —20 —22 —25 —30 ns

6 10K 6 10K 7 10K 8 10K 10 10K ns

5— 5— 7— 8— 10— ns
35 — 40 — 45 — 50 — 60 — ns
11 28 17 28 18 32 19 36 20 45 ns

tRAC Access Time from
tCAC Access Time from
tAA Access Time from Column-Address
tRAS
tRP
tCAS
tCP
tCSH
tRCD

RAS

Pulse Width 35 10K 40 10K 45 10K 50 10K 60 10K ns

RAS

Precharge Time 20 — 25 — 25 — 30 — 40 — ns

CAS

Pulse Width

CAS

Precharge Time

CAS

Hold Time

RAS

to

CAS

Delay Time
tASR Row-Address Setup Time 0 — 0 — 0 — 0 — 0 — ns
tRAH Row-Address Hold Time 6 — 6 — 7 — 8 — 10 — ns

(20)

(20)

0— 0— 0— 0— 0— ns
6— 6— 7— 8— 10— ns

tASC Column-Address Setup Time
tCAH Column-Address Hold Time
tAR Column-Address Hold Time 30 — 30 — 35 — 40 — 40 — ns

(referenced to

tRAD

RAS

to Column-Address Delay Time
tRAL Column-Address to
tRPC
tRSH
tCLZ
tCRP

RAS

to

RAS

Hold Time

CAS

to Output in Low-Z

CAS

to
tOD Output Disable Time
tOE Output Enable Time
tOEHC
tOEP
tOES

OE

HIGH Hold Time from

OE

HIGH Pulse Width 10 — 10 — 10 — 10 — 10 — ns

OE

LOW to

tRCS Read Command Setup Time

RAS

)

(11)

12 20 12 20 13 22 14 25 15 30 ns

RAS

Lead Time 18 — 20 — 22 — 25 — 30 — ns

CAS

Precharge Time 0 — 0 — 0 — 0 — 0 — ns

(27)

RAS

Precharge Time

(19, 28, 29)

(15, 16)

CAS

HIGH Setup Time 5 — 5 — 5 — 5 — 5 — ns

(15, 29)

(21)

CAS

HIGH 10 — 10 — 10 — 10 — 10 — ns

(17, 20)

8 — 12 — 13 — 14 — 15 — ns
3— 3— 3— 3— 3— ns
5— 5— 5— 5— 5— ns
315 315 315 315 315 ns

—10 —10 —12 —15 —15 ns

0— 0— 0— 0— 0— ns

tRRH Read Command Hold Time 0 — 0 — 0 — 0 — 0 — ns

(referenced to

RAS

(12)

)

tRCH Read Command Hold Time 0 — 0 — 0 — 0 — 0 — ns

(referenced to

tWCH Write Command Hold Time

CAS

(12, 17, 21)

)

(17, 27)

5— 6— 7— 8— 10— ns

tWCR Write Command Hold Time 30 — 30 — 35 — 40 — 50 — ns

(referenced to
tWP Write Command Pulse Width
tWPZ

WE

Pulse Widths to Disable Outputs 10 — 10 — 10 — 10 — 10 — ns
tRWL Write Command to
tCWL Write Command to
tWCS Write Command Setup Time
tDHR Data-in Hold Time (referenced to

RAS

(17)

)

RAS

Lead Time

CAS

Lead Time

(17)

(14, 17, 20)

RAS

5— 6— 7— 8— 10— ns

(17)
(17, 21)

8 — 12 — 13 — 14 — 15 — ns
8 — 12 — 13 — 14 — 15 — ns
0— 0— 0— 0— 0— ns

) 30— 30— 35— 40— 40— ns

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08/20/98

7