ISSI IS25F041A-5V-R, IS25F041A-3V-R, IS25F021A-5V-R, IS25F011A-5V-R, IS25F011A-3V-R Datasheet
...
IS25F011A
IS25F021A
IS25F041A
Integrated Silicon Solution, Inc.
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PRELIMINARY SF001-1A
06/24/98
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ISSI
®
IS25F011A
IS25F021A
IS25F041A
1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES
WITH 4-PIN SPI INTERFACE
PRELIMINARY
JUNE 1998
FEATURES
• Flash Storage for Resource-Limited Systems
– Ideal for portable/mobile and microcontroller-based
applications that store voice, text, and data
•
NexFLASH
TM
Serial Flash Memory
– Patented single transistor EEPROM memory
– High-density, low-voltage/power, cost-effective
– Small 264-byte sectors
– 10K/100K write cycles, ten years data retention
• Ultra-low Power for Battery-Operation
– Single 5V or 3V supply for read and erase/write
– < 1 µA standby current, 5 mA active @ 3V (typical)
– Low frequency read command for very low power
– No pre-erase. Erase/Write time of 5 ms/sector
@ 5V, ensures efficient battery use
• 4-pin SPI Serial Interface
– Easily interfaces to popular microcontrollers
– Clock operation as fast as 16 MHz
• On-chip Serial SRAM
– Dual 264-byte Read/Write SRAM buffers
– Use in conjunction with or independent of Flash
– Off-loads RAM-limited microcontrollers
• Special Features for Media-Storage Applications
– Byte-level addressing
– Transfer or compare sector to SRAM
– Versatile hardware and software write-protection
– Alternate oscillator frequency for EMI sensitive
applications.
– In-system electronic part number identification
– Removable Serial Flash Module package option
– SFK-SPI Serial Flash Development Kit
DESCRIPTION
The IS25F011A, IS25F021A, and IS25F041A Serial Flash
memories provide a storage solution for systems limited in
power, pins, space, hardware, and firmware resources.
They are ideal for applications that store voice, text, and
data in a portable or mobile environment. Using
ISSI's
patented single transistor EEPROM cell, the devices offer
a high-density, low-voltage, low-power, and cost-effective
nonvolatile memory solution. The devices operate on a
single 5V or 3V (2.7V-3.6V) supply for Read and
Erase/Write with typical current consumption as low as
5 mA active and less than 1 µA standby. Sector erase/write
speeds as fast as 5 ms increase system performance,
minimize power-on time, and maximize battery life.
The IS25F011A, IS25F021A, and IS25F041A provide
1M-bit, 2M-bit, and 4M-bit of flash memory organized as
512, 1024, or 2048 sectors of 264 bytes each. Each sector
is individually addressable serial-clocked commands. The
4-pin SPI serial interface works directly with popular
microcontrollers. Special features include: on-chip serial
SRAM, byte-level addressing, double-buffered sector writes,
transfer/compare sector to SRAM, hardware and software
write protection, alternate oscillator frequency, electronic
part number, and removable Serial Flash Module package
option. Development is supported with the PC-based
SFK-SPI Serial Flash Development Kit.
This document contains PRELIMINARY INFORMATION. ISSI reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc.
ISSI
®
IS25F011A
IS25F021A
IS25F041A
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Integrated Silicon Solution, Inc.
PRELIMINARY SF001-1A
06/24/98
ISSI
®
FUNCTIONAL OVERVIEW
The
NexFLASHTM
IS25F011A, IS25F021A, and
IS25F041A Serial Flash memories provide up to 1M-bit,
2M-bit, and 4M-bit respectively, of low-power and lowvoltage nonvolatile memory that is fully accessible through
a 4-pin Serial Peripheral Interface (SPI) bus. The
IS25F011A, IS25F021A, and IS25F041A incorporate a
variety of special features, such as on-board Serial SRAM,
advanced write protection, and electronic device identification.
DEVICE INFORMATION SECTOR
WRITE PROTECT LOGIC
1, 2, or 4 MEGABIT
SERIAL FLASH MEMORY ARRAY
512, 1024, OR 2048 BYTE-ADDRESSABLE
SECTORS OF 264 BYTES EACH
ROW DECODE (512, 1024, OR 2048 SECTORS)
PROGRAM BUFFER
(264 BYTES)
2112
2112
8
8
8
SRAM
(264 BYTES)
COLUMN DECODE, SENSE AMP LATCH
AND DATA COMPARE LOGIC
HIGH-VOLTAGE
GENERATORS
SECTOR-ADDRESS
LATCH
DATA
9/10/11
WRITE CONTROL
LOGIC
WP
HOLD OR
READ/BUSY
LOGIC
CONFIGURATION
REGISTER
STATUS
REGISTER
SPI
COMMAND
AND
CONTROL
LOGIC
BYTE-ADDRESS
LATCH/COUNTER
9
16
HOLD
OR R/
B
SCK
CS
SI
SO
Figure 2. IS25F011A, IS25F021A, and IS25F041A Architectural Block Diagram
An architectural block diagram of the IS25F011A,
IS25F021A, and IS25F041A is shown in Figure 2. Key
elements of the architecture include:
• SPI Interface and Command Set Logic
• Serial Flash Memory Array
• Serial SRAM and Program Buffer
• Write Protection Logic
• Configuration and Status Registers
IS25F011A
IS25F021A
IS25F041A
Integrated Silicon Solution, Inc.
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PRELIMINARY SF001-1A
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ISSI
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Figure 3. IS25F011A, IS25F021A, and IS25F041A
Pin Assignments, 28-Pin TSOP (Type I)
HOLD-R/B
NC
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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26
25
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Table 1. Pin Descriptions
SI Serial Data Input
SO Serial Data Output
SCK Serial Clock Input
CS
Chip Select Input
WP
Write Protect Input
Hold
, R/
B
Hold Input or Read Busy Output
Vcc Power Supply
Pin Descriptions
Package
The IS25F011A, IS25F021A, and IS25F041A are
available in a 28-pin TSOP (Type I) surface mount
package. See Figure 3 and Table 1 for pin assignments. All interface and supply pins are on one
side of the package. The “No Connect” (NC) pins
are not connected to the device, allowing the pads
and the area around them to be used for routing PCB
system traces. The devices are also available in a
cost-effective and space-efficient removable Serial
Flash Module package.
Serial Data Imput (SI)
The SPI bus Serial Data Input (SI) provides a means
for data to be written to (shifted into) the device.
Serial Data Output (SO)
The SPI bus Serial Data Output (SO) provides a
means for data to be read from (shifted out of) the
device during a read operation. When the device is
deselected (CS=1 or
HOLD
=0) the SO pin is in a
high-impedance state.
Serial Clock (SCK)
All commands and data written to the Serial Input
(SI) are clocked relative to the rising edge of the
Serial Clock (SCK). All data read from the Serial
Data Output (SO) is clocked relative to the falling or
rising edge of SCK as specified in the nonvolatile
configuration register. The data output clock edge is
factory-programmed to the default condition of the
falling edge, allowing compatibility with standard
SPI systems. Clock rates of up to 16 MHz for 5V
devices and up to 8 MHz for 3V devices are supported.
Chip Select (
CSCS
CSCS
CS
)
The IS25F011A, IS25F021A, and IS25F041A are selected for operation when the Chip Select input (CS) is
asserted low. Upon power-up, an initial low-to-high transition of CS is required before any command sequence will
be acknowledged. The device can be deselected to a nonactive state when CS is brought high. Once deselected,
the SO pin will enter a high-impedance state and power
consumption will decrease to standby levels unless programming is in process, in which case standby will resume
when programming is complete.
Write Protect (
WPWP
WPWP
WP
)
The Write Protect input (WP) works in conjunction with the
write protect range set in the configuration register bits.
When WP is asserted (active low) the entire Flash memory
array is write protected. When high, any Flash memory
sector can be written to unless its address is within the
write protect range that is set in the configuration register.
Hold or Ready/Busy (
HOLDHOLD
HOLDHOLD
HOLD
or R/
BB
BB
B
)
This multi-function pin can serve either as a Hold input
(
HOLD
) or as a Ready-Busy output (R/B). The pin function
is user-programmable via the nonvolatile configuration
register. Factory-programmed as a no-connect, the pin
can be reconfigured as a Ready-Busy output or as a Hold
input by setting the configuration register. See the configuration register section of this data sheet for further details.
Power Supply Pins (Vcc and GND)
The IS25F011A, IS25F021A, and IS25F041A support
single power supply Read and Erase/Write operations in
5V (4.5V -5.5V) and 3V (2.7V-3.6V) Vcc versions. Typical
active power is as low as 5 mA for the 3V version with
standby current less than 1 µA.
IS25F011A
IS25F021A
IS25F041A
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Integrated Silicon Solution, Inc.
PRELIMINARY SF001-1A
06/24/98
ISSI
®
Serial Flash Memory Array
The IS25F011A, IS25F021A, and IS25F041A Serial Flash
memory arrays are organized as 512, 1024, and 2048
sectors of 264-bytes (2,112 bits) each, as shown in Figure
4. Grouping sectors as pairs offer a convenient format for
applications that store and transfer data in a DOS compatible sector size of 512-bytes. The additional 16-bytes per
sector pair can be used for sector management such as
header, checksum, CRC, or other related application
requirements.
The Serial Flash memory of the IS25F011A, IS25F021A,
and IS25F041A is byte-addressable. That is, each sector
is individually addressable and each byte within a sector
is individually addressable. This allows a single byte, or
specified sequence of bytes, to be read without having to
clock an entire 264-byte sector out of the device. Data can
be read directly from a sector in the Flash memory array
by using a
Read from Sector
command from the SPI bus.
Data can be written to a sector in the Flash memory array
by means of the Serial SRAM using a
Write to Sector
command or a
Transfer SRAM to Sector
command.
After a sector has been written, the memory array will
become busy while it is programming the specified nonvolatile memory cells of that sector. This busy time will not
exceed tWP (~5 ms for 5V devices), during which time the
Flash array is unavailable for read or write access. The
device can be tested to determine the array’s availability using the Ready/Busy status that is available during
most read commands, via the status register, or on the
Ready/Busy pin. Note that the SRAM is always available,
even when the memory array is busy. See the Serial
SRAM section for more details.
The IS25F011A, IS25F021A, and IS25F041A do not
require pre-erase. Instead, the device incorporates an
auto-erase-before-write feature that automatically erases
the addressed sector at the beginning of the write operation. This allows for fast and consistent programming
times. It also simplifies firmware support by eliminating
the need for a separate pre-erase algorithm and the
complex management of disproportional erase and write
block sizes commonly found in other devices.
Byte 0
000H
Sector 0
000H
25F021
S[9:0]
25F011
S[8:0]
25F041
S[10:0]
Sector Address:
Byte Address: B[8:0]
Sector 1
001H
Sector 2047
7FFH
Sector 1023
3FFH
Sector 511
1FFH
Sector 2046
7FEH
Sector 1022
3FEH
Sector 510
1FEH
Sector 2-2045
002H-7FDH
Sector 2-1021
002H-3FDH
Sector 2-509
002H-1FDH
Byte1
001H
Byte1
001H
Byte 2-261
002H-105H
Byte 2-261
002H-105H
1M-bit, 2M-bit, or 4M-bit Serial Flash Memory Array
512, 1024, and 2048 Byte-Addressable Sectors
of 264-Bytes each
Byte 262
106H
Byte 262
106H
Byte 263
107H
Byte 0
000H
Byte 263
107H
Byte 0
000H
Byte 0
000H
Byte 1
001H
Byte 1
001H
Byte 2-261
002H-105H
Byte 2-261
002H-105H
Byte 262
106H
Byte 262
106H
Byte 263
107H
Byte 263
107H
Sector 1
001H
Sector 1
001H
Sector 0
000H
Sector 0
000H
Figure 4. IS25F011A, IS25F021A, and IS25F041A Serial Flash Memory Array
IS25F011A
IS25F021A
IS25F041A
Integrated Silicon Solution, Inc.
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PRELIMINARY SF001-1A
06/24/98
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ISSI
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Serial SRAM and Program Buffer
One of the most powerful features of the IS25F011A,
IS25F021A, and IS25F041A is the integrated Serial
SRAM and its associated Program Buffer. Together, the
264-byte Serial SRAM and 264-byte Program Buffer
provide up to 528-bytes of usable SRAM storage. The
SRAM can be used in conjunction with the Flash memory
or independently.
The main purpose of the Serial SRAM is to serve as the
primary buffer for sector data to be written into the Serial
Flash memory array. Using the
Write to Sector
command,
data is first shifted into the SRAM from the SPI bus. When
the command sequence has been completed, the entire
264-bytes is transferred to the Program Buffer. The Program Buffer supports the array during the Erase/Write cycle
(tWP), freeing the SRAM to accept new data. This double-
buffering scheme increases erase/write transfer rates and
can eliminate the need for external RAM buffers (Figure 5).
The SRAM is fully byte-addressable. Thus, the entire
264-bytes, a single byte, or a sequence of bytes can be
read from, or written to the SRAM. This allows the SRAM
to be used as a temporary work area for read-modify-write
operations prior to a sector write.
The
Transfer Sector to SRAM
command allows the contents of a specified sector of Flash memory to be moved to
the SRAM. This can be useful when only a portion of a
sector needs to be altered. In this case the sector is first
transferred to the SRAM, where modifications are made
using the
Write to SRAM
command. Once complete, a
Transfer SRAM to Sector
command is used to update the
sector.
SPI
COMMAND
AND
CONTROL
LOGIC
SCK
CS
SI
SO
STATUS
REGISTER
CONFIGURATION
REGISTER
PROGRAM BUFFER
COMPARE SECTOR
TO SRAM
READ FROM
DEVICE INFORMATION
SECTOR
READ FROM
PROGRAM BUFFER
Note:
1. A single byte, several bytes, or all bytes of a Flash sector, the SRAM, or Program Buffer may be addressed.
2. All double lines represent implied connections or actions.
SERIAL FLASH MEMORY ARRAY
512, 1024, AND 2048 BYTE-ADDRESSABLE
SECTORS OF 264-BYTES EACH
DEVICE INFORMATION SECTOR
TRANSFER SRAM TO SECTOR
(VIA PROGRAM BUFFER)
WRITE TO SECTOR
(VIA SRAM &
PROGRAM BUFFER)
TRANSFER SRAM TO
PROGRAM BUFFER
TRANSFER PROGRAM
BUFFER TO SRAM
SERIAL SRAM
READ FROM
OR WRITE TO
SRAM
TRANSFER
SECTOR TO
SRAM
READ FROM
SECTOR
Figure 5. Command Relationships of the SPI Interface, Serial Flash Memory Array, SRAM, and Program Buffer
IS25F011A
IS25F021A
IS25F041A
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Integrated Silicon Solution, Inc.
PRELIMINARY SF001-1A
06/24/98
ISSI
®
CF15:9
(RESERVED)
CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
AF WR3 WR2 WR1 WR0 WD RCE HR1 HR0
ALTERNATE OSCILATOR
FREQUENCY
WRITE PROTECT
RANGE
WRITE PROTECT
DIRECTION
READ DATA
CLOCK EDGE
HOLD-READY/BUSY
PIN FUNCTION
Figure 6. Configuration Register Bit Locations
The
Compare Sector
command allows the contents of the
SRAM to be compared with the specified sector in memory.
The result of the compare is set in the status register. This
command can be useful when rewriting multi-sector files
that have only minor changes from the previous write. If the
new data in the SRAM is the same as the previously
written data, the sector write can be skipped. Used in this
way, the command saves time that would have been
used for re-programming. It also extends the endurance
of the Flash memory cells. The Compare Sector command
is also useful for write/verify operation (see High Data
Integrity Applications, page 19).
Using the SRAM Independant of Flash Memory
The SRAM can be used independently of Flash memory
operations for lookup tables, variable storage, or scratch
pad purposes. If the Flash memory needs to be written to
while SRAM is being used for a different purpose, the
contents can be temporarily stored to a sector and then
transferred back again when needed. The SRAM can be
especially useful for RAM-limited microcontroller-based
systems, eliminating the need for external SRAM and
freeing pins for other purposes. It can also make it possible
to use small pin-count microcontrollers, since only a few
pins are needed for the interface instead of the 20-40 pins
required for parallel bus-oriented Flash devices.
If more than 264 bytes of SRAM are needed, the
Transfer
SRAM to Program Buffer, Transfer Program Buffer to
SRAM
, and the
Read Program Buffer
commands can be
used to expand the storage to 528 bytes. In this mode of
operation, all writes must be handled through the 264-byte
SRAM and the Program buffer is essentially used as a
stack.
Write Protection
The IS25F011A, IS25F021A, and IS25F041A provide
advanced software and hardware write protection features. Software-controlled write protection of the entire
array is handled using the
Write Enable and Write Disable
commands. Hardware write protection is possible using
the Write Protect pin (WP). Write-protecting a portion of
Flash memory is accommodated by programming a write
protect range in the configuration register. For applications needing a portion of the memory to be permanently
write-protected, a onetime programmable write protection feature is supported. Contact
ISSI
for further informa-
tion.
Configuration Register
The Configuration Register stores the current configuration of the
HOLD
-R/B pin, read clock edge, write protect
range, and alternate oscillator frequency (Figure 6). The
configuration register is accessed using the
Write and
Read Configuration Register
commands. A nonvolatile
IS25F011A
IS25F021A
IS25F041A
Integrated Silicon Solution, Inc.
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PRELIMINARY SF001-1A
06/24/98
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register, the configuration register will maintain its setting
even when power is removed. The factory default setting
for bits CF8-CF0 is: 0 0000 1001 B(write protect range =
none, read uses falling edge of the clock, and pin 1 = no
connect). Bits CF15-CF9 are reserved. When writting to
the configuration register CF15-CF9 should be 0. When
reading, the settings of CF15-CF9 should be ignored.
Standard write endurance rating of the memory array
allows for 10,000 erase/write cycles. Extended endurance to 100,000 cycles is possible using ECC techniques
like those provided in the SFK-SPI Development Kit (see
High Data Integrity Application, page 19). The rating of the
configuration register EEPROM cells, however, is 1,000
write cycles. This is more than adequate considering the
configuration seldom needs to be changed. To minimize
writes to the configuration register, the configuration
register should be read upon power-up to determine if a
change is required. If no change is needed, the write
configuration command can be skipped. This process will
extend the life of the configuration register and save
processing time (Figure 7).
Alternate Oscillator Frequency, AF
Flash memory devices have charge pump oscillators to
generate internal high-voltages used for programming
nonvolatile memory cells. In some applications, the oscillator frequency of the charge pump may cause noise
interference. To solve this problem, an alternate oscillator frequency (AF) can be selected by setting bit CF[8]
of the configuration register. The alternate frequency is
a non-harmonic frequency of the standard oscillator. The
factory default setting is for the standard oscillator frequency, AF equal to 0.
AF=0 Standard Oscillator Frequency is used.
AF=1 Alternate Oscillator Frequency is used.
Write Protect Range and Direction, WR[3:0], WD
The write protect range and direction bits WR[3:0] and
WD are located at configuration bits CF[7:4] and CF[3]
respectively. The write protect range and direction bits
select how the array is protected. They work in conjunction with the WP input pin, valid only if WP is inactive
(high). WR[3:0] can select write protection of all sectors,
none of the sectors, or specific sectors grouped in blocks
of 32 (~8 KB). The WD bit specifies whether the protected
block range starts from the first sector, address 0 (000H),
or from the last sector (1FFH for the IS25F011A, 3FFH for
the IS25F021A, and 7FF for the IS25F041A). Table 2 lists
the write protect sector range for both devices. Once
protected, all further writes to sectors within the range will
be ignored . The factory default setting is with no write
protected sectors, WR=[0,0,0,0] and WD=1.
Read Clock Edge, RCE
The Read Clock Edge bit (RCE) is located at configuration bit location CF[2]. It selects which edge of the clock
(SCK) is used while reading data out of the device.
Although the SPI protocol specifies that data is written
during the rising edge and read on the falling edge of the
clock, if required, the output can be driven on the rising
edge of the clock by setting the configuration registers
RCE bit to a 1. Using the rising edge of clock for data
reads may be beneficial to the timing of some high-speed
systems. The factory default setting is the falling edge of
SCK.
RCE=0 Read data is output on the falling edge of SCK.
RCE=1 Read data is output on the rising edge of SCK.
Figure 7. Flow Chart for Checking the Configuration
Register upon Power-up
System Power-up
Read Device Information Sector,
Verify Device Density and Type
Read Configuration Register
Verify bits are Set as Needed
Configuration
Setting is Correct?
Yes
Write Configuration Register
to Correct Setting
Application Routines
No
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