ISSI IS25C01 User Manual
IS25C01 ISSI
®
1K-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM
FEATURES
• Serial Peripheral Interface (SPI) Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage Operation
— Vcc = 1.8V to 5.5V
• Low power CMOS
— Active current less than 3.0 mA (2.5V)
— Standby current less than 1 µA (2.5V)
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
•
8 byte page write mode
— Partial page writes allowed
• 10 MHz Clock Rate (5V)
• Self timed write cycles
— 5 ms max. @ 2.5V
• High-reliability
— Endurance: 1 million cycles per byte
— Data retention: 100 years
• 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP packages
are available
• Lead-free available
DESCRIPTION
The IS25C01 is an electrically erasable PROM device
that uses the Serial Peripheral Interface (SPI) for
communications. The IS25C01 is 1Kbit
(128 x 8). The IS25C01 EEPROM is offered in a wide
operating voltage range of 1.8V to 5.5V to be compatible
with most application voltages. ISSI designed the
IS25C01 to be an efficient SPI EEPROM solution. The
device is packaged in 8-pin PDIP, 8-pin SOIC, and 8-pin
TSSOP.
The functional features of the IS25C01 allow it to be
among the most versatile serial non-volatile memories
available. Each device has a Chip-Select (CS) pin, and
a 3-wire interface of Serial Data In (SI), Serial Data Out
(SO), and Serial Clock (SCK). While the 3-wire interface of the IS25C01 provides for high-speed access, a
HOLD pin allows the memories to ignore the interface in
a suspended state; later the HOLD pin re-activates
communication without re-initializing the serial sequence. A Status Register facilitates a flexible write
protection mechanism, and a device-ready bit (RDY).
Preliminary Information
January 2006
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
1
IS25C01 ISSI
PIN CONFIGURATION
8-Pin DIP, TSSOP, and SOIC
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
®
PIN DESCRIPTIONS
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power
WP Write Protect
HOLD Suspends Serial Input
NC No Connect
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides syn-
chronization between the microcontroller and IS25C01.
Op-Codes, byte addresses, and data are latched on SI
with a rising edge of the SCK. Data on SO is refreshed
on the falling edge of SCK for SPI modes (0,0) and (1,1).
Serial Data Input (SI): This is the input pin for all data
that the IS25C01 is required to receive.
Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C01.
Chip Select (
Upon power-up, CS should follow Vcc. When the device
is to be enabled for instruction input, the signal requires
a High-to-Low transition. While CS is stable Low, the
master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication, CS must
be driven High. At this moment, the slave device may
start its internal write cycle. When CS is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
Write Protect (
to initiate Hardware Write Protection mode. This mode
prevents the 128 byte array or the Status Register from
being altered. To cause Hardware Write Protection, WP
must be Low. WP may be hardwired to Vcc or GND.
HOLD (
device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the HOLD signal allows
multiple slaves to share the bus. The HOLD signal
transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature, HOLD may be
hardwired to Vcc.
CSCS
CS): The CS pin activates the device.
CSCS
WPWP
WP): The purpose of this input signal is
WPWP
HOLDHOLD
HOLD): This input signal is used to suspend the
HOLDHOLD
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
IS25C01 ISSI
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal.
SLAVE: The IS25C01 is a slave because the clock
signal is an input.
TRANSMITTER/RECEIVER: The IS25C01 has both data
input (SI) and data output (SO).
MSB: The most significant bit. It is always the first bit
transmitted or received.
OP-CODE: The first byte transmitted to the slave
following CS transition to LOW. If the OP-CODE is a
valid member of the IS25C01 instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.
®
BLOCK DIAGRAM
SI
CS
WP
SCK
STATUS
REGISTER
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
VCC
128 x 8
MEMORY ARRAY
ADDRESS
DECODER
GND
OUTPUT
BUFFER
SO
HOLD
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
3
IS25C01 ISSI
STATUS REGISTER
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.
Table 1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
X XXX BP1BP0WENRDY
Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of WP or WEN.
®
Note: X = Don't care bit.
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 1. If
neither is true, it can be modified by a valid instruction.
Ready (
RDYRDY
RDY), Bit 0: When RDY = 1, it indicates that
RDYRDY
the device is busy with a write cycle. RDY = 0 indicates that the device is ready for an instruction. If RDY
= 1, the only command that will be handled by the
device is Read Status Register.
Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modification, regardless of the setting of WP pin or block protection. The only way to set WEN to 1 is via the Write
Enable command (WREN). WEN is reset to 0 upon
power-up, successful completion of Write, WRDI,
WRSR, or WP being Low.
Table 2. Block Protection
Status
Register
Bits Array Addresses Protected
Level BP1 BP0 IS25C01
0 0 0 None
1(1/4) 0 1 60h
-7Fh
2(1/2) 1 0 40h
-7Fh
3(All) 1 1 00h
-7Fh
Don’t Care, Bits 4-7: Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
IS25C01 ISSI
DEVICE OPERATION
The operations of the IS25C01 is controlled by a set of instructions that are clocked-in serially SI pin. (See Table 3). To
begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of the
clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input an
address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All bits
are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High transition of
SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal pro-
gramming were underway.
Table 3. Instruction Set
Name Op-code Operation Address Data(SI) Data (SO)
WREN 0000 X110 Set Write Enable Latch - --
WRDI 0000 X100 Reset Write Enable Latch - - -
RDSR 0000 X101 Read Status Register - - D7-D0,...
WRSR 0000 X001 Write Status Register - D7-D
READ 0000 X011 Read Data from Array A7-A
WRITE 0000 X010 Write Data to Array A7-A
0
0
-D
D7-D0,... -
0
-
7-D0
,...
®
1. X = Don’t care bit. For consistency, it is best to use “0”.
2. A7 = X.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no
affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the
array or Status Register to be ignored.
WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).
READ STATUS REGISTER (RDSR)
The Read Status instruction indicates the status of the
Block Protection setting (see Table 2), the Write Enable
state, and the RDY status. RDSR is the only instruction
accepted when a write cycle is underway. It is recommended that the status of RDY be checked, especially
prior to an attempted modification of data. The 8 bits of
the Status Register can be repeatedly output on SO
after the initial Op-code. (See Figure 4 for timing).
WRITE DISABLE (WRDI)
The device can be completely protected from modification by resetting WEN to 0 through the WRDI instruction. (See Figure 3 for timing).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
5
IS25C01 ISSI
®
WRITE STATUS REGISTER (WRSR)
This instruction lets the user choose a Block Protection
setting. The values of the other data bits incorporated
into WRSR can be 0 or 1, and are not stored in the
Status Register. WRSR will be ignored unless both the
following are true: a) WEN = 1, due to a prior WREN
instruction; and b) Hardware Write Protection is not
enabled. (See Table 4 for details). Except for the RDY
status, the values in the Status Register remain unchanged until the moment when the write cycle is
complete and the register is updated. Once successfully
completed, WEN is reset for complete chip write protection. (See Figure 5 for timing).
READ DATA (READ)
This instruction begins with the op-code and the 8-bit
address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, additional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising CS signal completes
the operation. (See Figure 6 for timing).
WRITE DATA (WRITE)
The WRITE instruction begins with the op-code, the 8-bit
address of the first byte to be modified, and the first data
byte. Additional data bytes may be written sequentially
to the array after the first byte. Each WRITE instruction
can affect the contents of a 8 byte page, but no more.
The page begins at address XXXXX 000, and ends with
XXXXX 111. If the last byte of the page is input, the
address rolls over to the beginning of the same page.
More than 8 data bytes can be input during the same
instruction, but upon a completed write cycle, a page
would only contain the last 8 bytes.
The region of the array defined within Block Protection
cannot be modified as long as that block configuration is
selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN) is
set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. In addition, if Hardware
Write Protection is enabled, the memory array cannot be
modified. Once Write is successfully completed, WEN
is reset for complete chip write protection. (See Figure 7
for timing).
Table 4. Write Protection
WPWP
WP
WPWP
0 Enabled X Read-only Read-only Read-only
1 Not Enabled 0 Read-only Read-only Read-only
1 Not Enabled 1 Read-only Unprotected Unprotected
Note: X = Don't care bit.
Hardware Write WEN Inside Block Outside Block Status Register
Protection
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
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