How it Works
IRF
Loading...
IRS2308STRPBF
Datasheet
21 pgs414.18 Kb0

IRF IRS2308STRPBF, IRS2308 Datasheet

V
CC
V
B
V
S
HO
LOCOM
HIN LIN
LIN
up to 600 V
TO
LOAD
V
CC
Typical Connection
HALF-BRIDGE DRIVER
Features
•
Floating channel designed for bootstrap operation
•
Fully operational to +600 V
•
Tolerant to negative transient voltage, dV/dt
immune
•
Gate drive supply range from 10 V to 20 V
•
Undervoltage lockout for both channels
•
3.3 V, 5 V, and 15 V input logic compatible
•
Cross-conduction prevention logic
•
Matched propagation delay for both channels
•
Outputs in phase with inputs
•
Logic and power ground +/- 5 V offset.
•
Internal 540 ns deadtime
•
Lower di/dt gate driver for better
noise immunity
Data Sheet No.PD60266
IRS2308
(S)PbF
www.irf.com 1
(Refer to L ead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Description
The IRS2308/IRS23084 are high volt­age, high speed power MOSFET and IGBT drivers with dependent high-side and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high
-side configuration which operates up to 600 V.
Packages
8-Lead SOIC
IRS2308S
8-Lead PDIP
IRS2308
Part
Input logic
Cross­conduction prevention
logic
Deadtime
(ns)
Ground Pins
ton/t
off
(ns)
2106
COM
21064
HIN/LIN no none
V
SS/COM
220/200
2108 Internal 540 COM
21084
HIN/
LIN
yes
Programmable 540 - 5000
VSS/COM
220/200
2109 Internal 540 COM
21094
IN/SD yes
Programmable 540 - 5000
VSS/COM
750/200
Feature Comparison
2304
HIN/LIN
yes
Internal 100
COM
160/140
2308
HIN/LIN yes
Internal 540 COM 220/200
•
RoHS compliant
IRS2308(S)PbF
www.irf.com 2
Symbol Definition Min. Max. Units
V
B
High-side floating absolute voltage -0.3 625
V
S
High-side floating supply offset voltage VB - 25 VB + 0.3
V
HO
High-side floating output voltage VS - 0.3 VB + 0.3
V
CC
Low-side and logic fixed supply voltage -0.3 25
V
LO
Low-side output voltage -0.3 VCC + 0.3
V
IN
Logic input voltage (HIN & LIN ) VSS - 0.3 V
CC
+ 0.3
dVS/dt Allowable offset supply voltage transient — 50 V/ns
P
D
Package power dissipation @ TA ≤ +25 °C
(8 lead PDIP) — 1.0
(8 lead SOIC) — 0.625
Rth
JA
Thermal resistance, junction to ambient
(8 lead PDIP) — 125 (8 lead SOIC) — 200
T
J
Junction temperature — 150
T
S
Storage temperature -50 150
T
L
Lead temperature (soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details).
V
°C
°C/W
W
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V differential.
VB High-side floating supply absolute voltage VS + 10 VS + 20 V
S
High-side floating supply offset voltage Note 1 600
V
HO
High-side floating output voltage V
S VB
V
CC
Low-side and logic fixed supply voltage 10 20
V
LO
Low-side output voltage 0 V
CC
V
IN
Logic input voltage COM V
CC
T
A
Ambient temperature -40 125
V
Symbol Definition Min. Max. Units
°C
www.irf.com 3
IRS2308(S)PbF
Static Electrical Characteristics
V
BIAS
(VCC, VBS) = 15 V, VSS = COM, DT= VSS and TA = 25 °C unless otherwise specified. The VIL, V
IH,
and IIN param-
eters are referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO, IO, and R
on
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol Definition Min. T yp. Max. Units T est Conditions
V
IH
Logic “1” input voltage for HIN & LIN 2.5 — —
V
IL
Logic “0” input voltage for HIN & LIN — — 0.8
V
OH
High level output voltage, V
BIAS
- V
O
— 0.05 0.2
V
OL
Low level output voltage, V
O
— 0.02 0.1
I
LK
Offset supply leakage current — — 50 VB = VS = 600 V
I
QBS
Quiescent VBS supply current 20 60 150
I
QCC
Quiescent VCC supply current 0.4 1.0 1.6 mA
I
IN+
Logic “1” input bias current — 5 20 HIN = 5 V, LIN = 5 V
I
IN-
Logic “0” input bias current — 1 5 HIN = 0 V, LIN = 0 V
V
CCUV+
VCC and VBS supply undervoltage positive going
8.0 8.9 9.8
V
BSUV+
threshold
V
CCUV-
VCC and V
BS
supply undervoltage negative going
7.4 8.2 9.0
V
BSUV-
threshold
V
CCUVH
Hysteresis 0.3 0.7 —
V
BSUVH
I
O+
Output high short circuit pulsed current 97 290 —
VO = 0 V,
PW ≤ 10 µs
I
O-
Output low short circuit pulsed current 250 600 —
VO = 15 V,
PW ≤ 10 µs
V
µA
µA
V
mA
Dynamic Electrical Characteristics
V
BIAS
(VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF, TA = 25 °C, DT = VSS unless otherwise specified.
Symbol Definition Min. T yp. Max. Units Test Conditions
t
on
Turn-on propagation delay — 220 300 VS = 0 V
t
off
Turn-off propagation delay — 200 280 VS = 0 V or 600 V
MT Delay matching | ton - t
off
|
—046
t
r
Turn-on rise time — 100 220
t
f
Turn-off fall time — 35 80
DT
Deadtime: LO turn-off to HO turn-on(DT
LO-HO) &
400 540 680
HO turn-off to LO turn-on (DT
HO-LO)
MDT Deadtime matching = | DT
LO-HO
- DT
HO-LO
|
—060
ns
VS = 0 V
VCC = 10 V to 20 V
IO = 2 mA
V
IN
= 0 V or 5 V
IRS2308(S)PbF
www.irf.com 4
Functional Block Diagram
IR2308
LIN
UV
DETECT
DELAY
COM
LO
VCC
HIN
DT
VSS
VS
HO
VB
PULSE FILTER
HV
LEVEL
SHIFTER
R R S
Q
UV
DETECT
DEADTIME &
SHOOT-THROUGH
PREVENTION
PULSE
GENERATOR
VSS/COM
LEVEL SHIFT
VSS/COM
LEVEL SHIFT
www.irf.com 5
IRS2308(S)PbF
Lead Definitions
Symbol Description
HIN Logic input for high-side gate driver output (HO), in phase LIN Logic input for low-side gate driver output (LO), in phase V
B
High-side floating supply HO High-side gate driver output V
S
High-side floating supply return V
CC
Low-side and logic fixed supply LO Low-side gate driver output COM Low-side return
Lead Assignments
8 Lead PDIP 8 Lead SOIC
IRS2308PbF IRS2308SPbF
1 2 3 4
8
7 6
5
V
CC
HIN LIN COM
V
B
HO
V
S
LO
1 2 3 4
8
7 6
5
V
CC
HIN LIN COM
V
B
HO
V
S
LO
IRS2308(S)PbF
www.irf.com 6
Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions
Figure 3. Deadtime Waveform Definitions
HO
LO
HIN
LIN
LIN
HIN
50%
50%
t
r
t
on
t
f
t
off
HO
LO
90% 90%
10% 10%
HIN
LIN
HO
90%
10%
LO
90%
10%
DT
LO-HO
DT
LO-HO
MDT=
- DT
HO-LO
DT
HO-LO
50
%
50
%
www.irf.com 7
IRS2308(S)PbF
0
100
200
300
400
500
-50-250 255075100125 Temperature(
o
C)
Turn-on Delay Time (ns
Figure 4A. Turn-On Time
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
V
BIAS
Supply Voltage (V)
Turn-on Delay Time (ns
Figure 4B. Turn-On Time
vs. Supply Voltage
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125 Temperature(
o
C)
Turn-O ff Time (ns
)
Figure 5A. Turn-Off Propagation D elay
vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
V
BIAS
Supply Voltage (V)
T u rn-Off Time ( ns
)
Figure 5B. Turn-Off Propagation Delay vs.
Supply Voltage
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Figure 4A. Turn-On T ime
vs. Temperature
Figure 4B. Turn-On T ime
vs. Supply Volt age
Temperature (oC)
V
BIAS
Supply Voltage (V)
Turn-On Delay Time (ns)
Turn-On Delay Time (ns)
Figure 5A. Turn-Off Prop agation Delay
vs. Temperature
Figure 5B. Turn-Off Prop agation Delay
vs. Supply Volt age
Turn-Off Time (ns)
Turn-Off Time (ns)
Temperature (oC)
V
BIAS
Supply Voltage (V)
Loading...
+ 14 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use