IPS Alpha BM066A001A Specification

Global LCD Panel Exchange Center

TECHNICAL DATA

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Date:July.13,2006

BM066A001A

CONTENTS

No. Item Sheet No. Page

䋭

䋭

1

2 INITIAL OPTICAL CHARACTERISTICS

3

4

5

9 PRECAUTION

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

INTERFACE PIN ASSIGNMENT

DIMENSIONAL OUTLINE7

DESIGNATION LOT MARK8

COVER

DESCRIPTION

BLOCK DIAGRAM

INTERFACE TIMING6

IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1
IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1
IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1
IPS4STD 㵨 2499 - 1

IPS4STD 㵨 2499 - 1

1-1/1

2-1/1

3-1/1

4-1/2䌾2/2

5-1/1

6-1/1

7-1/6䌾6/6

8-1/3䌾3/3

9-1/2䌾2/2

10-1/1

11-1/3䌾3/3

IPS Alpha Technology, Ltd.

Date

July.13,2006

Sheet

No.

IPS4STD - 2499 - 1

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Page

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The following specifications are applied to the following Super-TFT module.
Note : Inverter for back light unit is built in this module.

Product Name : BM066A001A

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DESCRIPTION

General Specifications

Effective Display Area : (H)575.769×(V)323.712 (mm)

Number of Pixels : (H)1,366×(V)768 (pixels)

Pixel Pitch : (H)0.4215×(V)0.4215 (mm)

Color Pixel Arrangement : R+G+B Vertical Stripe

Display Mode : Transmissive Mode

Normally Black Mode

Top Polarizer Type : Anti-Glare

Number of Colors : 16,777,216 (colors)

Viewing Angle Range : Super Wide Version

(Horizontal & Vertical : 170°, CR㻢10)

Input Signal : 1-channel LVDS (LVDS:Low Voltage Differential Signaling)

Back Light : 7pcs. of CCFL (Type:U-Shape)

External Dimensions : (H)626.0×(V)373.0×(t)47.5 (mm)

Weight : 5,100g typ.

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Date

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Sheet

No.

IPS4STD - 2499 - 1

Page

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1. ABSOLUTE MAXIMUM RATINGS

1.1 Environmental Absolute Maximum Ratings

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ITEM

Temperature

Humidity

Vibration

Shock

Corrosive Gas

Illumination at

LCD Surface

Min.

0-20

Max.

50

Min.

2)

䋭
䋭

Not Acceptable

䋭䋭

4.9(0.5G)

29.4(3G)

50,000

䋭
䋭

Not Acceptable

Max.

2)

14.7 (1.5G)

294 (30G)

50,000

Unit Note

㷄

䋦RH

m/s

m/s

2

2

1),5),6)60

1)

3)

4)

䋭

lx

Note 1) Temperature and Humidity should be applied to the glass surface of a Super-TFT module,
not to the system installed with a module.

The temperature at the center of rear surface should be less than 70㷄 on the condition of operating.

The brightness of a CCFL tends to drop at low temperature. Besides, the life-time becomes shorter

at low temperature.

2) Ta㻡40 㷄㵹㵹㵹Relative humidity should be less than

85%RH max. Dew is prohibited.

Ta䋾40 㷄㵹㵹㵹Relative humidity should be lower than

the moisture of the 85%RH at 40㷄.

3) Frequency of the vibration is between 15Hz and 100Hz. (Remove the resonance point)

4) Pulse width of the shock is 10 ms.

5) Long operation under low temperature may cause some portion of display area to be reddish for
several minutes after turning on the product.
However, it does not affect the characteristics and reliability of the product.

Operating Storage

1.2 Electrical Absolute Maximum Ratings
(1)Super-TFT Module

ITEM

Power Supply Voltage

Input Voltage for logic

Electrostatic Durability

SYMBOL Min. Max. Unit Note

V

DD

V

I

V

ESD0

V

EDS1

Note 1) It is applied to pixel data signal and clock signal.

2) Discharge Coefficient 䋺 200pF-250, Environmental 䋺 25㷄-70䋦RH

3) It is applied to I/F connector pins.

4) It is applied to the surface of a metallic bezel and a LCD panel.

(2) Back-light Inverter

ITEM

Input Voltage

ON/OFF Control Input Voltage

SYMBOL Unit Note

Vin

ON/OFF

0 V

13.2

-0.3 3.6

±100

±8

Min. Max.

28.0-1.0

-1.0

-1.0Brightness Control Voltage BRT

5.5

5.5

V

V

kV

V

V

V

Vss = 0 V

1)

2),3)

2),4)

Vss = 0 V

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2. INITIAL OPTICAL CHARACTERISTICS

The following optical characteristics are measured under stable conditions. It takes about 30 minutes
to reach stable conditions. The measuring point is the center of display area unless otherwise noted.
The optical characteristics should be measured in a dark room or equivalent state.

Measuring equipment䋺CS-1000A, or equivalent
Ambient Temperature =25㷄䇮VDD=12.0V䇮f V=60Hz䇮
Vin=24V䇮BRT=3.15V

ITEM

Contrast Ratio CR 750

Response

Time

Brightness of white Bwh

Brightness uniformity Buni %30 4)

Color

Chromaticity

(CIE)

Variation of

Color Position

(CIE)

Rise ton 9

Fall toff

Red

Green

Blue

White

Red

Green

Blue

White

SYMBOL CONDITION Min. Typ. Max. UNIT NOTE

400

䋭

䋭

350

䋭䋭

㱣 0.65

䌹 0.33

㱣

䌹

㱣

䌹

㱣

䌹

㰱㱣 0.04

㰱䌹

㰱㱣

㰱䌹

㰱㱣

㰱䌹

㰱㱣

㰱䌹

䋽0°

1)

=+50°
=0°,90°
80°,270°

1)

0.62

0.30

0.26

0.58

0.12

0.04

0.242

0.248

䋭䋭

䋭䋭
䋭䋭

䋭䋭

䋭䋭
䋭䋭

䋭䋭

䋭䋭

7

450 cd/m

0.29

0.61

0.15

0.07

0.272

0.278

䋭

20

20

䋭

0.68

0.36

0.32

0.64

0.18

0.10

0.302

0.308

0.04

0.04

0.04

0.04

0.04

0.04

0.04

䋭

ms

ms

䋭

䋭

2

[Gray scale

=255]

[Gray scale

=255]

2)

3)

3)

5)

Contrast Ratio at 85° CR85°

IPS Alpha Technology, Ltd.

Date

July.13,2006

Sheet

No.

10

䋭䋭

IPS4STD - 2499 - 1

䋭

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

Estimated

Value

Page 4-1/2

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Note 1) Definition of Viewing Angle

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㱢=90°

Y

㱢=180°

䋨12 o'clock䋩

X'

䋨9 o'clock䋩

Super-TFT Module

2) Definition of Contrast Ratio (CR)

CR =

(Luminance at displaying WHITE)

(Luminance at displaying BLACK)

㱔=0°

Z

Z'

㱔

eye

㱢

Y'

㱢=270°

䋨6 o'clock䋩

㱢=0°

X䋨3 o'clock䋩

3) Definition of Response Time

Displaying

Data Signal

%

100

Optical

90

Response

( Luminance)

10

0

4䋩 Definition of Brightness Uniformity

10%

90%

(1) (2) (3)

(4) (5) (6)

(7)

10%

䋺measuring points

(8) (9)

50%

50%

90%

䌾

䌾

WHITE

ton

䌾

䌾

䌾

䌾

BLACK

toff

Display pattern is white (255 level) . The brightness
uniformity is defined as the following equation. Brightness at each
point is measured, and average, maximum and minimum
brightness is calculated.

Buni=

Bmax or Bmin - Bave

㬍100

Bave

where, Bmax = Maximum brightness
Bmin = Minimum brightness

9

㰿 (B(k))

Bave= Average brightness =

k=1

9

5䋩Variation of color position on CIE is defined as difference between colors at =0°and
at䋽50°& =0°,90°,180°,270°.

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Date

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Sheet

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT-LCD Module Ta=25㷄䋬Vss=0V

ITEM SYMBOL Min. Unit Note

Power Supply Voltage V

Power Supply Current

Ripple Voltage of Power Supply 0.15

V

I

DD

DDR

DD

11.4

䋭
䋭䋭

Typ. Max.

12.0

0.4

12.6 V

0.6

A 1),2)

V

Note 1) DC current at fv=60.0Hz, fCLK=82MHz, VDD=12.0V and Display pattern is Horizontal stripe.

Super-TFT Module

DC Ampere Meter

DD

䌖

SS

䌖

2) Current fuse is built in a module. Current capacity of power supply for VDD
should be larger than 4A, so that the fuse can be opened at the trouble of power supply.

3.2 Back Light

Input Voltage

Input Current

ON/OFF Control
Input Voltage

Brightness Control
Input Voltage

PWM Duty

Output current

Open Output Voltage Vrms1900Vopen

ON

OFF

Min. Brightness

Max. Brightness

Min. Brightness

Max. Brightness

SymbolITEM

ON/OFF

BRT

On-Duty

IL

VALUE

MaxTypMin

䋭

䋭

䋭

䋭

3.0 V

20

䋭䋭

5.0 6.0 7.0

1700 1800

0

3.15

䋭䋭

5.52.0

0.8-0.3

䋭

3.3

100

mArms

V26.424.021.6VBL

Vin=24.0V,BRT=3.15V 1)3.42.84

AIBL

V

V

V

%

Vin=24.0V,BRT=0V

%

Vin=24.0V,BRT=3.15V

Vin=24.0V,BRT=3.15V

NotesUnit

kHz48 52fLOutput Frequency 50

1) This characteristics should be applied putting on the lamp about 30 minutes later with ambient
temperature. (Ta=25 ± 2㷄)

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Date

July.13,2006

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4. BLOCK DIAGRAM

(1) Super-TFT Module

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Drain Driver

LVDS

Display data.

Timing signal.

DC power supply

DC power supply

ON/OFF Control

CN2

CN1

Receiver

Tcon

Timing

Converter

DC/DC

Converter

D1 D2 D4098

G1

G2

Super TFT-LCD

Gate driver

G768

HV

BRT

CN3

Back light

Inverter

HV

HV

HV

Lamp 1

Lamp 7

IPS Alpha Technology, Ltd.

Date

July.13,2006

Sheet

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IPS4STD - 2499 - 1

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5. INTERFACE PIN ASSIGNMENT

5. 1 TFT-LCD MODULE

CN1 : HIROSE FX15S-41S-0.5SH

(Matching connector :HIROSE FX15S-41P-C)

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Pin No. Symbol Description

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

Rx0- Pixel Data

Rx0+

VSS

Rx1-

Rx1+

VSS GND(0V)

Rx2- Pixel Data

Rx2+

VSS

CLK- Pixel Clock

CLK+

VSS

Rx3-

Rx3+

VSS

IC Internally Conected , Keep Open

IC

IC

IC

IC

IC

IC

IC

IC

IC

IC

IC

IC

IC

Power Supply (typ.+12V) 1)

GND(0V) 2)

GND(0V)

Pixel Data

GND(0V)

GND(0V)

Pixel Clock

GND(0V)

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Internally Conected , Keep Open

Note

3)

2)

3)

2)

3)

2)

3)

2)

3)

2)

Notes 1) All VDD pins shall be connected to +12.0V(Typ.).

2) All VSS pins shall be grounded. Metal bezel is internally connected to VSS.

3) Rx n+ and Rx n- (n=0,1,2,3) should be wired by twist-pairs or side-by-side FPC patterns, respectively.

IPS Alpha Technology, Ltd.

Date

July.13,2006

Sheet

No.

IPS4STD - 2499 - 1

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5. 2 BACK-LIGHT UNIT

CN2 : JST S14B-PH-SM4-TB
(Matching connector : JST PHR-14 )

SYMBOLPin No.

VIN1

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NoteDescription

2

3

4

5

11

12

13

14

Notes 1) All VIN pins shall be connected to +24.0V(Typ.).

2) All VSS pins shall be grounded. Metal bezel is internally connected to VSS.

3) High level:2.2䌾5.5V, Low level:-0.3䌾0.8V

4) High level : 3.15V , Low level : 0V

VIN

VIN

VIN

VIN

VSS6

VSS7

VSS8

VSS9

VSS10

NC

ON/OFF

BRT High : Max. Brightness , Low : Min. Brightness

NC NC

Power supply(Typ. 24.0V)

GND(0V)

NC

High:Lamp ON, Low:Lamp OFF

1)

2)

3)

4)

CN3 : JST S10B-PH-SM4-TB
(Matching connector : JST PHR-10)

1

2

3

4

5

6

7

8

9

10

Note 1) CN3 is not used.

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NoteDescriptionSYMBOLPin No.

1)

IPS Alpha Technology, Ltd.

Date

July.13,2006

Sheet

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5.3 BLOCK DIAGRAM OF INTERFACE

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CN1

TFT-LCD Module SideTV set Side

TxIN

R0-R7

G0-G7

B0-B7

Hsync

Vsync

DTMG

Host

Graphics

PLL

Controller

R0䌾R7 䋺Pixel R Data
G0䌾G7 䋺Pixel G Data
B0䌾B7 䋺Pixel B Data
HSYNC 䋺Horizontal synchronization signal
VSYNC 䋺Vertical synchronization signal
DTMG 䋺Display timing signal

Rx 0+

Rx 0-

Rx 1+

Rx 1-

Rx 2+

Rx 2-

Rx 3+

Rx 3-

CLK+

CLK-

100

100

100

100

100

㱅

RxOUT

R0㵥 R7
G0 㵥 G7

㱅

㱅

B0㵥 B7

Hsync

Vsync

㱅

㱅

PLL

DTMG

DCLK

Timing

Converter

Notes 1) The system must have the transmitter to drive the module.

2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used
differentially.

IPS Alpha Technology, Ltd.

Date

July.13,2006

Sheet

No.

IPS4STD - 2499 - 1

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5.4 LVDS INTERFACE

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SIGNAL THC63LVDM83A THC63LVDM83A THC63LVDF84A THC63LVDF84A CONTROL

R2 51 Tx IN0 27 Rx OUT0 R2
R3 52 Tx IN1 29 Rx OUT1 R3
R4 54 Tx IN2 TA OUT0+ Rx 0+ 30 Rx OUT2 R4
R5 55 Tx IN3 32 Rx OUT3 R5
R6 56 Tx IN4 33 Rx OUT4 R6
R7 3 Tx IN6 TA OUT0- Rx 0- 35 Rx OUT6 R7
G2 4 Tx IN7 37 Rx OUT7 G2
G3 6 Tx IN8 38 Rx OUT8 G3
G4 7 Tx IN9 39 Rx OUT9 G4
G5 11 Tx IN12 TA OUT1+ Rx 1+ 43 Rx OUT12 G5
G6 12 Tx IN13 45 Rx OUT13 G6
G7 14 Tx IN14 46 Rx OUT14 G7
B2 15 Tx IN15 TA OUT1- Rx 1- 47 Rx OUT15 B2

24bit B3 19 Tx IN18 51 Rx OUT18 B3

B4 20 Tx IN19 53 Rx OUT19 B4
B5 22 Tx IN20 54 Rx OUT20 B5
B6 23 Tx IN21 TA OUT2+ Rx 2+ 55 Rx OUT21 B6

B7 24 Tx IN22 1 Rx OUT22 B7
HSYNC 27 Tx IN24 3 Rx OUT24 HSYNC
VSYNC 28 Tx IN25 TA OUT2- Rx 2- 5 Rx OUT25 VSYNC

DTMG 30 Tx IN26 6 Rx OUT26 DTMG

R0 50 Tx IN27 7 Rx OUT27 R0

R1 2 Tx IN5 34 Rx OUT5 R1

G0 8 Tx IN10 TA OUT3+ Rx 3+ 41 Rx OUT10 G0

G1 10 Tx IN11 42 Rx OUT11 G1

B0 16 Tx IN16 49 Rx OUT16 B0

B1 18 Tx IN17 TA OUT3- Rx 3- 50 Rx OUT17 B1

RSVD 1) 25 Tx IN23 2 Rx OUT23 not connect

DCLK 31 TxCLK IN TxCLK OUT+ RxCLK IN+ 26 RxCLK OUT DCLK

TRANSMITTER TRANSMITTER INTERFACE CONNECTOR INTERFACE CONNECTOR RECEIVER RECEIVER TFT

PIN INPUT PC TFT-LCD PIN OUTPUT INPUT

TxCLK OUT- RxCLK IN-

R0䌾R7 䋺Pixel R Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
G0䌾G7 䋺Pixel G Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
B0䌾B7 䋺Pixel B Data 䋨7䋻MSB䋬䇭0䋻LSB䋩
HSYNC 䋺Horizontal synchronization signal
VSYNC 䋺Vertical synchronization signal
DTMG 䋺Display timing signal

Notes 1) RSVD(reserved) pins on the transmitter shall be "H" or "L".

IPS Alpha Technology, Ltd.

Date

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Sheet

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5.5 CORRESPONDENCE BETWEEN INPUT DATA AND DISPLAY IMAGE

Display data of adjacent one pixel is latched during one cycle of DCLK.

pixel 䋺 R0䌾R7 :R data

䋨1䋬1䋩

G0䌾G7 :G data
B0䌾B7 :B data

RGB

   

   

   

   

䌾

䌾

䌾

䌾

&%.-

4䌾4
)䌾)

INVALID

$䌾$

&6/)

IPS Alpha Technology, Ltd.

䌾

䌾

1,1 1,2 1,1365 1,1366

䌾

䌾

䌾

䌾

Date

July.13,2006

Sheet

No.

IPS4STD - 2499 - 1

䌾

䌾

INVALID

䌾

䌾

䌾

䌾

2,1 2,2

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5.6 RELATIONSHIP BETWEEN DISPLAY COLORS AND INPUT SIGNALS

Red Data Green Data Blue Data

Input R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Color

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Basic Blue (255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Color Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red : : : : : : : : : : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : : : : : : : : : :

Red (254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red (255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Green(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Green : : : : : : : : : : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : : : : : : : : : :

Green(254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0

Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Blue(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Blue(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Blue : : : : : : : : : : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : : : : : : : : : :

Blue(254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0

Blue(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 11

MSB LSB MSB LSB MSB LSB

Notes 1) Definition of gray scale:
Color(n)䊶䊶䊶䊶Number in parenthesis indicates gray scale level. Larger n corresponds to brighter level.

2) Data: 1:High, 0:Low

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Date

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6. INTERFACE TIMING

6.1 LVDS RECEIVER TIMING

Rx0 G2R7R6R5R4R3R2 Vdiff=0VVdiff=0V

Rx1 B3B2G7G6G5G4G3 Vdiff=0V

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tRP2

tRP3

tRP4

tRP5

tRP6

tRP0

tRP1

Rx2 DE

Rx3 X B1 B0 G1 G0 R1 R0 Vdiff=0V

CLK

Rx0 = (Rx0+) 㵨 (Rx0-)
Rx1 = (Rx1+) 㵨 (Rx1-)
Rx2 = (Rx2+) 㵨 (Rx2-)
Rx3 = (Rx3+) 㵨 (Rx3-)
CLK = (CLK+) 㵨 (CLK-)

RCLK Cycle Time

Rx0
Rx1
Rx2
Rx3

VSYNCHSY

NC

Item Symbol Min. Unit

0 data position

1st data position

2nd data position

3rd data position

4th data position

5th data position

B7 B6 B5 B4 Vdiff=0V

tCLK

Vdiff=0V

Typ. Max.

1/tCLK

tRP0

tRP1

tRP2

tRP3

tRP4

tRP5

65 66 68

1/7tCLK-0.41

-0.41

2/7tCLK-0.41

3/7tCLK-0.41

4/7tCLK-0.41

5/7tCLK-0.41

1/7tCLK

0

2/7tCLK

3/7tCLK

4/7tCLK

5/7tCLK

1/7tCLK+0.41

+0.41

2/7tCLK+0.41

3/7tCLK+0.41

4/7tCLK+0.41

5/7tCLK+0.41

MHz

ns

IPS Alpha Technology, Ltd.

6th data position

Date

July.13,2006

tRP6

6/7tCLK-0.41

Sheet

No.

6/7tCLK

6/7tCLK+0.41

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6.2 SYNCHRONIZATION SIGNAL TIMING

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fV

fVd

DTMG

DTMG

DCLK

DATA

䊶䊶䊶䊶䊶

tH

tHd

䊶䊶䊶䊶䊶 䊶䊶䊶䊶䊶

DE

VSYNCᲦHSYNCᲦDTMGᲦ
R0䌾7䋬G0䌾7䋬B0䌾7

Item

Vertical Frequency

Vertical Period

Vertical Valid

Horizontal Frequency

Horizontal Period

Horizontal Valid

TSTC

1.5V

THTC

DCLK

Symbol Min. Typ. Max. Unit Note

fV

tV

tVd

fH

tH

tHd

57 60 63 Hz

773 800 1500 tH

768

䋭

48

䋭

1400 1708 2000

kHz

tCLK

1366 tCLK

tH

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Date

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6.3 TIMING BETWEEN INTERFACE SIGNALS AND POWER SUPPLY

12V

11.4V

Power Supply
VDD

0V

1V

T1

T7

11.4V

1V

T8T2

Interface Signal

VI

Back-light
Power Supply

V

BL

Back-light

ON/OFF
note(1)

Back-light

BRT
note(1)

24V

0V

0V

0V

Invalid Signal

T3

T4 T5

Valid Signal

Invalid Signal

21.6V21.6V

T6

0 㻡 T1 㻡 10
350 㻡 T2

0 㻡 T3

1 㻡 T4

Note 1) In all periods, the backlight ON/OFF signal voltage and the BRT signal voltage should be lower than
the backlight power supply voltage.

IPS Alpha Technology, Ltd.

Date

July.13,2006

-100 㻡 T5

-100 㻡 T6

0 㻡 T7

350 㻡 T8

Sheet

No.

Unit : ms

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8. DESIGNATION OF LOT MARK

8.1 LOT MARK

Month 2)

Year 1)

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6 digits for production number
䋨000001䌾999999䋩

Special mark 4)

Production management sign

Week 3)

Notes

1)

Year Mark

2006

2007
2008

4) It is the mark that was opened up by production person to take
correspondence with production number.

06

07

08

2䋩

Month Mark

101

2

3

4

5

6

02

03

04

05

06

Month Mark

7

8

9

10

11

12

07

08

09

10

11

12

8.2 Revision (REV.) control

REV. is the column for manufacturing convenience. A-Z except I and O may be written
on this column.

8.3 Location of lot mark

Lot mark is printed on a label. The label is on the metallic bezel as shown in 7. External Dimensional.
The style of character will be changed without notice.

3)
Week(Day) Mark

1䌾7

8䌾14

15䌾21

22䌾28

29䌾31

1

2

3

4

5

㜞㔚࿶ᵈᗧ

Lot mark

$/##

CAUTION HIGH VOLTAGE

*

/#&'+0,#2#0

$/##*

ᧄ䊂䉞䉴䊒䊧䉟䊡䊆䉾䊃ౝ䈱Ⱟశ▤䈮䈲᳓㌁䈏฽䉁䉏䈩䈍䉍䉁䈜䇯ᶧ᥏䊂䉞䉴䊒䊧䉟䈱⎕
䈮ᒰ䈢䈦䈩䈲࿾ᣇ⥄ᴦ૕䈱᧦଀䉁䈢䈲ⷙೣ䈮ᓥ䈦䈩⎕䈚䈩䈘䈇䇯

㪚㪦㪣㪛㩷㪚㪘㪫㪟㪦㪛㪜㩷㪝㪣㪬㪦㪩㪜㪪㪚㪜㪥㪫㩷㪣㪘㪤㪧㩷㪠㪥㩷㪚㪦㪣㪦㪩㩷㪣㪚㪛㩷㪚㪦㪥㪫㪘㪠㪥㪪㩷㪤㪜㪩㪚㪬㪩 㪰
㪧㪣㪜㪘㪪㪜㩷㪝㪦㪣㪣㪦㪮㩷㪣㪦㪚㪘㪣㩷㪦㪩㪛㪠㪥㪘㪥㪚㪜㪪㩷㪦㪩㩷㪩㪜㪞㪬㪣㪘㪫㪠㪦㪥㪪㩷㪝㪦㪩㩷㪠㪫㪪㩷㪛㪠㪪㪧㪦㪪㪘㪣

㪅

IPS Alpha Technology, Ltd.

Date

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Sheet

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

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9. PRECAUTION

Please pay attention to the followings when a Super-TFT module with a back-light unit is used,
handled and mounted.

9.1 Precaution to handling and mounting

(1) Applying strong force to a part of the module may cause partial deformation of frame or mold,
and cause damage to the display.
(2) The module should gently and firmly be held by both hands. Never hold by just one hand in order
to avoid any internal damage. Never drop or hit the module.
(3) The module should be installed with mounting holes of a module.
(4) Uneven force such as twisted stress should not be applied to a module when a module is mounted
on the cover case. The cover case must have sufficient strength so that external force can not be
transmitted directly to a module.
(5) It is recommended to leave a space between a module and a holding board of a module so that
partial force is not applied to a module.

B-zone

Cover case

Effective display area

Edge of
cover case

Super-TFT module

Polarizer

above precaution(5)

Fig.1 Cross sectional view of a monitor set

(6) The edge of a cover case should be located inside more than 1mm from the edge of a module front
frame.
(7) A transparent protective plate should be added on the display area of a module in order to protect
a polarizer and Super-TFT cell. The transparent protective plate should have sufficient strength
so that the plate can not touch a module by external force.
(8) Materials included acetic acid and choline should not be used for a cover case as well as other parts
and boards near a module. Acetic acid attacks a polarizer. Choline attacks electric circuits due to
electro-chemical reaction.
(9) The polarizer on a TFT cell should carefully be handled due to its softness, and should not be touched,
pushed or rubbed with glass, tweezers or anything harder than HB pencil lead. The surface of
a polarizer should not be touched and rubbed with bare hand, greasy clothes or dusty clothes.
(10) The surface of a polarizer should be gently wiped with absorbent cotton, chamois or other soft
materials slightly contained petroleum benzene when the surface becomes dirty. Normal-hexane
as cleaning chemicals is recommended in order to clean adhesives which fix front/rear polarizers
on a Super-TFT cell. Other cleaning chemicals such as acetone, toluen and alcohol should not be
used to clean adhesives because they cause chemical damage to a polarizer.
(11) Saliva or water drops should be immediately wiped off. Otherwise, the portion of a polarizer may
be deformed and its color may be faded.
(12) The module should not be opened or modified. It may cause not to operate properly.

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(13) Metallic bezel of a module should not be handled with bare hand or dirty gloves. Otherwise,
color of a metallic frame may become dirty during its storage. It is recommended to use clean
soft gloves and clean finger stalls when a module is handled at incoming inspection process and
production (assembly) process.
(14) Lamp(CCFL) cables should not be pulled and held.

9.2 Precaution to operation

(1) The ambient temperature near the operated module should be satisfied with the absolute maximum
ratings. Unless it meets the specifications, sufficient cooling system should be adopted to system.
(2) The spike noise causes the mis-operation of a module. The level of spike noise should be as follows:

-200mV<=over- and under- shoot of VDD<= +200mV
VDD including over- and under- shoot should be satisfied with the absolute maximum ratings.
(3) Optical response time, luminance and chromaticity depend on the temperature of a Super-TFT
module. Response time and saturation time of CCFL luminance become longer at lower temperature
operation.
(4) Sudden temperature change may cause dew on and/or in the a module. Dew males damage to a
polarizer and/or electrical contacting portion. Dew causes fading of displayed quality.
(5) Fixed patterns displayed on a module for a long time may cause after-image. It will be recovered
soon.
(6) A module has high frequency circuits. Sufficient suppression to electromagnetic interference should
be done by system manufacturers. Grounding and shielding methods may be effective to minimize
the interference.
(7) Noise may be heard when a back-light is operated. If necessary, sufficient suppression should be
done by system manufacturers.
(8) The module should not be connected or removed while a main system works.
(9) Inserting or pulling I/F connectors causes any trouble when power supply and signal dates are
on-state.I/F connectors should be inserted and pulled after power supply and signal dates are
turned off.

9.3 Electrostatic discharge control

(1) Since a module consists of a Super-TFT cell and electronic circuits with CMOS-ICs, which are
very weak to electrostatic discharge, persons who are handling a module should be grounded
through adequate methods such as a list band. I/F connector pins should not be touched directly
with bare hands.
(2) Protection film for a polarizer on a module should be slowly peeled off so that the electrostatic
charge can be minimized.

9.4 Precaution to strong light exposure

(1) A module should not be exposed under strong light. Otherwise, characteristics of a polarizer and
color filter in a module may be degraded.

9.5 Precaution to storage

When modules for replacement are stored for a long time, following precautions should be taken care of:
(1) Modules should be stored in a dark place. It is prohibited to apply sunlight or fluorescent light

during storage. Modules should be stored at 0 to 35䍎C at normal humidity (60%RH or less).
(2) The surface of polarizers should not come in contact with any other object. It is recommended that
modules should be stored in the Hitachi's shipping box.

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9.6 Precaution to handling protection film

(1) The protection film for polarizers should be pealed off slowly and carefully by persons who are
electrically grounded with adequate methods such as a list band. Besides, ionized air should be blown
over during peeling action. Dusts on a polarizer should be blown off by an ionized nitrogen gun and
so on.
(2) The protection film should be peeling off without rubbing it to the polarizer. Because, if the film is
rubbed together with the polarizer, since the film is attached to the polarizer with a small amount
of adhesive, the adhesive may remain on a polarizer.
(3) The module with protection film should be stored on the conditions explained in 10.5 (1). However,
in case that the storage time is too long, adhesive may remain on a polarizer even after a protection
film is peeled off. Besides, in case that a module is stored at higher temperature and/or higher
humidity, adhesive may remain on a polarizer. The remained adhesive may cause non-uniformity
of display image.
(4) The adhesive can be removed easily with Normal-Hexane. The remained adhesive or its vestige on
the polarizer should be wiped off with absorbent cotton or other soft materials such as chamois
slightly contained Normal-Hexane.

9.7 Safety

(1) Since a Super-TFT cell and lamps are made of glass, handling to the broken module should be taken
care sufficiently in order not to be injured. Hands touched liquid crystal from a broken cell should be
washed sufficiently.
(2) The module should not be taken apart during operation so that back-light drives by high voltage.

9.8 Environmental protection

(1) The Super-TFT module contains cold cathode fluorescent lamps. Please follow local ordinance or
regulations for its disposal.
(2) Flexible printed circuits and printed circuits board used in a module contain small amount of lead.
Please follow local ordinance or regulations for its disposal.

9.9 Use restrictions and limitations

(1) This product is not authorized for use in life support devices or systems, military applications or
other applications which pose a significant risk of personal injury.
(2) In no event shall Hitachi, Ltd., be liable for any incidental, indirect or consequential damages in
connection with the installation or use of this product, even if informed of the possibility thereof
in advance. These limitations apply to all causes of action in the aggregate, including without
limitation breach of contact, breach of warranty, negligence, strict liability, misrepresentation and
other torts.

9.10 Others

(1) Electrical components which may not affect electrical performance are subjective to change without
notice because of their availability.

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