Page 1
Tentative
IPS Alpha Technology, Ltd.
TECHNICAL DATA
AX080F068G
CONTENTS
No.
COVER
RECORD OF REVISION
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
1
ELECTRICAL CHARACTERISTICS
2
3
BLOCK DIAGRAM
INTERFACE PIN ASSIGNMENT
5
INTERFACE TIMING
6
DIMENSIONAL OUT LINE
7
8
Item
ATD1121
ATD1121
ATD1121
ATD1121
ATD1121
ATD1121
ATD11214
ATD1121
ATD1121
Sheet No.
AX080F068G2601
2602 AX080F068G
2603 AX080F068G
2604
2605
2606
2607
2608
2609 AX080F068G
AX080F068G
AX080F068G
AX080F068G
AX080F068G
AX080F068G
Page
1-1/1
2-1/1
3-1/1
4-1/1
5-1/1
6-1/1
7-1/1～1/7
8-1/3～3/3
9-1/3～3/3
IPS Alpha Technology, Ltd. Date Jan. 09, 2009 Sheet No.
ATD1121 1-1/1PageAX080F068G2601
Page 2
Date
RECORD OF REVISION
The upper section : Before revision
The lower section : After revision
Sheet No.
Page
Summary
IPS Alpha Technology, Ltd. Page 2-1/1Date Jan. 30, 2009 Sheet No.
ATD1227 2602 32FHD
Page 3
DESCRIPTION
N
The following specifications are applied to the following TFT module.
ote : Inverter for back light unit is built in this module.
Product Name : 32FHD
General Specifications
Effective Display Area ：(H) 698.4 × (V) 392.85 (mm)
Number of Pixels ：(H)1,920×(V)1,080 (pixels)
Pixel Pitch ：(H) 0.3638 × (V) 0.3638 (mm)
Color Pixel Arrangement : R+G+B Vertical Stripe
Display Mode : Transmissive Mode
Normally Black Mode
Top Polarizer Type : Semi-Glare
Number of Colors ：1,073,741,824 (colors)
Viewing Angle Range : Super wide version
(Horizontal & Vertical : 170°at φ=0°,90°，180°,270°, CR≧10）
Input Signal : 1-channel LVDS (LVDS:Low Voltage Differential Signaling)
Back Light : 8pcs. of CCFL
External Dimensions : (H)760.0 x (V)450.0 x (t)48.0Max (mm)
Weight :TBD (g)
2603 32FHDIPS Alpha Technology, Ltd. Date Page 3-1/1Jan. 30, 2009 Sheet No. ATD1227
Page 4
1. ABSOLUTE MAXIMUM RATINGS
1.1 Environmental Absolute Maximum Ratings
ITEM
Operating
Min. Max.
Min. Max.
Temperature 0 50
Humidity
Vibration
Shock
Corrosive Gas
- 4.9(0.5G) -
- 29.4(3G)
2)
Not Acceptable Not Acceptable
Note 1) Temperature and Humidity should be applied to the glass surface of a TFT module,
not to the system installed with a module.
The temperature at the center of rear surface should be less than 70℃ on the condition of operating.
The brightness of a CCFL tends to drop at low temperature. Besides, the life-time becomes shorter
at low temperature.
2) Ta≦40 ℃‥‥‥Relative humidity should be less than 85%RH max. Dew is prohibited.
Ta＞40 ℃‥‥‥Relative humidity should be lower than the moisture of the 85%RH at 40℃.
3) Frequency of the vibration is between 15Hz and 100Hz. (Remove the resonance point)
4) Pulse width of the shock is 10 ms.
5) Long operation under low temperature may cause some portion of display area to be reddish for
several minutes after turning on the product.
However, it does not affect the characteristics and reliability of the product.
-20
Storage
60
2)
TBD
Unit
℃
％RH
m/s2
m/s2
-
Note
1),5)
1)
3)
4)- TBD
1.2 Electrical Absolute Maximum Ratings
(1)TFT Module Vss = 0 V
ITEM
Power Supply Voltage
Input Voltage for logic
Electrostatic Durability
SYMBOL Min.
Ｖ
Ｖ
DD
1
0
ＶESD0
ＶESD1
Max.
13.2
4.0-0.3
±100
±20
Unit
Note
V
V1)
V
kV
2),3)
2),4)
Note 1)It is applied to pixel data signal and clock signal.
2)Discharge Coefficient：200pF-250Ω, Environmental：25℃-70％RH
3)It is applied to I/F connector pins.
4)It is applied to the surface of a metallic bezel and a LCD panel.
(2) Back-light Inverter Vss = 0 V
ITEM
ON/OFF Control Input Voltage
Brightness Control Voltage
SYMBOL
Vin
ON/OFF
PWM 0
Min.
0
0
Max.
26.4Input Voltage
6.0
3.3
Unit
V
V
V
Note
Date Jan. 30, 2009 Sheet No.
Page 4-1/1IPS Alpha Technology, Ltd. 32FHD2604ATD1227
Page 5
2. ELECTRICAL CHARACTERISTICS
VBL=24V
,3)
2.1 TFT-LCD Module Ta=25℃、Vss=0V
ITEM
Power supply Voltage
Power supply Current
Ripple voltage of power Supply
LVDS select
High
Low 0
SYSTEM
ＤＤ
Ｖ
ＤＤ
Ｉ
Ｖ
ＤＤＲ
LVDSSEL
Min.
11.4
-
- 350 mＶ
2.2
Typ
12.0 12.6
(0.8) TBD
-
3.1 3.6 V
0 0.6 V
Max
単位
Ｖ
Ａ
備考
1),2)
Note 1)fV=60.0Hz，fCLK=82MHz，VDD=12.0V，and Display pattern is white.
TFT Module
DC Ampere Met er
Ｖ
DD
Ｖ
SS
2) Current fuse is built in a module. Current capacity of power supply for VDD
should be larger than 4A, so that the fuse can be opened at the trouble of electrical circuit of module.
2.2 Back Light
ITEM
Input Current
Control Voltage
Brigthness Control
Input Voltage
PWM Duty
ONON/OFF
Min. Brightness
Max. Brightness
Min. Brightness
Max. Brightness
Symbol Min. Typ. Max. Unit
24.0Input Voltage VBL
3.2
-
-V
0-
-
( 20 )
-
IBL
ON/OFF
PWM
on-Duty
21.6
-
2.0
0OFF
-
-
-
-
Note 3)This characteristics should be applied putting on the lamp about 60 minutes later
with ambient temperature. (Ta=25℃±2℃）
26.4
-
5.0
0.8
3.3
-
100
V
PWM on Duty100%
A
V
V
V
%
Notes
,
5-1/1PageIPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No. ATD1227 2605 32FHD
Page 6
3. BLOCK DIAGRAM
r
r
g
l
pply
(1) TFT Module
SourceDriver
2ch-LVDS
Display data.
Timin
signa
DC
Power
su
(2) Back light unit
DC power supply
ON/OFF Control
Brightness Control
CN3
CN2
Tcon
LVDS
Receiver
Back light
Inverter
Timing
Converter
DC/DC
Converter
Lamp8
Lamp7
G1
G2
Gate Drive
G1080
D1 D2 D5760
G1
G2
TFT-LCD
Gate Drive
G1080
Error Signal
Lamp 2
Lamp
1
IPS Alpha Technology, Ltd. 6-1/1Date Jan. 30, 2009 Sheet No. PageATD1227 2606 32FHD
Page 7
4. INTERFACE PIN ASSIGNMENT
4. 1 TFT-LCD module
CN3:JAE FI-R51S-HF
(Matching connector : JAE FI-R51-HL)
PIN
SYMBOL DESCRIPTION NOTE
No.
1V
SS GND(0V) 2) 28 RxB0-
3IC
4IC
5IC
Internally Connected,
Keep Open
6IC
7 LVDS
8IC
9NC
10 NC
12 RxA0-
13 RxA0+
14 RxA1-
15 RxA1+ 42 V
16 RxA2-
17 RxA2+
18 V
19 CLKA-
20 CLKA+ 47 NC
21 V
22 RxA3-
23 RxA3+ 50 VDD
24 NC
25 NC
26 V
27 V
SEL Select LVDS Data Format 5) 34 VSS GND(0V) 2)
Internally Connected,
Keep Open
No Connection
SS GND(0V) 2)
ODD Pixel Data 3)
ODD Pixel Data 3)
ODD Pixel Data 3)
SS GND(0V) 2)
ODD Pixel Clock 3)
SS GND(0V) 2) 48 VDD
ODD Pixel Data 3)
No Connection
SS
GND(0V) 2)
SS
PIN
SYMBOL DESCRIPTION NOTE
No.
29 RxB0+2 Test 4)
30 RxB1-
31 RxB1+
32 RxB2-
33 RxB2+
35 CLKB-
36 CLKB+
37 V
38 RxB3-
39 RxB3+11 V
40 NC No Connection
41 NC No Connection
43 V
44 VSS
45 VSS
46 V
49 V
51 V
EVEN Pixel Data 3)
EVEN Pixel Data 3)
EVEN Pixel Data 3)
EVEN Pixel Clock 3)
SS GND(0V) 2)
EVEN Pixel Data 3)
SS
SS
GND(0V) 2)
SS
No Connection
DD
DD
Power Supply (typ.+12V) 1)
Note 1) All V
2) All V
DD pins shall be connected to +12.0V(Typ.).
SS pins shall be grounded. Metal bezel is internally connected to VSS.
3) Rx n+ and Rx n- (n=0,1,2,3) should be wired by twist-pairs or side-by-side FPC patterns, respectively.
4) Open : Normal mode. GND : Test mode.
5) See page 8-3/6 & 8-4/6
IPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No. 7-1/7ATD1227 2607 32FHD Page
Page 8
4. 2 Back light unit
Inverter pin assignment
JST S14B-PHA-SM-TB(LF)(SN)
(Matching connector : JST PHR-14)
PIN No. SYMBOL DESCRIPTION
1
2
3
4
5
6 Vss
7
8 Vss
9 Vss
10 Vss
11
12
13
14
Note 1) All Vin pins shall be connected to +24.0V(Typ.).
2) All Vss pins shall be grounded. Metal bezel is internally connected to Vss.
Vin
Vin
Vin 1)
Vin
Vin
Vss
FAIL
ON/OFF
PWM
SELECT
Power supply ( Typ. +24.0V )
GND ( 0V ) 2)
Status output (Normal:GND abnormal:open )
High : LAMP ON(3.3V) Low : LAMP OFF
14pin low:0-3.3V pulse
(120-240Hz ON duty 20-100%)
Low:external pwm dimming
NOTE
DateIPS Alpha Technology, Ltd. Jan. 30, 2009 Sheet No.
ATD1227 2607
Page 7-2/732FHD
Page 9
4. 3 Block diagram of interface
RA0-RA7
GA0-GA7
BA0-BA7
VSYNC
HSYNC
DE
DCLK
RB0-RB7
GB0-GB7
BB0-BB7
RSVD
1)
TxIN
TTL Parallel-to-LVDS
PLL
TTL Parallel-to-LVDS
CN3
RxA 0+
RxA 0-
RxA 1+
RxA 1-
RxA 2+
RxA 2-
RxA 3+
RxA 3-
CLKA+
CLKA-
RxB 0+
RxB 0RxB 1+
RxB 1RxB 2+
RxB 2-
RxB 3+
RxB 3-
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
TFT-LCD Module SideTV SET Side
LVDS-to-LVDS Parallel
PLL
LVDS-to-LVDS Parallel
RxOUT
RA0-RA7
GA0-GA7
BA0-BA7
not connect
not connect
DE
DCLK
RB0-RB7
GB0-GB7
BB0-BB7
not connect
not connect
DE
CLKB+
DCLK
PLL
CLKB-
100Ω
PLL
Host
Graphics
Controller
Timing Converter
RA0～RA7, RB0～RB7 : Pixel R Data (7; MSB, 0; LSB)
GA0～GA7, GB0～GB7 : Pixel G Data (7; MSB, 0; LSB)
BA0～BA7, BB0～BB7 : Pixel B Data (7; MSB, 0; LSB)
DE : Data Enable
Note 1) The system must have the transmitter to drive the module.
2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line
when it is used differentially.
DCLK
IPS Alpha Technology, Ltd. 7-3/7Date Jan. 30, 2009 Sheet No. PageATD1227 2607 32FHD
Page 10
4. 4 LVDS interface
The LVDSSEL signal of CN3 pin No.7 specification is “L” or open.【LVDSSEL = L or open】
SIGNAL
TRANSMITTER
THC63LVDM83A CONTROL
INTERFACE CONNECTOR RECEIVER
PIN INPUT TV Set TFT-LCD PIN OUTPUT INPUT
RA0/RB0 51 Tx IN0
RA1/RB1 52 Tx IN1 29
RA2/RB2 54 Tx IN2
TA OUT0+ RxA/B 0+ 30 Rx OUT2 RA2/RB2
27 Rx OUT0 RA0/RB0
Rx OUT1 RA1/RB1
RA3/RB3 55 Tx IN3 32 Rx OUT3 RA3/RB3
RA4/RB4 56 Tx IN4
33 Rx OUT4 RA4/RB4
RA5/RB5 3 Tx IN6 TA OUT0- RxA/B 0- 35 Rx OUT6
GA0/GB0 4 Tx IN7 37 Rx OUT7 GA0/GB0
38
GA1/GB1 6 Tx IN8
Rx OUT8 GA1/GB1
GA2/GB2 7 Tx IN9 39 Rx OUT9 GA2/GB2
Rx OUT12 GA3/GB3GA3/GB3 11 Tx IN12 TA OUT1+
Rx OUT13 GA4/GB4
GA4/GB4 12
RxA/B 1+ 43
Tx IN13 45
GA5/GB5 14 Tx IN14 46 Rx OUT14 GA5/GB5
Rx OUT15 BA0/BB0BA0/BB0 15 Tx IN15 TA OUT1-
Rx OUT18 BA1/BB1
Rx OUT20 BA3/BB3
Rx OUT22 BA5/BB5
Rx OUT24
Rx OUT25
Rx OUT26 DE/DE
24bit
RxA/B 1- 47
BA1/BB1 19
Tx IN18 51
BA2/BB2 20 Tx IN19 53 Rx OUT19 BA2/BB2
BA3/BB3 22 Tx IN20 54
BA4/BB4 23 Tx IN21 TA OUT2+
BA5/BB5 24
HSYNC or RSVD1)
Tx IN22 1
27 Tx IN24 3
28 Tx IN25 TA OUT2-
DE/DE 30
Tx IN26 6
RxA/B 2+ 55 Rx OUT21 BA4/BB4
RxA/B 2- 5
RA6/RB6 50 Tx IN27 7 Rx OUT27 RA6/RB6
RA7/RB7 2 Tx IN5 34
GA6/GB6 8 Tx IN10 TA OUT3+
GA7/GB7 10
Tx IN11 42
RxA/B 3+ 41 Rx OUT10 GA6/GB6
BA6/BB6 16 Tx IN16 49
Rx OUT5 RA7/RB7
Rx OUT11 GA7/GB7
Rx OUT16 BA6/BB6
BA7/BB7 18 Tx IN17 TA OUT3- RxA/B 3- 50 Rx OUT17 BA7/BB7
RSVD 1) 25 Tx IN23 2
DCLK 31
TxCLK IN
TxCLK OUT+
TxCLK OUT- RxCLKA/B IN-
RxCLKA/B IN+
Rx OUT23 RSVD 1)
RxCLK OUT
26
TFT
RA5/RB5
HSYNC or RSVD1)
VSYNC or RSVD1)VSYNC or RSVD1)
DCLK
RA0～RA7, RB0～RB7 : Pixel R Data (7; MSB, 0; LSB)
GA0～GA7, GB0～GB7 : Pixel G Data (7; MSB, 0; LSB)
BA0～BA7, BB0～BB7 : Pixel B Data (7; MSB, 0; LSB)
DE : Data Enable
Note 1) RSVD(reserved) pins on the transmitter shall be tied to"H"or"L".
Page 7-4/7IPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No. ATD1227 2607 32FHD
Page 11
The LVDSSEL signal of CN3 pin No.7 specification is “H”.【LVDSSEL = H】
SIGNAL
TRANSMITTER
THC63LVDM83A
PIN
INPUT
INTERFACE CONNECTOR
TV Set
RA2/RB2 51 Tx IN0 27
RA3/RB3 52
RA4/RB4
54 RxA/B 0+
Tx IN1
TA OUT0+
RA5/RB5 55 Tx IN3
RA6/RB6 56
Tx IN4
TA OUT0- RxA/B 0-
GA2/GB2
4
Tx IN7
GA3/GB3 6 Tx IN8 38
GA4/GB4
GA5/GB5 11
7 Tx IN9
RxA/B 1+Tx IN12
GA6/GB6 12 Tx IN13 45
GA7/GB7
24bit
BA2/BB2
15 Tx IN15
TA OUT1BA3/BB3 19 Tx IN18 51 Rx OUT18 BA3/BB3
BA4/BB4 20
Tx IN19
RxA/B 1-
BA5/BB5 22 Tx IN20 54 Rx OUT20 BA5/BB5
BA6/BB6
Tx IN21 55
TA OUT2+ RxA/B 2+23
BA7/BB7 24 Tx IN22 1 Rx OUT22 BA7/BB7
27 Tx IN24 3 Rx OUT24
VSYNC or RSVD1)
28 5
Tx IN25
TA OUT2- RxA/B 2-
DE/DE 30 Tx IN26 6
Tx IN2750
RA1/RB1 2 Tx IN5 34 Rx OUT5 RA1/RB1
GA0/GB0 8
Tx IN10 41 Rx OUT10
TA OUT3+ RxA/B 3+
GA1/GB1 10 Tx IN11 42 Rx OUT11 GA1/GB1
BA1/BB1 18
Tx IN17
TA OUT3- RxA/B 3-
RSVD 1) 25 Tx IN23
DCLK 31
TxCLK IN
TxCLK OUT+ RxCLKA/B IN+
TxCLK OUT- RxCLKA/B IN-
RECEIVER
PIN OUTPUTTFT-LCD
TFT
CONTROL
INPUT
Rx OUT0 RA2/RB2
Rx OUT1
3029Rx OUT2
RA3/RB3
RA4/RB4Tx IN2
Rx OUT3 RA5/RB532
33
Rx OUT4
Rx OUT6
RA6/RB6
RA7/RB7RA7/RB7 3 35Tx IN6
37 Rx OUT7 GA2/GB2
Rx OUT8 GA3/GB3
39
Rx OUT9 GA4/GB4
43TA OUT1+
Rx OUT12 GA5/GB5
Rx OUT13 GA6/GB6
GA7/GB714 Tx IN14 46 Rx OUT14
47 Rx OUT15 BA2/BB2
53
Rx OUT19 BA4/BB4
Rx OUT21 BA6/BB6
HSYNC or RSVD1)HSYNC or RSVD1)
Rx OUT25
VSYNC or RSVD1)
Rx OUT26 DE/DE
7RA0/RB0 Rx OUT27
RA0/RB0
GA0/GB0
BA0/BB0BA0/BB0 16 Tx IN16 49
BA1/BB1
50
Rx OUT16
Rx OUT17
2 Rx OUT23 RSVD 1)
RxCLK OUT
26
DCLK
RA0～RA7, RB0～RB7 ：Pixel R Data (7; MSB, 0; LSB)
GA0～GA7, GB0～GB7 ：Pixel G Data (7; MSB, 0; LSB)
BA0～BA7, BB0～BB7 ：Pixel B Data (7; MSB, 0; LSB)
DE ：Data Enable
Note 1) RSVD(reserved) pins on the transmitter shall be tied to"H"or"L".
IPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No.
ATD1227
32FHD
7-5/7Page2607
Page 12
4. 5 Correspondence between input data and display image
Display data of adjacent one pixel is latched during one cycle of DCLK.
(1,1) (1,2) ODD pixel : RA0 - RA7 : R data
RA GA BA RB GB BB BA0 - BA7 : B data
EVEN pixel RB0 - RB7 : R data
GA0 - GA7 : G data
GB0 - GB7 : G data
BB0 - BB7 : B data
DCLK
1 , 1 1 , 2 1 , 3 1 , 1920
2 , 1 2 , 2 2 , 3 2 , 1920
3 , 1 3 , 2 3 , 3 3 , 1920
7080 , 1 1080 , 2 1080 , 3 1080 ,1920
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
RA0 - RA7
GA0 - GA7
BA0 - BA7
RB0 - RB7
GB0 - GB7
BB0 - BB7
DE
IPS Alpha Technology, Ltd. 7-6/7Date Jan. 30, 2009 Sheet No. PageATD1227 2607 32FHD
1,2 1,4 1,1918 2,2 2,41,1920
1,1919
InvalidInvalid 1,1 1,3 1,191 2,1 2,3
InvalidInvalid
Page 13
4. 6 Relationship between display colors and input signals
・
Red Data
Input R9 R8 R7 R6 R5 R4
Color
Black 000000
Red(1023) 1111111
Green(1023) 00000000
Color Cyan 000000
Magenta 1111111
Yellow 11111111
Black 00000000
Red (2) 00000000
Red(1022) 11111111
Black 00000000
Green (2) 00000000
Green(1022) 00000000
Black 00000000
Blue (2) 00000000
Blue (1022) 00000000
MSB LSB MSB LSB MSB LSB
: :::::::
: :::::::
: :::::::
0 0000000Blue (1023) 0 0 0
R1 R0
00
11
00
11
11
00
01
10
::
10
11
00
00
00
::
00
00
00
00
00
::
00
00
Green Data Bl ue Data
G2G3 B4 B3
0
0
0
0
1
1
0
0
1
1
0
1
1
000 0000000Red (1) 000
:
:
:
:
0
0
0
0
:
:
:
:
1
1
1
1
00 00000000
:
:
:
:
0
0
0
0
B7 B6 B5 B2G1 G0 B9 B8G7 G6 G5 G4R3 R2 G9 G8
000 0000000000000 00
00 00000000000 01 000
0 00000000011 111111
111 1110011000000 00000000Basic Blue(1023) 0 0
111 1111111111100 1100
11 11110111000 001 00011
0 00000000011 1111111
11 11111111111 111 1111111White 111
0 00000000000 00000000
00 00000000000 0
0 00000000000 00000000
::: ::::::::::::: ::::::Red : : :
:: ::::::::::: :: :::::
0 00000000000 000000
00 00000000000 01 0001111Red(1023) 1 1 1
0 00000000000 00000000
00 00001000000 0000 0000000Green (1) 0 0 0
0 00000000000 10000000
::: ::::::::::::: ::::::Green : : :
:: ::::::::::: :: :::::
0 00000000011 101111
00 00001000111 10 1110000Green(1023) 0 0 0
0 000000000
00 00000000000 0000 0000000Blue (1) 000
0 01000000000 00000000
::: ::::::::::::: ::::::Blue : : :
:: ::::::::::: :: :::::
1 11011111100 000000
11 11110111000 0
B1 B0
00
0
11
11
1
1
0
::
:
0
0
::
:
0
1
::
:
1
Note 1) Definition of gray scale :
Color(n)・・・
Number in parenthesis indicates gray scale level.
Larger n correspondsto brighter level.
2) Data : 1 : High, 0 : Low
ATD1227 7-7/7Page32FHD2607IPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No.
Page 14
5. INTERFACE TIMING
A
N
N
N
N
5. 1 LVDS receiver timing
tRPA2
tRPA3
tRPA4
tRPA5
tRPA6
tRPA0
tRPA1
RxA0
RxA1
RxA2
RxA3
GA2/0 RA7/5 RA6/4 RA5/3 RA4/2 RA3/1 RA2/0
BA3/1 BA2/0 GA7/5 GA6/4 GA5/3 GA4/2 GA3/1
DE
VSY
X BA1/7 BA0/6 GA1/7 GA0/6 RA1/7 RA0/6
HSY
C
BA7/5 BA6/4 BA5/3 BA4/2
C
Vdiff=0V
Vdiff=0V
Vdiff=0V
Vdiff=0V
tCLKA
CLK
tSC
CLKB Vdiff=0V
tCLKB
Vdiff=0V
tRPB2
tRPB3
tRPB4
tRPB5
tRPB6
tRPB0
tRPB1
RxB0
RxB1
RxB2
RxB3
GB2/0 RB7/5 RB6/4 RB5/3 RB4/2 RB3/1 RB2/0
BB3/1 BB2/0 GB7/5 GB6/4 GB5/3 GB4/2 GB3/1
DE
X BB1/7 BB0/6 GB1/7 GB0/6 RB1/7 RB0/6
VSY
HSY
C
BB7/5 BB6/4 BB5/3 BB4/2
C
Rx*0=(Rx*0+)-(Rx*0-) Rx*3=(Rx*3+)-(Rx*3-)
Rx*1=(Rx*1+)-(Rx*1-) CLK=(CLK+)-(CLK-)
Rx*2=(Rx*2+)-(Rx*2-)
ITEM SYMBOL Min. Typ. Max. UNIT NOTE
CLK
Frequency DCLK 64.0 67.5 72.5 MHz =1/tclk
CLK Skew tSC - 4.0 0 + 4.0 ns
0 data position tRP0 1/7tCLK - 0.4
1st data position tRP1 - 0.4
Rx*0
Rx*1
Rx*2
Rx*3
2nd data position tRP2 6/7tCLK - 0.4
3rd data position tRP3 5/7tCLK - 0.4 5/7tCLK
4th data position tRP4 4/7tCLK - 0.4 4/7tCLK
5th data position tRP5 3/7tCLK - 0.4 3/7tCLK
6th data position tRP6 2/7tCLK - 0.4 2/7tCLK 2/7tCLK + 0.4
1/7tCLK 1/7tCLK + 0.4
0 + 0.4
6/7tCLK 6/7tCLK + 0.4
5/7tCLK + 0.4
4/7tCLK + 0.4
3/7tCLK + 0.4
Vdiff=0V
Vdiff=0V
Vdiff=0V
Vdiff=0V
ns
8-1/3PageIPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No. ATD1227 2608 32FHD
Page 15
5. 2 Syncronization signal timing
DE
DE
tV
tVD
tH
tHD
DCLK
DE,
R0 - 7, G0 - 7, B0 - 7
Note 1) Reference level for each timing signal is 1.2 V unless it is stated on the chart, high level voltage(VIH)
and low level voltage(VIL) are defined as follows:
2) The timing of DCLK to other signals conforms to the specifications of LVDS transmitter.
I )50Hz 2pxl/clk
ITEM SYMBOL Min. Typ. Max. UNIT NOTE
Vertical Frequency fV 46 50 52 Hz
Vertical Period tV 1265 1338 1435 tH
DE
II )60Hz 2pxl/clk
DE
Vertical Valid tVD 1080 tH
Horizontal Frequency fH 65.1 66 69 kHz
Horizontal Period tH
Horizontal Valid tHD 960 tCLK
ITEM SYMBOL Min. Typ. Max. UNIT NOTE
Vertical Frequency fV 58 60 62 Hz
Vertical Period tV 1090 1116 1150 tH
Vertical Valid tVD 1080 tH
Horizontal Frequency fH 65.1 66 69 kHz
Horizontal Period tH
Horizontal Valid tHD 960 tCLK
1.2V
ＶIH ≧ 2.0 Ｖ ＶIL ≦ 0.8 Ｖ
1.2V
TSTC THTC
1.2V
990 1009
990 1009
1035 tCLK
1035 tCLK
8-2/3PageIPS Alpha Technology, Ltd. Date Jan. 30, 2009 Sheet No. ATD1227 2608 32FHD
Page 16
5.3 TIMING BETWEEN INTERFACE SIGNALS POWER SUPPLY
≦
Jan.30,2009
12V
11.4V
Power Supply
VDD
1V
0V
T1
T2
T3
T11
T10
10.8V
6.6V
T9
T8
LVDSSEL
LVDS Signals
VI
Back light
power supply
VBL
Back light
PWM
1)
0V
24V
0V
0V
Hi-Z
T12
21.6V
T4
Active Signal
T5
T13
Hi-Z
T6
T7
Back light
ON/OFF
0V
1)
0.5 10
350
10
200
200
Note 1) In all periods, the backlight ON/OFF signal voltage and the PWM signal voltage should be lower than
the backlight power supply voltage.
IPS Alpha Technology, Ltd. Date
≦ T1
≦ T2 ≦ T9
≦ T3 ≦ T10
≦ T4 ＜ T11
≦ T5 ≦ T12 ≦ T2-150
0
≦ T6 ≦ T13
0
≦ T7 Unit : ms
0
0
350
10
10
10
≦ T8
32FHD
Page 8-3/3Jan. 30, 2009 Sheet No. ATD1227 2608
Page 17
ATD12272609 32FHD
Jan.30,2009
6.
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9-3/3
ATD12272609 32FHD
Jan.30,2009
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