Page 1
Tentative
IPS Alpha Technology, Ltd.
TECHNICAL DATA
AX080B048G
CONTENTS
No.
COVER
RECORD OF REVISION
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
1
INITIAL OPTICAL CHARACTERISTICS
2
ELECTRICAL CHARACTERISTICS
3
BLOCK DIAGRAM
4
INTERFACE PIN ASSIGNMENT
5
INTERFACE TIMING
6
DIMENSIONAL OUTLINE
7
8
9
10
11
12
Item
ATD0934
ATD0934
ATD0934
ATD0934
ATD0934
ATD0934
ATD0934
ATD0934
ATD0934
ATD0934
Sheet No.
AX080B048G 2601
2602 AX080B048G
2603 AX080B048G
2604
2605
2606
2607
2608
2609
2610 AX080B048G
AX080B048G
AX080B048G
AX080B048G
AX080B048G
AX080B048G
AX080B048G
Page
1-1/1
2-1/1
3-1/1
4-1/1
5-1/2~ 2/2
6-1/1
7-1/1
8-1/6~ 6/6
9-1/3~ 3/3
10-1/3~ 3/3
IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No.
ATD0934 1-1/1 Page AX080B048G 2601
Page 2
Date
RECORD OF REVISION
The upper section : Before revision
The lower section : After revision
Sheet No.
Page
Summary
IPS Alpha Technology, Ltd. Page 2-1/1 Date Dec. 05, 2008 Sheet No.
ATD0934 2602 AX080B048G
Page 3
DESCRIPTION
The following specifications are applied to the following TFT module.
ote : Inverter for back light unit is built in this module.
Product Name : AX080B048G
General Specifications
Effective Display Area : (H)697.685×(V)392.256 (mm)
Number of Pixels : (H)1,366×(V)768 (pixels)
Pixel Pitch : (H)0.51075×(V)0.51075 (mm)
Color Pixel Arrangement : R+G+B Vertical Stripe
Display Mode : Transmissive Mode
Normally Black Mode
Top Polarizer Type : Semi-Glare
Number of Colors : 16,777,216 (colors)
Viewing Angle Range : Wide Version
(Horizontal & Vertical : 170°at φ =0°,90°, 180°,270°, CR≧ 10)
Input Signal : 1-channel LVDS (LVDS:Low Voltage Differential Signaling)
Back Light : 8pcs. of CCFL
External Dimensions : (H)760.0 x (V)450.0 x (t)48.0Max (mm)
Weight :TBD (g)
Sheet No. ATD0934 2603 AX080B048G IPS Alpha Technology, Ltd. Date Page 3-1/1 Dec. 05, 2008
Page 4
1. ABSOLUTE MAXIMUM RATINGS
1.1 Environmental Absolute Maximum Ratings
ITEM
Operating
Min. Max.
Min. Max.
Temperature 0 50
Humidity
Vibration
Shock
Corrosive Gas
- 4.9(0.5G) -
- 29.4(3G)
2)
Not Acceptable Not Acceptable
Note 1) Temperature and Humidity should be applied to the glass surface of a TFT module,
not to the system installed with a module.
The temperature at the center of rear surface should be less than 70℃ on the condition of operating.
The brightness of a CCFL tends to drop at low temperature. Besides, the life-time becomes shorter
at low temperature.
2) Ta≦ 40 ℃‥‥‥ Relative humidity should be less than 85%RH max. Dew is prohibited.
Ta> 40 ℃‥‥‥ Relative humidity should be lower than the moisture of the 85%RH at 40℃ .
3) Frequency of the vibration is between 15Hz and 100Hz. (Remove the resonance point)
4) Pulse width of the shock is 10 ms.
5) Long operation under low temperature may cause some portion of display area to be reddish for
several minutes after turning on the product.
However, it does not affect the characteristics and reliability of the product.
-20
Storage
60
2)
TBD
Unit
℃
%RH
m/s2
m/s2
-
Note
1),5)
1)
3)
4) - TBD
1.2 Electrical Absolute Maximum Ratings
(1)TFT Module Vss = 0 V
ITEM
Power Supply Voltage
Input Voltage for logic
Electrostatic Durability
SYMBOL Min.
V
V
DD
1
0
VESD0
VESD1
Max.
13.2
3.6 -0.3
±100
±8
Unit
Note
V
V1 )
V
kV
2),3)
2),4)
Note 1)It is applied to pixel data signal and clock signal.
2)Discharge Coefficient:200pF-250Ω , Environmental:25℃-70%RH
3)It is applied to I/F connector pins.
4)It is applied to the surface of a metallic bezel and a LCD panel.
(2) Back-light Inverter Vss = 0 V
ITEM
ON/OFF Control Input Voltage
Brightness Control Voltage
SYMBOL
Vin
ON/OFF
PWM 0
Min.
0
0
Max.
26.4 Input Voltage
6.0
3.3
Unit
V
V
V
Note
Date Dec. 05, 2008 Sheet No.
Page 4-1/1 IPS Alpha Technology, Ltd. AX080B048G 2604 ATD0934
Page 5
2. INITIAL OPTICAL CHARACTERISTICS
The following optical characteristics are measured under stable conditions. It takes about 30 minutes
to reach stable conditions. The measuring point is the center of display area unless otherwise noted.
The optical characteristics should be measured in a dark room or equivalent state.
Measuring equipment: CS-1000A, or equivalent
Ambient Temperature =25℃、 VDD=12.0V、 f V=60Hz、
VBL=24V、 PWM on duty =100%
ITEM SYMBOL CONDITION Min. Typ. Max. UNIT NOTE
Contrast Ratio
Response Time
CR
Rise ton - 8 20 ms
Fall toff - 6 20 ms 3)
500 1000
Brightness of white Bwh 350 450
Brightness uniformity Buni - - 30
Color
Chromaticity
( CIE)
Variation of
Color Position
(CIE)
Red
Green
Blue
White
Red
Green
Blue
White
χ 0.62
y
θ=0 ° 0.30 0.33 0.36
χ 1) 0.27 0.30
y
0.59
χ 0.12 0.15 0.18
y
0.04 0.07 0.10
χ 0.250 0.280
y
0.260 0.290 0.320
Δχ -
θ=+50°
Δχ --
Δy - - 0.04
Δχ - - 0.04
φ=0° 、90°
180°、 270°
1)
Δy --
Δχ - - 0.04
Δy - - 0.04
Contrast Ratio at 85° CR85 10
0.65 0.68
0.62 0.65
- 0.04
---
-- 2 )
-
0.33
0.310
0.04
0.04
cd/m
%
-
-
3)
2
4)
【 Gray scale
=255】
5)Δy - - 0.04
【 Gray scale
=255】
Estimated value
IPS Alpha Technology, Ltd. Date Dec. 05, 2008
Sheet No. ATD0934 2605 AX080B048G
Page 5-1/2
Page 6
Note 1) Definition of Viewing Angle
(12 o'clock)
φ=180°
X'
(9 o'clock)
φ=90°
Y
TFT - LCM
θ=0°
Z
θ
eye
φ
φ=0°
X(3o'clock)
2) Definition of Contrast Ratio (CR)
(Luminance at displaying WHITE)
CR=
(Luminance at displaying BLACK)
3) Definition of Response Time
Displaying
BLACK
Data Signal
Optical
Response
%
100
90
( Luminance)
10
4) Definition of Brightness Uniformi
(1) (2) (3)
10%
90%
(4) (5) (6)
(7) (8) (9)
10%
0
50%
50%
90%
: measuring points
Z'
φ=270°
Y'
(6 o'clock)
WHITE
ton toff
Display pattern is white (255 level) . The brightness
uniformity is defined as the following equation. Brightness at each
point is measured, and average, maximum and minimum
brightness is calculated.
Buni=
Bmax or Bmin - Bave
Bave
where, Bmax = Maximum brightness
Bmin = Minimum brightness
BLACK
×100
9
Σ (B(k))
Bave = Average brightness=
k=1
9
5) Variation of color position on CIE is defined as difference between colors at θ =0°and
atθ= +50°& φ =0°90°180°270°.
IPS Alpha Technology, Ltd.
Date
5-2/2 Dec. 05, 2008 Sheet No. Page ATD0934 2605 AX080B048G
Page 7
3. ELECTRICAL CHARACTERISTICS
3.1 TFT-LCD Module Ta=25℃、 Vss=0V
ITEM
Power supply Voltage
Power supply Current
Ripple voltage of power Supply
SYSTEM
DD
V
DD
I
V
DDR
Min.
11.4
-
-
Typ
12.0 12.6
0.39 0.6
-
Max
単位
V
A
350 m V
備考
1),2)
Note 1)fV=60.0Hz, fCLK=82MHz, VDD=12.0V, and Display pattern is white.
TFT Module
DC Ampere Met er
V
DD
V
SS
2) Current fuse is built in a module. Current capacity of power supply for VDD
should be larger than 4A, so that the fuse can be opened at the trouble of electrical circuit of module.
3.2 Back Light
ITEM
Symbol Min. Typ. Max. Unit
Notes
Input Voltage VBL
Input Current
Control Voltage
Brigthness Control
Input Voltage
PWM Duty
ON ON/OFF
OFF
Min. Brightness
Max. Brightness
Min. Brightness
Max. Brightness
IBL
ON/OFF
PWM
on-Duty
21.6
-
2.0
0
-
-
-
-
24.0 26.4
3.2
-
-
-A
5.0
0.8
0-
-
( 20 )
-
3.3
-
100
Note 3)This characteristics should be applied putting on the lamp about 60 minutes later
with ambient temperature. (Ta=25℃ ±2℃)
V
VBL=24V,
PWM on Duty100%
V
V
V
V
%
6-1/1 Page IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No. ATD0934 2606 AX080B048G
Page 8
4. BLOCK DIAGRAM
(1) TFT Module
Source
LVDS
Display data
Timing signal
DC Power supply
(2) Back light unit
DC power supply
ON/OFF Control
Brightness Control
CN2
CN1
Back light
Inverter
LVDS
Receiver
Tcon
DC/DC
Converte
Timing
Converter
S1 S2 S4098
G1
G2
TFT-LCD
Gate Drive
G768
Lamp8
Lamp7
Error Signal
Lamp 2
Lamp
1
IPS Alpha Technology, Ltd. 7-1/1 Date Dec. 05, 2008 Sheet No. Page ATD0934 2607 AX080B048G
Page 9
5. INTERFACE PIN ASSIGNMENT
5. 1 TFT-LCD MODULE
CN1:JAE FI-X30SSL-HF
(Matching connector : JAE FI-X30C2L)
Pin No. SYMBOL Description
1 VDD 1)
2 VDD
3 VDD
4 VDD
5 VSS
6 VSS
7 VSS
8 VSS
9I C
10 IC
11 VSS
12 Rx0-
13 Rx0+
14 VSS 2)
15 Rx1-
16 Rx1+
17 VSS 2)
18 Rx2-
19 Rx2+
20 VSS 2)
21 CLK-
22 CLK+
23 VSS 2)
24 Rx3- 3)
25 Rx3+
26 VSS 2)
27 IC
28 IC
29 IC
30 IC
Power Supply (typ.+12V)
GND(0V)
Internally Connected, Keep Open
GND(0V)
Pixel Data
GND(0V)
Pixel Data
GND(0V)
Pixel Data
GND(0V)
Pixel Data
GND(0V)
Pixel Data
GND(0V)
Internally Connected, Keep Open
Note
2)
3)
3)
3)
3)
Notes 1) All VDD pins shall be connected to +12.0V(Typ.).
2) All VSS pins shall be grounded. Metal bezel is internally connected to VSS.
3) Rx n+ and Rx n- (n=0,1,2,3) should be wired by twist-pairs or side-by-side FPC patterns, respectively.
IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No. 8-1/6 ATD0934 2608 AX080B048G Page
Page 10
5. 2 Back light unit
Inverter pin assignment
JST S14B-PHA-SM-TB(LF)(SN)
(Matching connector : JST PHR-14)
PIN No. SYMBOL DESCRIPTION
1
2
3
4
5
6 Vss
7
8 Vss
9 Vss
10 Vss
11
12
13
14
Note 1) All Vin pins shall be connected to +24.0V(Typ.).
2) All Vss pins shall be grounded. Metal bezel is internally connected to Vss.
Vin
Vin
Vin 1)
Vin
Vin
Vss
FAIL
ON/OFF
PWM
SELECT
Power supply ( Typ. +24.0V )
GND ( 0V ) 2)
Status output (Normal:GND abnormal:open )
High : LAMP ON(3.3V) Low : LAMP OFF
14pin low:0-3.3V pulse
(120-240Hz ON duty 20-100%)
Low:external pwm dimming
NOTE
Date IPS Alpha Technology, Ltd. Dec. 05, 2008 Sheet No.
ATD0934 2608
Page 8-2/6 AX080B048G
Page 11
5.3 BLOCK DIAGRAM OF INTERFACE
CN1
TFT-LCD ModuleSide TV set Side
TxIN
R0-R7
G0-G7
B0-B7
DE
DCLK
PLL
Host
Graphics
Controller
R0~ R7 : Pixel R Data
G0~ G7 : Pixel G Data
B0~ B7 : Pixel B Data
DE : Data Enable
Rx 0+
Rx 0Rx 1+
Rx 1-
Rx 2+
Rx 2-
Rx 3+
Rx 3-
CLK+
CLK-
(7; MSB, 0; LSB)
(7; MSB, 0; LSB)
(7; MSB, 0; LSB)
100Ω
100Ω
100Ω
100Ω
100Ω
Timing Converter
PLL
xOUT
R0‐R7
G0‐G7
B0‐B7
DE
DCLK
Timing
Converter
1) The system must have the transmitter to drive the module.
otes
2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line
when it is used differentially.
IPS Alpha Technology, Ltd. 8-3/6 Date Dec. 05, 2008 Sheet No. Page ATD0934 2608 AX080B048G
Page 12
5.4 LVDS INTERFACE
TRANSMITTER
THC63LVDM83A
PIN INPUT
54 Tx IN2 TA OUT0+ Rx 0+
55
56 Tx IN4
3 Tx IN6 TA OUT0-
4 Tx IN7
6 Tx IN8
11
-2 7
- 28 Tx IN25
30
R0~ R7 :Pixel B Data (7;MSB, 0;LSB)
G0~ G
B0~ B7 :Pixel B Data (7;MSB, 0;LSB)
DE :Data Enable
:Pixel B Data (7;MSB, 0;LSB)
24bit
SIGNAL
R2 51 Tx IN0
R3 52 Tx IN1 R3
R4
R5
R6
R7
G2
G3
G4 7 Tx IN9
G5
G6 12 Tx IN13
G7 14 Tx IN14
B2 15 Tx IN15
B3 19 Tx IN18
B4 20 Tx IN19
B5 22 Tx IN20
B6 23
B7 24 Tx IN22
R0 50
R1 2
G0 8 Tx IN10
G1 10
B0 16 Tx IN16
B1 18
RSVD 1) 25
DCLK 31
INTERFACE CONNECTOR
TV Set TFT-LCD
Tx IN3
Tx IN12 TA OUT1+
TA OUT1-
Tx IN21 TA OUT2+
Tx IN24
TA OUT2-
Tx IN26 DE
Tx IN27
Tx IN5
Tx IN11
Tx IN17
Tx IN23
TxCLK IN
TA OUT3-
TxCLK OUT- RxCLK IN-
Rx 0- R7
Rx 1+
Rx 1-
Rx 2+
Rx 2-
Rx 3-
RxCLK IN+ DCLK TxCLK OUT+
TFT
CONTROL
INPUT
R2
R4
R5
R6
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
not connected
not connected
DE
R0
R1
G0 Rx 3+ TA OUT3+
G1
B0
B1
not connected
Notes 1) RSVD(reserved) pins on the transmitter shall be tied to"H"or"L".
Page 8-4/6 IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No. ATD0934 2608 AX080B048G
Page 13
5.5 CORRESPONDENCE BETWEEN INPUT DATA AND DISPLAY IMAGE
Display data of adjacent one pixel is latched during one cycle of DCLK.
(1,1)
R B
B GR
1,1 1, 2 1,3 1,1366
2,1 2,2 2,3 2,1366
3,1 3,2 3,3 3,1366
pixel : R0~ R7 :R data
G0~ G7 :G data
B0 ~ B7 :B data
DCLK
R0~R7
G0~G7
B0~B7
DTM G
DE
768,1 768,2 768,3
~
~
~
INVALID 1, 1 1, 2 1, 1365 1,1366 2,1 2,2 INVALID
~
~
~
~
~
~
~
~
~
768,13 66
~
~
~
~
IPS Alpha Technology, Ltd. 8-5/6 Date Dec. 05, 2008 Sheet No. Page ATD0934 2608 AX080B048G
Page 14
5.6 RELATIONSHIP BETWEEN DISPLAY COLORS AND INPUT SIGNALS
Red Data Green Data Blue Data
R4 R3 R2 R1 R0 G7 G6 Input R7 R6 R5 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Color
Black
Red(255)
Green(255)
Basic Blue(255)
Color
Cyan 000000001111111111111111
MSB LSB MSB LSB MSB LSB
000000000000000000000000
111111110000000000000000
000000001111111100000000
000000000000000011111111
Magenta 111111110000000011111111
Yellow 111111111111111100000000
White 111111111111111111111111
Red
Black
Red (1)
Red (2)
: ::::::::::::::::::::::::
000000000000000000000000
000000010000000000000000
000000100000000000000000
: ::::::::::::::::::::::::
Green
Red(254)
Red(255)
Black
Green (1)
Green (2)
: ::::::::::::::::::::::::
111111100000000000000000
111111110000000000000000
000000000000000000000000
000000000000000100000000
000000000000001000000000
: ::::::::::::::::::::::::
Blue
Green(254)
Green(255)
Black
Blue (1)
Blue (2)
: ::::::::::::::::::::::::
000000001111111000000000
000000001111111100000000
000000000000000000000000
000000000000000000000001
000000000000000000000010
: ::::::::::::::::::::::::
Blue (254)
Blue (255)
000000000000000011111110
0000000000000000111 1 1111
Notes 1) Definition of gray scale:
Color(n)・・・・ Number in parenthesis indicates gray scale level. Larger n corresponds to brighter level.
2) Data: 1:High, 0:Low
Page 8-6/6 IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No. ATD0934 2608 AX080B048G
Page 15
6. INTERFACE TIMING
6.1 LVDS receiver timing
tRP2
tRP3
tRP4
tRP5
tRP6
tRP0
tRP1
Rx0
Rx1
Rx2
Rx3
G2 R7 R6 R5 R4 R3 R2
B3 B2 G7 G6 G5 G4 G3
DE
XB 1B 0G 1G 0R 1R 0
CLK
Rx0=(Rx0+)-(Rx0-)
Rx1=(Rx1+)-(Rx1-)
Rx2=(Rx2+)-(Rx2-)
Rx3=(Rx3+)-(Rx3-)
CLK=(CLK+)-(CLK-)
Item
RCLK
VSYNCHSY
Frequency
NC
B7 B6 B5 B4
Vdiff=0V
Symbol
tCLK
Min
65 82 85 MHz
tCLK
Typ Max
Vdiff=0V
Vdiff=0V
Vdiff=0V
Vdiff=0V
Unit
Rx0
Rx2
Rx3
0 data position
1st data position
2nd data position
3rd data position Rx1
4th data position tRIP4
5th data position
6th data position
tRIP0
tRIP1
tRIP2
tRIP3
tRIP5
tRIP6
1/7tCLK - 0.41
-0.41
6/7tCLK - 0.41
5/7tCLK - 0.41
4/7tCLK - 0.41
3/7tCLK - 0.41
2/7tCLK - 0.41
1/7tCLK
0
6/7tCLK
5/7tCLK
4/7tCLK
3/7tCLK
2/7tCLK
1/7tCLK + 0.41
+0.41
6/7tCLK + 0.41
5/7tCLK + 0.41
4/7tCLK + 0.41
3/7tCLK + 0.41
2/7tCLK + 0.41
ns
9-1/3 Page IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No. ATD0934 2609 AX080B048G
Page 16
6.2 SYNCRONIZATION SIGNAL TIMING
DE
DE
tV
tVD
tH
tHD
I )50Hz
DE
II )60Hz
DE
ITEM SYMBOL Min. Typ. Max. UNIT NOTE
Vertical frequency fV 48 50 52 Hz
Vertical period tV 773 860 1000 tH
Vertical valid tVD 768 tH
Horizontal frequency fH - 43 - kHz
Horizontal period tH
Horizontal valid tHD 1366 tCLK
ITEM SYMBOL Min. Typ. Max. UNIT NOTE
Vertical frequency fV 58 60 62 Hz
Vertical period tV 773 773 1000 tH
Vertical valid tVD 768 tH
Horizontal frequency fH - 46.4 - kHz
Horizontal period tH
Horizontal valid tHD 1366 tCLK
1400 1814
1400 1833
2000 tCLK
2000 tCLK
9-2/3 Page IPS Alpha Technology, Ltd. Date Dec. 05, 2008 Sheet No. ATD0934 2609 AX080B048G
Page 17
6.3 TIMING BETWEEN INTERFACE SIGNALS POWER SUPPLY
12V
Power Supply
VDD
0V
11.4V
1V
T1
T2
10.8V
6.6V
T9
T11
T10
LVDS Signals
VI
Back light
power supply
VBL
Back light
PWM
1)
Back light
ON/OFF
1)
0V
24V
0V
0V
0V
Hi-Z
T3
21.6V
T4
Active Signal
T5
T8
Hi-Z
T6
T7
0.5 10 0
≦ T1
350 0
≦ T2 ≦ T7
10 0
≦ T3 ≦ T8
200 0
≦ T4 ≦ T9
200 1000
≦ T5 ≦ T10
Note 1) In all periods, the backlight ON/OFF signal voltage and the PWM signal voltage should be lower than
the backlight power supply voltage.
≦ T6
10
< T11 Unit : ms
IPS Alpha Technology, Ltd. Date
Page 9-3/3 Dec. 05, 2008 Sheet No. ATD0934 2609 AX080B048G
Page 18
ATD09342610AX080B048G
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